drm/msm/dpu: rename dpu_hw_pipe_cdp_cfg to dpu_hw_cdp_cfg

Rename dpu_hw_pipe_cdp_cfg to dpu_hw_cdp_cfg and move it
to dpu_hw_utils file so that other modules in addition to
SSPP such as writeback can use it as all the fields can
be used by writeback as well.

Suggested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/483503/
Link: https://lore.kernel.org/r/1650984096-9964-6-git-send-email-quic_abhinavk@quicinc.com
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
index 09cdc35766534b180bb7d97a46ea270bfeced09e..0a0864dff78379cd8462a8aa0ec4e51c0c184432 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
@@ -627,7 +627,7 @@ static void dpu_hw_sspp_setup_qos_ctrl(struct dpu_hw_pipe *ctx,
 }
 
 static void dpu_hw_sspp_setup_cdp(struct dpu_hw_pipe *ctx,
-               struct dpu_hw_pipe_cdp_cfg *cfg,
+               struct dpu_hw_cdp_cfg *cfg,
                enum dpu_sspp_multirect_index index)
 {
        u32 idx;

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
index 92b071b78fdb6fcbd979ef6571022051a104ddd6..a81e16657d6151e59723f7f2f9ab5eb4ae3a46d9 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
@@ -192,22 +192,6 @@ enum {
        DPU_SSPP_CDP_PRELOAD_AHEAD_64
 };
 
-/**
- * struct dpu_hw_pipe_cdp_cfg : CDP configuration
- * @enable: true to enable CDP
- * @ubwc_meta_enable: true to enable ubwc metadata preload
- * @tile_amortize_enable: true to enable amortization control for tile format
- * @preload_ahead: number of request to preload ahead
- *     DPU_SSPP_CDP_PRELOAD_AHEAD_32,
- *     DPU_SSPP_CDP_PRELOAD_AHEAD_64
- */
-struct dpu_hw_pipe_cdp_cfg {
-       bool enable;
-       bool ubwc_meta_enable;
-       bool tile_amortize_enable;
-       u32 preload_ahead;
-};
-
 /**
  * struct dpu_hw_pipe_ts_cfg - traffic shaper configuration
  * @size: size to prefill in bytes, or zero to disable
@@ -359,7 +343,7 @@ struct dpu_hw_sspp_ops {
         * @index: rectangle index in multirect
         */
        void (*setup_cdp)(struct dpu_hw_pipe *ctx,
-                       struct dpu_hw_pipe_cdp_cfg *cfg,
+                       struct dpu_hw_cdp_cfg *cfg,
                        enum dpu_sspp_multirect_index index);
 };
 

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
index 39134754579e835c443459e3bce3cfce76e91697..a200df1617e86cf0c057886b9ab43ef84f51e990 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
@@ -298,6 +298,21 @@ struct dpu_drm_scaler_v2 {
        struct dpu_drm_de_v1 de;
 };
 
+/**
+ * struct dpu_hw_cdp_cfg : CDP configuration
+ * @enable: true to enable CDP
+ * @ubwc_meta_enable: true to enable ubwc metadata preload
+ * @tile_amortize_enable: true to enable amortization control for tile format
+ * @preload_ahead: number of request to preload ahead
+ *     DPU_*_CDP_PRELOAD_AHEAD_32,
+ *     DPU_*_CDP_PRELOAD_AHEAD_64
+ */
+struct dpu_hw_cdp_cfg {
+       bool enable;
+       bool ubwc_meta_enable;
+       bool tile_amortize_enable;
+       u32 preload_ahead;
+};
 
 u32 *dpu_hw_util_get_log_mask_ptr(void);
 

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
index c77c3d9dd384887760ee04bfc96fdaa6a51d8e9b..08b8c644a1cbc5f41adf9cd7b2db7b0e20a23b3a 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
@@ -1246,9 +1246,9 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane)
                                pstate->multirect_index);
 
                if (pdpu->pipe_hw->ops.setup_cdp) {
-                       struct dpu_hw_pipe_cdp_cfg cdp_cfg;
+                       struct dpu_hw_cdp_cfg cdp_cfg;
 
-                       memset(&cdp_cfg, 0, sizeof(struct dpu_hw_pipe_cdp_cfg));
+                       memset(&cdp_cfg, 0, sizeof(struct dpu_hw_cdp_cfg));
 
                        cdp_cfg.enable = pdpu->catalog->perf.cdp_cfg
                                        [DPU_PERF_CDP_USAGE_RT].rd_enable;