GENX(3DSTATE_CLEAR_PARAMS_length)];
};
-#if GFX_VERx10 == 120
+#if INTEL_NEEDS_WA_1808121037
enum iris_depth_reg_mode {
IRIS_DEPTH_REG_MODE_HW_DEFAULT = 0,
IRIS_DEPTH_REG_MODE_D16_1X_MSAA,
/* Is object level preemption enabled? */
bool object_preemption;
-#if GFX_VERx10 == 120
+#if INTEL_NEEDS_WA_1808121037
enum iris_depth_reg_mode depth_reg_mode;
#endif
struct iris_batch *batch,
const struct isl_surf *surf)
{
-#if GFX_VERx10 == 120
+#if INTEL_NEEDS_WA_1808121037
const bool is_d16_1x_msaa = surf->format == ISL_FORMAT_R16_UNORM &&
surf->samples == 1;
* settings while we change the registers.
*/
iris_emit_end_of_pipe_sync(batch,
- "Workaround: Stop pipeline for 14010455700",
+ "Workaround: Stop pipeline for Wa_1808121037",
PIPE_CONTROL_DEPTH_STALL |
PIPE_CONTROL_DEPTH_CACHE_FLUSH);
- /* Wa_14010455700
+ /* Wa_1808121037
*
* To avoid sporadic corruptions “Set 0x7010[9] when Depth Buffer
* Surface Format is D16_UNORM , surface type is not NULL & 1X_MSAA”.
{
struct iris_genx_state *genx = ice->state.genx;
-#if GFX_VERx10 == 120
+#if INTEL_NEEDS_WA_1808121037
genx->depth_reg_mode = IRIS_DEPTH_REG_MODE_UNKNOWN;
#endif