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ARM: tegra30: clk: Fix output_rate overflow
author
Mark Zhang
<markz@nvidia.com>
Tue, 16 Oct 2012 08:31:49 +0000
(16:31 +0800)
committer
Stephen Warren
<swarren@nvidia.com>
Tue, 16 Oct 2012 17:14:34 +0000
(11:14 -0600)
Change the type of variable from "unsigned long" to "u64".
This avoids the overflow while clock rate calculating.
Signed-off-by: Mark Zhang <markz@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
arch/arm/mach-tegra/tegra30_clocks.c
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diff --git
a/arch/arm/mach-tegra/tegra30_clocks.c
b/arch/arm/mach-tegra/tegra30_clocks.c
index
5cd502c
..
e9de5df
100644
(file)
--- a/
arch/arm/mach-tegra/tegra30_clocks.c
+++ b/
arch/arm/mach-tegra/tegra30_clocks.c
@@
-1199,7
+1199,7
@@
static long tegra30_pll_round_rate(struct clk_hw *hw, unsigned long rate,
{
struct clk_tegra *c = to_clk_tegra(hw);
unsigned long input_rate = *prate;
- u
nsigned long
output_rate = *prate;
+ u
64
output_rate = *prate;
const struct clk_pll_freq_table *sel;
struct clk_pll_freq_table cfg;
int mul;