* config/avr/avr.md: Add more patterns for mized-mode add and subtract

        (addsi3_zero_extend, subhi3_zero_extend1, subsi3_zero_extend).

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@49936 138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index e1984f4..e64cbb9 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2002-02-20  Torbjorn Granlund  <tege@swox.com>
+
+       * config/avr/avr.md: Add more patterns for mized-mode add and subtract
+        (addsi3_zero_extend, subhi3_zero_extend1, subsi3_zero_extend).
+
 Thu Feb 21 16:20:46 2002  Alexandre Oliva  <aoliva@redhat.com>
 
        * rtlanal.c (replace_rtx): Don't make a CONST_INT the operand of

diff --git a/gcc/config/avr/avr.md b/gcc/config/avr/avr.md
index 3c1432d..f432f0e 100644 (file)
--- a/gcc/config/avr/avr.md
+++ b/gcc/config/avr/avr.md
@@ -605,6 +605,19 @@
   [(set_attr "length" "4,3,3,4,5,5")
    (set_attr "cc" "set_n,set_n,set_czn,set_czn,set_n,set_n")])
 
+(define_insn "*addsi3_zero_extend"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+       (plus:SI (zero_extend:SI
+                 (match_operand:QI 1 "register_operand" "r"))
+                (match_operand:SI 2 "register_operand" "0")))]
+  ""
+  "add %A0,%1
+       adc %B0,__zero_reg__
+       adc %C0,__zero_reg__
+       adc %D0,__zero_reg__"
+  [(set_attr "length" "4")
+   (set_attr "cc" "set_n")])
+
 ;-----------------------------------------------------------------------------
 ; sub bytes
 (define_insn "subqi3"
@@ -629,6 +642,17 @@
   [(set_attr "length" "2,2")
    (set_attr "cc" "set_czn,set_czn")])
 
+(define_insn "*subhi3_zero_extend1"
+  [(set (match_operand:HI 0 "register_operand" "=r")
+       (minus:HI (match_operand:HI 1 "register_operand" "0")
+                 (zero_extend:HI
+                  (match_operand:QI 2 "register_operand" "r"))))]
+  ""
+  "sub %A0,%2
+       sbc %B0,__zero_reg__"
+  [(set_attr "length" "2")
+   (set_attr "cc" "set_n")])
+
 (define_insn "subsi3"
   [(set (match_operand:SI 0 "register_operand" "=r,d")
         (minus:SI (match_operand:SI 1 "register_operand" "0,0")
@@ -640,6 +664,19 @@
   [(set_attr "length" "4,4")
    (set_attr "cc" "set_czn,set_czn")])
 
+(define_insn "*subsi3_zero_extend"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+       (minus:SI (match_operand:SI 1 "register_operand" "0")
+                 (zero_extend:SI
+                  (match_operand:QI 2 "register_operand" "r"))))]
+  ""
+  "sub %A0,%2
+       sbc %B0,__zero_reg__
+       sbc %C0,__zero_reg__
+       sbc %D0,__zero_reg__"
+  [(set_attr "length" "4")
+   (set_attr "cc" "set_n")])
+
 ;******************************************************************************
 ; mul