ppc/85xx: Remove CONFIG_SYS_DDR_TLB_START
authorKumar Gala <galak@kernel.crashing.org>
Fri, 13 Nov 2009 15:09:10 +0000 (09:09 -0600)
committerKumar Gala <galak@kernel.crashing.org>
Tue, 5 Jan 2010 19:49:08 +0000 (13:49 -0600)
Now that we dynamically determine TLB CAM entries to use we dont need
CONFIG_SYS_DDR_TLB_START anymore.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
include/configs/MPC8572DS.h
include/configs/P1_P2_RDB.h
include/configs/P2020DS.h

index 41e4a6e..78b7369 100644 (file)
@@ -98,7 +98,6 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #define CONFIG_SYS_PCIE1_ADDR          (CONFIG_SYS_CCSRBAR+0xa000)
 
 /* DDR Setup */
-#define CONFIG_SYS_DDR_TLB_START 9
 #define CONFIG_VERY_BIG_RAM
 #define CONFIG_FSL_DDR2
 #undef CONFIG_FSL_DDR_INTERACTIVE
index ddfe7aa..15bfeef 100644 (file)
@@ -149,8 +149,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_SYS_DDR_ERR_DIS         0x00000000
 #define CONFIG_SYS_DDR_SBE             0x00FF0000
 
-#define CONFIG_SYS_DDR_TLB_START 9
-
 /*
  * Memory map
  *
index df9ab34..f4509bd 100644 (file)
@@ -101,7 +101,6 @@ extern unsigned long calculate_board_ddr_clk(unsigned long dummy);
 #define CONFIG_SYS_PCIE1_ADDR          (CONFIG_SYS_CCSRBAR+0xa000)
 
 /* DDR Setup */
-#define CONFIG_SYS_DDR_TLB_START 9
 #define CONFIG_VERY_BIG_RAM
 #define CONFIG_FSL_DDR3                1
 #undef CONFIG_FSL_DDR_INTERACTIVE