drm/i915/mtl: Add MeteorLake PCI IDs
authorRadhakrishna Sripada <radhakrishna.sripada@intel.com>
Fri, 8 Jul 2022 00:03:35 +0000 (17:03 -0700)
committerMatt Roper <matthew.d.roper@intel.com>
Fri, 8 Jul 2022 20:25:33 +0000 (13:25 -0700)
Add Meteorlake PCI IDs. Split into M, and P subplatforms.

v2: Update PCI id's
v3: Move id 7d60 under MTL_M(MattR)

Bspec: 55420

Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220708000335.2869311-3-radhakrishna.sripada@intel.com
drivers/gpu/drm/i915/i915_drv.h
drivers/gpu/drm/i915/i915_pci.c
drivers/gpu/drm/i915/intel_device_info.c
drivers/gpu/drm/i915/intel_device_info.h
include/drm/i915_pciids.h

index c21906a162a87780477619b98d840c55ebabffe9..3364a6e5169bdbe9f5c719cddd2285648dd02bb8 100644 (file)
@@ -1071,6 +1071,10 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define IS_PONTEVECCHIO(dev_priv) IS_PLATFORM(dev_priv, INTEL_PONTEVECCHIO)
 #define IS_METEORLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_METEORLAKE)
 
+#define IS_METEORLAKE_M(dev_priv) \
+       IS_SUBPLATFORM(dev_priv, INTEL_METEORLAKE, INTEL_SUBPLATFORM_M)
+#define IS_METEORLAKE_P(dev_priv) \
+       IS_SUBPLATFORM(dev_priv, INTEL_METEORLAKE, INTEL_SUBPLATFORM_P)
 #define IS_DG2_G10(dev_priv) \
        IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G10)
 #define IS_DG2_G11(dev_priv) \
index 056931393a899d78928aeb1c16c5de159587159b..3e3e95c7a63f10e20ab13febe3cc30b5eea42069 100644 (file)
@@ -1218,6 +1218,7 @@ static const struct pci_device_id pciidlist[] = {
        INTEL_RPLP_IDS(&adl_p_info),
        INTEL_DG2_IDS(&dg2_info),
        INTEL_ATS_M_IDS(&ats_m_info),
+       INTEL_MTL_IDS(&mtl_info),
        {0, 0, 0}
 };
 MODULE_DEVICE_TABLE(pci, pciidlist);
index 27c343316afaaf55914b0ca4bd4f3f3cce568868..d98fbbd589aaa43669187b6e937dbe701aed5228 100644 (file)
@@ -202,6 +202,14 @@ static const u16 subplatform_g12_ids[] = {
        INTEL_DG2_G12_IDS(0),
 };
 
+static const u16 subplatform_m_ids[] = {
+       INTEL_MTL_M_IDS(0),
+};
+
+static const u16 subplatform_p_ids[] = {
+       INTEL_MTL_P_IDS(0),
+};
+
 static bool find_devid(u16 id, const u16 *p, unsigned int num)
 {
        for (; num; num--, p++) {
@@ -256,6 +264,12 @@ void intel_device_info_subplatform_init(struct drm_i915_private *i915)
        } else if (find_devid(devid, subplatform_g12_ids,
                              ARRAY_SIZE(subplatform_g12_ids))) {
                mask = BIT(INTEL_SUBPLATFORM_G12);
+       } else if (find_devid(devid, subplatform_m_ids,
+                             ARRAY_SIZE(subplatform_m_ids))) {
+               mask = BIT(INTEL_SUBPLATFORM_M);
+       } else if (find_devid(devid, subplatform_p_ids,
+                             ARRAY_SIZE(subplatform_p_ids))) {
+               mask = BIT(INTEL_SUBPLATFORM_P);
        }
 
        GEM_BUG_ON(mask & ~INTEL_SUBPLATFORM_MASK);
index 68f7c231ef3e24dcac6a9917e4678a1fd1c46d07..677fb68f172680880942948d5d17130cb26b311e 100644 (file)
@@ -127,6 +127,10 @@ enum intel_platform {
  */
 #define INTEL_SUBPLATFORM_N    1
 
+/* MTL */
+#define INTEL_SUBPLATFORM_M    0
+#define INTEL_SUBPLATFORM_P    1
+
 enum intel_ppgtt_type {
        INTEL_PPGTT_NONE = I915_GEM_PPGTT_NONE,
        INTEL_PPGTT_ALIASING = I915_GEM_PPGTT_ALIASING,
index 1bd0420a213d792c2438c83196f46240029e019f..278031aa2e848377fc32e920b16f06f87ec4f8ac 100644 (file)
 #define INTEL_ATS_M_IDS(info) \
        INTEL_ATS_M150_IDS(info), \
        INTEL_ATS_M75_IDS(info)
+/* MTL */
+#define INTEL_MTL_M_IDS(info) \
+       INTEL_VGA_DEVICE(0x7D40, info), \
+       INTEL_VGA_DEVICE(0x7D60, info)
+
+#define INTEL_MTL_P_IDS(info) \
+       INTEL_VGA_DEVICE(0x7D45, info), \
+       INTEL_VGA_DEVICE(0x7D55, info), \
+       INTEL_VGA_DEVICE(0x7DD5, info)
+
+#define INTEL_MTL_IDS(info) \
+       INTEL_MTL_M_IDS(info), \
+       INTEL_MTL_P_IDS(info)
 
 #endif /* _I915_PCIIDS_H */