MIPS: Octeon: Disable CVMSEG by default on other platforms
authorJiaxun Yang <jiaxun.yang@flygoat.com>
Tue, 4 Apr 2023 09:33:49 +0000 (10:33 +0100)
committerThomas Bogendoerfer <tsbogend@alpha.franken.de>
Wed, 5 Apr 2023 07:45:09 +0000 (09:45 +0200)
QEMU can't emulate CVMSEG on generic platform for now.

Just disable it by default.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
arch/mips/cavium-octeon/Kconfig

index c1899f1..450e979 100644 (file)
@@ -14,7 +14,8 @@ config CAVIUM_CN63XXP1
 config CAVIUM_OCTEON_CVMSEG_SIZE
        int "Number of L1 cache lines reserved for CVMSEG memory"
        range 0 54
-       default 1
+       default 0 if !CAVIUM_OCTEON_SOC
+       default 1 if CAVIUM_OCTEON_SOC
        help
          CVMSEG LM is a segment that accesses portions of the dcache as a
          local memory; the larger CVMSEG is, the smaller the cache is.