u16 sync_ctrl1;
u8 temp;
- if ((qn == 0) && (qn_plus_1 == 0))
+ if (qn == 0 && qn_plus_1 == 0)
return 0;
switch (pll) {
return err;
/* PLL5 can have OUT8 as second additional output. */
- if ((pll == 5) && (qn_plus_1 != 0)) {
+ if (pll == 5 && qn_plus_1 != 0) {
err = idtcm_read(idtcm, 0, HW_Q8_CTRL_SPARE,
&temp, sizeof(temp));
if (err)
}
/* PLL6 can have OUT11 as second additional output. */
- if ((pll == 6) && (qn_plus_1 != 0)) {
+ if (pll == 6 && qn_plus_1 != 0) {
err = idtcm_read(idtcm, 0, HW_Q11_CTRL_SPARE,
&temp, sizeof(temp));
if (err)
}
}
- if ((qn != 0) || (qn_plus_1 != 0))
+ if (qn != 0 || qn_plus_1 != 0)
err = _sync_pll_output(idtcm, pll, sync_src, qn,
qn_plus_1);
err = 0;
/* Top (status registers) and bottom are read-only */
- if ((regaddr < GPIO_USER_CONTROL)
- || (regaddr >= SCRATCH))
+ if (regaddr < GPIO_USER_CONTROL || regaddr >= SCRATCH)
continue;
/* Page size 128, last 4 bytes of page skipped */
- if (((loaddr > 0x7b) && (loaddr <= 0x7f))
- || loaddr > 0xfb)
+ if ((loaddr > 0x7b && loaddr <= 0x7f) || loaddr > 0xfb)
continue;
err = idtcm_write(idtcm, regaddr, 0, &val, sizeof(val));
u16 dpll;
u16 out0 = 0, out1 = 0;
- if ((qn == 0) && (qn_plus_1 == 0))
+ if (qn == 0 && qn_plus_1 == 0)
return 0;
switch (pll) {
}
}
- if ((qn != 0) || (qn_plus_1 != 0))
+ if (qn != 0 || qn_plus_1 != 0)
err = _enable_pll_tod_sync(idtcm, pll, sync_src, qn,
qn_plus_1);
if (err)