clk: renesas: rzg2l: Wait for status bit of SD mux before continuing

[ Upstream commit 549f4ae2601f968e2474c6031fb4799468882f64 ]

The hardware user manual for RZ/G2L (r01uh0914ej0130-rzg2l-rzg2lc.pdf,
chapter 7.4.7 Procedure for Switching Clocks by the Dynamic Switching
Frequency Selectors) specifies that we need to check CPG_PL2SDHI_DSEL
for SD clock switching status.

Fixes: eaff33646f4cb ("clk: renesas: rzg2l: Add SDHI clk mux support")
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230929053915.1530607-3-claudiu.beznea@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c
index 2c87757..85e49f4 100644 (file)
--- a/drivers/clk/renesas/rzg2l-cpg.c
+++ b/drivers/clk/renesas/rzg2l-cpg.c
@@ -192,7 +192,8 @@ static int rzg2l_cpg_sd_clk_mux_set_parent(struct clk_hw *hw, u8 index)
        u32 off = GET_REG_OFFSET(hwdata->conf);
        u32 shift = GET_SHIFT(hwdata->conf);
        const u32 clk_src_266 = 2;
-       u32 bitmask;
+       u32 msk, val, bitmask;
+       int ret;
 
        /*
         * As per the HW manual, we should not directly switch from 533 MHz to
@@ -206,14 +207,10 @@ static int rzg2l_cpg_sd_clk_mux_set_parent(struct clk_hw *hw, u8 index)
         * the index to value mapping is done by adding 1 to the index.
         */
        bitmask = (GENMASK(GET_WIDTH(hwdata->conf) - 1, 0) << shift) << 16;
+       msk = off ? CPG_CLKSTATUS_SELSDHI1_STS : CPG_CLKSTATUS_SELSDHI0_STS;
        if (index != clk_src_266) {
-               u32 msk, val;
-               int ret;
-
                writel(bitmask | ((clk_src_266 + 1) << shift), priv->base + off);
 
-               msk = off ? CPG_CLKSTATUS_SELSDHI1_STS : CPG_CLKSTATUS_SELSDHI0_STS;
-
                ret = readl_poll_timeout(priv->base + CPG_CLKSTATUS, val,
                                         !(val & msk), 100,
                                         CPG_SDHI_CLK_SWITCH_STATUS_TIMEOUT_US);
@@ -225,7 +222,13 @@ static int rzg2l_cpg_sd_clk_mux_set_parent(struct clk_hw *hw, u8 index)
 
        writel(bitmask | ((index + 1) << shift), priv->base + off);
 
-       return 0;
+       ret = readl_poll_timeout(priv->base + CPG_CLKSTATUS, val,
+                                !(val & msk), 100,
+                                CPG_SDHI_CLK_SWITCH_STATUS_TIMEOUT_US);
+       if (ret)
+               dev_err(priv->dev, "failed to switch clk source\n");
+
+       return ret;
 }
 
 static u8 rzg2l_cpg_sd_clk_mux_get_parent(struct clk_hw *hw)