ARM: 8862/1: errata: 814220-B-Cache maintenance by set/way operations can execute...

The v7 ARM states that all cache and branch predictor maintenance operations
that do not specify an address execute, relative to each other, in program
order. However, because of this erratum, an L2 set/way cache maintenance
operation can overtake an L1 set/way cache maintenance operation, this would
cause the data corruption.

This ERRATA affected the Cortex-A7 and present in r0p2, r0p3, r0p4, r0p5.

This patch is the SW workaround by adding a DSB before changing cache levels as
the ARM ERRATA: ARM/MP: 814220 told in the ARM ERRATA documentation.

Signed-off-by: Jason Liu <r64343@freescale.com>
Signed-off-by: Benjamin Gaignard <benjamin.gaignard@linaro.org>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 96377e3cd3d8508421c9e5f5120fb5d74bcbd2c9..c87cc9a6fb3c6c0c8fdd607b438007e8cb447d02 100644 (file)
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1250,6 +1250,18 @@ config PCI_HOST_ITE8152
        default y
        select DMABOUNCE
 
+config ARM_ERRATA_814220
+       bool "ARM errata: Cache maintenance by set/way operations can execute out of order"
+       depends on CPU_V7
+       help
+         The v7 ARM states that all cache and branch predictor maintenance
+         operations that do not specify an address execute, relative to
+         each other, in program order.
+         However, because of this erratum, an L2 set/way cache maintenance
+         operation can overtake an L1 set/way cache maintenance operation.
+         This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3,
+         r0p4, r0p5.
+
 endmenu
 
 menu "Kernel Features"

diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S
index db3986708c8a99509fb6eb7e14b5e72c52234e20..ea05d6fd53a116dad8e386daaca21829b0b2c920 100644 (file)
--- a/arch/arm/mm/cache-v7.S
+++ b/arch/arm/mm/cache-v7.S
@@ -171,6 +171,9 @@ loop2:
 skip:
        add     r10, r10, #2                    @ increment cache number
        cmp     r3, r10
+#ifdef CONFIG_ARM_ERRATA_814220
+       dsb
+#endif
        bgt     flush_levels
 finished:
        mov     r10, #0                         @ switch back to cache level 0