}
};
-#define GEN6_VME_KERNEL_NUMBER ARRAY_ELEMS(gen6_vme_kernels)
-
static void
gen6_vme_set_common_surface_tiling(struct i965_surface_state *ss, unsigned int tiling)
{
for (i = 0; i < GEN6_VME_KERNEL_NUMBER; i++) {
struct i965_kernel *kernel;
- kernel = &gen6_vme_kernels[i];
+ kernel = &vme_context->vme_kernels[i];
assert(sizeof(*desc) == 32);
/*Setup the descritor table*/
memset(desc, 0, sizeof(*desc));
struct i965_driver_data *i965 = i965_driver_data(ctx);
int i;
+ memcpy(vme_context->vme_kernels, gen6_vme_kernels, sizeof(vme_context->vme_kernels));
+
for (i = 0; i < GEN6_VME_KERNEL_NUMBER; i++) {
/*Load kernel into GPU memory*/
- struct i965_kernel *kernel = &gen6_vme_kernels[i];
+ struct i965_kernel *kernel = &vme_context->vme_kernels[i];
kernel->bo = dri_bo_alloc(i965->intel.bufmgr,
kernel->name,
for (i = 0; i < GEN6_VME_KERNEL_NUMBER; i++) {
/*Load kernel into GPU memory*/
- struct i965_kernel *kernel = &gen6_vme_kernels[i];
+ struct i965_kernel *kernel = &vme_context->vme_kernels[i];
dri_bo_unreference(kernel->bo);
kernel->bo = NULL;
#define MAX_INTERFACE_DESC_GEN6 32
#define MAX_MEDIA_SURFACES_GEN6 34
+#define GEN6_VME_KERNEL_NUMBER 2
+
struct encode_state;
struct gen6_encoder_context;
unsigned int size_block; /* in bytes */
unsigned int pitch;
} vme_output;
+
+ struct i965_kernel vme_kernels[GEN6_VME_KERNEL_NUMBER];
};
VAStatus gen6_vme_pipeline(VADriverContextP ctx,
#include "i965_media_h264.h"
#include "i965_media.h"
-extern struct i965_kernel *h264_avc_kernels;
-
/* On Ironlake */
#include "shaders/h264/mc/export.inc.gen5"
avc_hw_scoreboard_context->surface.total_mbs = i965_h264_context->avc_it_command_mb_info.mbs * 2;
dri_bo_unreference(avc_hw_scoreboard_context->hw_kernel.bo);
- avc_hw_scoreboard_context->hw_kernel.bo = h264_avc_kernels[H264_AVC_COMBINED].bo;
+ avc_hw_scoreboard_context->hw_kernel.bo = i965_h264_context->avc_kernels[H264_AVC_COMBINED].bo;
assert(avc_hw_scoreboard_context->hw_kernel.bo != NULL);
dri_bo_reference(avc_hw_scoreboard_context->hw_kernel.bo);
unsigned int pad3;
};
-extern struct i965_kernel *h264_avc_kernels;
-
#define NUM_AVC_ILDB_INTERFACES ARRAY_ELEMS(avc_ildb_kernel_offset_gen4)
static unsigned long *avc_ildb_kernel_offset = NULL;
int kernel_offset = avc_ildb_kernel_offset[i];
memset(desc, 0, sizeof(*desc));
desc->desc0.grf_reg_blocks = 7;
- desc->desc0.kernel_start_pointer = (h264_avc_kernels[H264_AVC_COMBINED].bo->offset + kernel_offset) >> 6; /* reloc */
+ desc->desc0.kernel_start_pointer = (i965_h264_context->avc_kernels[H264_AVC_COMBINED].bo->offset + kernel_offset) >> 6; /* reloc */
desc->desc1.const_urb_entry_read_offset = 0;
desc->desc1.const_urb_entry_read_len = ((i == AVC_ILDB_ROOT_Y_ILDB_FRAME ||
i == AVC_ILDB_ROOT_Y_ILDB_FIELD ||
I915_GEM_DOMAIN_INSTRUCTION, 0,
desc->desc0.grf_reg_blocks + kernel_offset,
i * sizeof(*desc) + offsetof(struct i965_interface_descriptor, desc0),
- h264_avc_kernels[H264_AVC_COMBINED].bo);
+ i965_h264_context->avc_kernels[H264_AVC_COMBINED].bo);
dri_bo_emit_reloc(bo,
I915_GEM_DOMAIN_INSTRUCTION, 0,
#include "intel_driver.h"
-#include "i965_render.h"
-
#define I965_MAX_PROFILES 11
#define I965_MAX_ENTRYPOINTS 5
#define I965_MAX_CONFIG_ATTRIBUTES 10
struct hw_context *(*enc_hw_context_init)(VADriverContextP, VAProfile);
};
+
+#include "i965_render.h"
+
struct i965_driver_data
{
struct intel_driver_data intel;
}
};
-#define NUM_H264_AVC_KERNELS (sizeof(h264_avc_kernels_gen4) / sizeof(h264_avc_kernels_gen4[0]))
-struct i965_kernel *h264_avc_kernels = NULL;
-
#define NUM_AVC_MC_INTERFACES (sizeof(avc_mc_kernel_offset_gen4) / sizeof(avc_mc_kernel_offset_gen4[0]))
static unsigned long *avc_mc_kernel_offset = NULL;
static void
i965_media_h264_interface_descriptor_remap_table(VADriverContextP ctx, struct i965_media_context *media_context)
{
+ struct i965_h264_context *i965_h264_context = (struct i965_h264_context *)media_context->private_context;
struct i965_interface_descriptor *desc;
int i;
dri_bo *bo;
int kernel_offset = avc_mc_kernel_offset[i];
memset(desc, 0, sizeof(*desc));
desc->desc0.grf_reg_blocks = 7;
- desc->desc0.kernel_start_pointer = (h264_avc_kernels[H264_AVC_COMBINED].bo->offset + kernel_offset) >> 6; /* reloc */
+ desc->desc0.kernel_start_pointer = (i965_h264_context->avc_kernels[H264_AVC_COMBINED].bo->offset + kernel_offset) >> 6; /* reloc */
desc->desc1.const_urb_entry_read_offset = 0;
desc->desc1.const_urb_entry_read_len = 2;
desc->desc3.binding_table_entry_count = 0;
I915_GEM_DOMAIN_INSTRUCTION, 0,
desc->desc0.grf_reg_blocks + kernel_offset,
i * sizeof(*desc) + offsetof(struct i965_interface_descriptor, desc0),
- h264_avc_kernels[H264_AVC_COMBINED].bo);
+ i965_h264_context->avc_kernels[H264_AVC_COMBINED].bo);
dri_bo_emit_reloc(bo,
I915_GEM_DOMAIN_INSTRUCTION, 0,
dri_bo_unreference(i965_h264_context->avc_it_command_mb_info.bo);
dri_bo_unreference(i965_h264_context->avc_it_data.bo);
dri_bo_unreference(i965_h264_context->avc_ildb_data.bo);
- free(i965_h264_context);
- *data = NULL;
for (i = 0; i < NUM_H264_AVC_KERNELS; i++) {
- struct i965_kernel *kernel = &h264_avc_kernels[i];
+ struct i965_kernel *kernel = &i965_h264_context->avc_kernels[i];
dri_bo_unreference(kernel->bo);
kernel->bo = NULL;
}
+
+ free(i965_h264_context);
+ *data = NULL;
}
void
i965_h264_context = calloc(1, sizeof(struct i965_h264_context));
/* kernel */
- if (h264_avc_kernels == NULL) {
- assert(NUM_H264_AVC_KERNELS == (sizeof(h264_avc_kernels_gen5) /
- sizeof(h264_avc_kernels_gen5[0])));
- assert(NUM_AVC_MC_INTERFACES == (sizeof(avc_mc_kernel_offset_gen5) /
- sizeof(avc_mc_kernel_offset_gen5[0])));
-
- if (IS_IRONLAKE(i965->intel.device_id)) {
- h264_avc_kernels = h264_avc_kernels_gen5;
- avc_mc_kernel_offset = avc_mc_kernel_offset_gen5;
- intra_kernel_header = &intra_kernel_header_gen5;
- i965_h264_context->use_avc_hw_scoreboard = 1;
- i965_h264_context->use_hw_w128 = 1;
- } else {
- h264_avc_kernels = h264_avc_kernels_gen4;
- avc_mc_kernel_offset = avc_mc_kernel_offset_gen4;
- intra_kernel_header = &intra_kernel_header_gen4;
- i965_h264_context->use_avc_hw_scoreboard = 0;
- i965_h264_context->use_hw_w128 = 0;
- }
+ assert(NUM_H264_AVC_KERNELS == (sizeof(h264_avc_kernels_gen5) /
+ sizeof(h264_avc_kernels_gen5[0])));
+ assert(NUM_AVC_MC_INTERFACES == (sizeof(avc_mc_kernel_offset_gen5) /
+ sizeof(avc_mc_kernel_offset_gen5[0])));
+ if (IS_IRONLAKE(i965->intel.device_id)) {
+ memcpy(i965_h264_context->avc_kernels, h264_avc_kernels_gen5, sizeof(i965_h264_context->avc_kernels));
+ avc_mc_kernel_offset = avc_mc_kernel_offset_gen5;
+ intra_kernel_header = &intra_kernel_header_gen5;
+ i965_h264_context->use_avc_hw_scoreboard = 1;
+ i965_h264_context->use_hw_w128 = 1;
+ } else {
+ memcpy(i965_h264_context->avc_kernels, h264_avc_kernels_gen4, sizeof(i965_h264_context->avc_kernels));
+ avc_mc_kernel_offset = avc_mc_kernel_offset_gen4;
+ intra_kernel_header = &intra_kernel_header_gen4;
+ i965_h264_context->use_avc_hw_scoreboard = 0;
+ i965_h264_context->use_hw_w128 = 0;
+ }
- for (i = 0; i < NUM_H264_AVC_KERNELS; i++) {
- struct i965_kernel *kernel = &h264_avc_kernels[i];
- kernel->bo = dri_bo_alloc(i965->intel.bufmgr,
- kernel->name,
- kernel->size, 0x1000);
- assert(kernel->bo);
- dri_bo_subdata(kernel->bo, 0, kernel->size, kernel->bin);
- }
+ for (i = 0; i < NUM_H264_AVC_KERNELS; i++) {
+ struct i965_kernel *kernel = &i965_h264_context->avc_kernels[i];
+ kernel->bo = dri_bo_alloc(i965->intel.bufmgr,
+ kernel->name,
+ kernel->size, 0x1000);
+ assert(kernel->bo);
+ dri_bo_subdata(kernel->bo, 0, kernel->size, kernel->bin);
}
for (i = 0; i < 16; i++) {
H264_AVC_NULL
};
+#define NUM_H264_AVC_KERNELS 2
+
struct i965_h264_context
{
struct {
VASurfaceID surface_id;
int frame_store_id;
} fsid_list[16];
+
+ struct i965_kernel avc_kernels[NUM_H264_AVC_KERNELS];
};
void i965_media_h264_decode_init(VADriverContextP ctx, struct decode_state *decode_state, struct i965_media_context *media_context);
*
*/
+#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <assert.h>
}
};
-static struct i965_kernel *mpeg2_vld_kernels = NULL;
-
-#define NUM_MPEG2_VLD_KERNELS (sizeof(mpeg2_vld_kernels_gen4)/sizeof(mpeg2_vld_kernels_gen4[0]))
-
static void
i965_media_mpeg2_surface_state(VADriverContextP ctx,
int index,
static void
i965_media_mpeg2_interface_descriptor_remap_table(VADriverContextP ctx, struct i965_media_context *media_context)
{
+ struct i965_mpeg2_context *i965_mpeg2_context = (struct i965_mpeg2_context *)media_context->private_context;
struct i965_interface_descriptor *desc;
int i;
dri_bo *bo;
for (i = 0; i < NUM_MPEG2_VLD_KERNELS; i++) {
memset(desc, 0, sizeof(*desc));
desc->desc0.grf_reg_blocks = 15;
- desc->desc0.kernel_start_pointer = mpeg2_vld_kernels[i].bo->offset >> 6; /* reloc */
+ desc->desc0.kernel_start_pointer = i965_mpeg2_context->vld_kernels[i].bo->offset >> 6; /* reloc */
desc->desc1.const_urb_entry_read_offset = 0;
desc->desc1.const_urb_entry_read_len = 30;
desc->desc3.binding_table_entry_count = 0;
I915_GEM_DOMAIN_INSTRUCTION, 0,
desc->desc0.grf_reg_blocks,
i * sizeof(*desc) + offsetof(struct i965_interface_descriptor, desc0),
- mpeg2_vld_kernels[i].bo);
+ i965_mpeg2_context->vld_kernels[i].bo);
dri_bo_emit_reloc(bo,
I915_GEM_DOMAIN_INSTRUCTION, 0,
struct decode_state *decode_state,
struct i965_media_context *media_context)
{
+ struct i965_mpeg2_context *i965_mpeg2_context = (struct i965_mpeg2_context *)media_context->private_context;
int i, j;
unsigned char *constant_buffer;
unsigned char *qmx;
lib_reloc_offset = 128 + sizeof(idct_table);
lib_reloc = (unsigned int *)(constant_buffer + lib_reloc_offset);
for (i = 0; i < 8; i++) {
- lib_reloc[i] = mpeg2_vld_kernels[LIB_INTERFACE].bo->offset;
+ lib_reloc[i] = i965_mpeg2_context->vld_kernels[LIB_INTERFACE].bo->offset;
dri_bo_emit_reloc(media_context->curbe.bo,
I915_GEM_DOMAIN_INSTRUCTION, 0,
0,
lib_reloc_offset + i * sizeof(unsigned int),
- mpeg2_vld_kernels[LIB_INTERFACE].bo);
+ i965_mpeg2_context->vld_kernels[LIB_INTERFACE].bo);
}
dri_bo_unmap(media_context->curbe.bo);
static void
i965_media_mpeg2_free_private_context(void **data)
{
+ struct i965_mpeg2_context *i965_mpeg2_context = *data;
int i;
+ if (i965_mpeg2_context == NULL)
+ return;
+
for (i = 0; i < NUM_MPEG2_VLD_KERNELS; i++) {
- struct i965_kernel *kernel = &mpeg2_vld_kernels[i];
+ struct i965_kernel *kernel = &i965_mpeg2_context->vld_kernels[i];
dri_bo_unreference(kernel->bo);
kernel->bo = NULL;
}
- mpeg2_vld_kernels = NULL;
+ free(i965_mpeg2_context);
+ *data = NULL;
}
void
i965_media_mpeg2_dec_context_init(VADriverContextP ctx, struct i965_media_context *media_context)
{
struct i965_driver_data *i965 = i965_driver_data(ctx);
+ struct i965_mpeg2_context *i965_mpeg2_context;
int i;
+ i965_mpeg2_context = calloc(1, sizeof(struct i965_mpeg2_context));
+
/* kernel */
- if (mpeg2_vld_kernels == NULL) {
- assert(NUM_MPEG2_VLD_KERNELS == (sizeof(mpeg2_vld_kernels_gen5) /
- sizeof(mpeg2_vld_kernels_gen5[0])));
- assert(NUM_MPEG2_VLD_KERNELS <= MAX_INTERFACE_DESC);
-
- if (IS_IRONLAKE(i965->intel.device_id))
- mpeg2_vld_kernels = mpeg2_vld_kernels_gen5;
- else
- mpeg2_vld_kernels = mpeg2_vld_kernels_gen4;
-
- for (i = 0; i < NUM_MPEG2_VLD_KERNELS; i++) {
- struct i965_kernel *kernel = &mpeg2_vld_kernels[i];
- kernel->bo = dri_bo_alloc(i965->intel.bufmgr,
- kernel->name,
- kernel->size, 64);
- assert(kernel->bo);
- dri_bo_subdata(kernel->bo, 0, kernel->size, kernel->bin);
- }
+ assert(NUM_MPEG2_VLD_KERNELS == (sizeof(mpeg2_vld_kernels_gen4) /
+ sizeof(mpeg2_vld_kernels_gen4[0])));
+ assert(NUM_MPEG2_VLD_KERNELS == (sizeof(mpeg2_vld_kernels_gen5) /
+ sizeof(mpeg2_vld_kernels_gen5[0])));
+ assert(NUM_MPEG2_VLD_KERNELS <= MAX_INTERFACE_DESC);
+
+ if (IS_IRONLAKE(i965->intel.device_id))
+ memcpy(i965_mpeg2_context->vld_kernels, mpeg2_vld_kernels_gen5, sizeof(i965_mpeg2_context->vld_kernels));
+ else
+ memcpy(i965_mpeg2_context->vld_kernels, mpeg2_vld_kernels_gen4, sizeof(i965_mpeg2_context->vld_kernels));
+
+ for (i = 0; i < NUM_MPEG2_VLD_KERNELS; i++) {
+ struct i965_kernel *kernel = &i965_mpeg2_context->vld_kernels[i];
+ kernel->bo = dri_bo_alloc(i965->intel.bufmgr,
+ kernel->name,
+ kernel->size, 64);
+ assert(kernel->bo);
+ dri_bo_subdata(kernel->bo, 0, kernel->size, kernel->bin);
}
/* URB */
struct decode_state;
struct i965_media_context;
+#define NUM_MPEG2_VLD_KERNELS 15
+
+struct i965_mpeg2_context
+{
+ struct i965_kernel vld_kernels[NUM_MPEG2_VLD_KERNELS];
+};
+
void i965_media_mpeg2_decode_init(VADriverContextP ctx, struct decode_state * decode_state, struct i965_media_context *media_context);
void i965_media_mpeg2_dec_context_init(VADriverContextP ctx, struct i965_media_context *media_context);
#include "intel_driver.h"
#include "i965_defines.h"
#include "i965_structs.h"
-
+#include "i965_drv_video.h"
#include "i965_post_processing.h"
#include "i965_render.h"
-#include "i965_drv_video.h"
#define HAS_PP(ctx) (IS_IRONLAKE((ctx)->intel.device_id) || \
IS_GEN6((ctx)->intel.device_id))
-struct pp_module
-{
- struct i965_kernel kernel;
-
- /* others */
- void (*initialize)(VADriverContextP ctx, VASurfaceID surface, int input,
- unsigned short srcw, unsigned short srch,
- unsigned short destw, unsigned short desth);
-};
-
static const uint32_t pp_null_gen5[][4] = {
#include "shaders/post_processing/null.g4b.gen5"
};
},
};
-#define NUM_PP_MODULES ARRAY_ELEMS(pp_modules_gen5)
-
-static struct pp_module *pp_modules = NULL;
-
struct pp_static_parameter
{
struct {
desc = bo->virtual;
memset(desc, 0, sizeof(*desc));
desc->desc0.grf_reg_blocks = 10;
- desc->desc0.kernel_start_pointer = pp_modules[pp_index].kernel.bo->offset >> 6; /* reloc */
+ desc->desc0.kernel_start_pointer = pp_context->pp_modules[pp_index].kernel.bo->offset >> 6; /* reloc */
desc->desc1.const_urb_entry_read_offset = 0;
desc->desc1.const_urb_entry_read_len = 4; /* grf 1-4 */
desc->desc2.sampler_state_pointer = pp_context->sampler_state_table.bo->offset >> 5;
I915_GEM_DOMAIN_INSTRUCTION, 0,
desc->desc0.grf_reg_blocks,
offsetof(struct i965_interface_descriptor, desc0),
- pp_modules[pp_index].kernel.bo);
+ pp_context->pp_modules[pp_index].kernel.bo);
dri_bo_emit_reloc(bo,
I915_GEM_DOMAIN_INSTRUCTION, 0,
memset(&pp_static_parameter, 0, sizeof(pp_static_parameter));
memset(&pp_inline_parameter, 0, sizeof(pp_inline_parameter));
assert(pp_index >= PP_NULL && pp_index < NUM_PP_MODULES);
- assert(pp_modules);
pp_context->current_pp = pp_index;
- pp_module = &pp_modules[pp_index];
+ pp_module = &pp_context->pp_modules[pp_index];
if (pp_module->initialize)
pp_module->initialize(ctx, surface, input, srcw, srch, destw, desth);
memset(&pp_static_parameter, 0, sizeof(pp_static_parameter));
memset(&pp_inline_parameter, 0, sizeof(pp_inline_parameter));
assert(pp_index >= PP_NULL && pp_index < NUM_PP_MODULES);
- assert(pp_modules);
pp_context->current_pp = pp_index;
- pp_module = &pp_modules[pp_index];
+ pp_module = &pp_context->pp_modules[pp_index];
if (pp_module->initialize)
pp_module->initialize(ctx, surface, input, srcw, srch, destw, desth);
desc = bo->virtual;
memset(desc, 0, sizeof(*desc));
desc->desc0.kernel_start_pointer =
- pp_modules[pp_index].kernel.bo->offset >> 6; /* reloc */
+ pp_context->pp_modules[pp_index].kernel.bo->offset >> 6; /* reloc */
desc->desc1.single_program_flow = 1;
desc->desc1.floating_point_mode = FLOATING_POINT_IEEE_754;
desc->desc2.sampler_count = 1; /* 1 - 4 samplers used */
I915_GEM_DOMAIN_INSTRUCTION, 0,
0,
offsetof(struct gen6_interface_descriptor_data, desc0),
- pp_modules[pp_index].kernel.bo);
+ pp_context->pp_modules[pp_index].kernel.bo);
dri_bo_emit_reloc(bo,
I915_GEM_DOMAIN_INSTRUCTION, 0,
dri_bo_unreference(pp_context->stmm.bo);
pp_context->stmm.bo = NULL;
+ for (i = 0; i < NUM_PP_MODULES; i++) {
+ struct pp_module *pp_module = &pp_context->pp_modules[i];
+
+ dri_bo_unreference(pp_module->kernel.bo);
+ pp_module->kernel.bo = NULL;
+ }
+
free(pp_context);
}
i965->pp_context = NULL;
-
- for (i = 0; i < NUM_PP_MODULES && pp_modules; i++) {
- struct pp_module *pp_module = &pp_modules[i];
-
- dri_bo_unreference(pp_module->kernel.bo);
- pp_module->kernel.bo = NULL;
- }
}
return True;
if (pp_context == NULL) {
pp_context = calloc(1, sizeof(*pp_context));
i965->pp_context = pp_context;
- }
- pp_context->urb.size = URB_SIZE((&i965->intel));
- pp_context->urb.num_vfe_entries = 32;
- pp_context->urb.size_vfe_entry = 1; /* in 512 bits unit */
- pp_context->urb.num_cs_entries = 1;
- pp_context->urb.size_cs_entry = 2; /* in 512 bits unit */
- pp_context->urb.vfe_start = 0;
- pp_context->urb.cs_start = pp_context->urb.vfe_start +
- pp_context->urb.num_vfe_entries * pp_context->urb.size_vfe_entry;
- assert(pp_context->urb.cs_start +
- pp_context->urb.num_cs_entries * pp_context->urb.size_cs_entry <= URB_SIZE((&i965->intel)));
-
- assert(NUM_PP_MODULES == ARRAY_ELEMS(pp_modules_gen6));
-
- if (IS_GEN6(i965->intel.device_id))
- pp_modules = pp_modules_gen6;
- else if (IS_IRONLAKE(i965->intel.device_id)) {
- pp_modules = pp_modules_gen5;
- }
-
- for (i = 0; i < NUM_PP_MODULES && pp_modules; i++) {
- struct pp_module *pp_module = &pp_modules[i];
- dri_bo_unreference(pp_module->kernel.bo);
- pp_module->kernel.bo = dri_bo_alloc(i965->intel.bufmgr,
- pp_module->kernel.name,
- pp_module->kernel.size,
- 4096);
- assert(pp_module->kernel.bo);
- dri_bo_subdata(pp_module->kernel.bo, 0, pp_module->kernel.size, pp_module->kernel.bin);
+ pp_context->urb.size = URB_SIZE((&i965->intel));
+ pp_context->urb.num_vfe_entries = 32;
+ pp_context->urb.size_vfe_entry = 1; /* in 512 bits unit */
+ pp_context->urb.num_cs_entries = 1;
+ pp_context->urb.size_cs_entry = 2; /* in 512 bits unit */
+ pp_context->urb.vfe_start = 0;
+ pp_context->urb.cs_start = pp_context->urb.vfe_start +
+ pp_context->urb.num_vfe_entries * pp_context->urb.size_vfe_entry;
+ assert(pp_context->urb.cs_start +
+ pp_context->urb.num_cs_entries * pp_context->urb.size_cs_entry <= URB_SIZE((&i965->intel)));
+
+ assert(NUM_PP_MODULES == ARRAY_ELEMS(pp_modules_gen5));
+ assert(NUM_PP_MODULES == ARRAY_ELEMS(pp_modules_gen6));
+
+ if (IS_GEN6(i965->intel.device_id))
+ memcpy(pp_context->pp_modules, pp_modules_gen6, sizeof(pp_context->pp_modules));
+ else if (IS_IRONLAKE(i965->intel.device_id))
+ memcpy(pp_context->pp_modules, pp_modules_gen5, sizeof(pp_context->pp_modules));
+
+ for (i = 0; i < NUM_PP_MODULES; i++) {
+ struct pp_module *pp_module = &pp_context->pp_modules[i];
+ dri_bo_unreference(pp_module->kernel.bo);
+ pp_module->kernel.bo = dri_bo_alloc(i965->intel.bufmgr,
+ pp_module->kernel.name,
+ pp_module->kernel.size,
+ 4096);
+ assert(pp_module->kernel.bo);
+ dri_bo_subdata(pp_module->kernel.bo, 0, pp_module->kernel.size, pp_module->kernel.bin);
+ }
}
}
PP_NV12_DNDI,
};
+#define NUM_PP_MODULES 5
+
struct pp_load_save_context
{
int dest_w;
};
+struct pp_module
+{
+ struct i965_kernel kernel;
+
+ /* others */
+ void (*initialize)(VADriverContextP ctx, VASurfaceID surface, int input,
+ unsigned short srcw, unsigned short srch,
+ unsigned short destw, unsigned short desth);
+};
+
struct i965_post_processing_context
{
int current_pp;
+ struct pp_module pp_modules[NUM_PP_MODULES];
struct {
dri_bo *bo;
}
};
-static struct i965_kernel *render_kernels = NULL;
-
-#define NUM_RENDER_KERNEL (sizeof(render_kernels_gen4)/sizeof(render_kernels_gen4[0]))
-
#define URB_VS_ENTRIES 8
#define URB_VS_ENTRY_SIZE 1
memset(sf_state, 0, sizeof(*sf_state));
sf_state->thread0.grf_reg_count = I965_GRF_BLOCKS(SF_KERNEL_NUM_GRF);
- sf_state->thread0.kernel_start_pointer = render_kernels[SF_KERNEL].bo->offset >> 6;
+ sf_state->thread0.kernel_start_pointer = render_state->render_kernels[SF_KERNEL].bo->offset >> 6;
sf_state->sf1.single_program_flow = 1; /* XXX */
sf_state->sf1.binding_table_entry_count = 0;
I915_GEM_DOMAIN_INSTRUCTION, 0,
sf_state->thread0.grf_reg_count << 1,
offsetof(struct i965_sf_unit_state, thread0),
- render_kernels[SF_KERNEL].bo);
+ render_state->render_kernels[SF_KERNEL].bo);
dri_bo_unmap(render_state->sf.state);
}
memset(wm_state, 0, sizeof(*wm_state));
wm_state->thread0.grf_reg_count = I965_GRF_BLOCKS(PS_KERNEL_NUM_GRF);
- wm_state->thread0.kernel_start_pointer = render_kernels[PS_SUBPIC_KERNEL].bo->offset >> 6;
+ wm_state->thread0.kernel_start_pointer = render_state->render_kernels[PS_SUBPIC_KERNEL].bo->offset >> 6;
wm_state->thread1.single_program_flow = 1; /* XXX */
I915_GEM_DOMAIN_INSTRUCTION, 0,
wm_state->thread0.grf_reg_count << 1,
offsetof(struct i965_wm_unit_state, thread0),
- render_kernels[PS_SUBPIC_KERNEL].bo);
+ render_state->render_kernels[PS_SUBPIC_KERNEL].bo);
dri_bo_emit_reloc(render_state->wm.state,
I915_GEM_DOMAIN_INSTRUCTION, 0,
memset(wm_state, 0, sizeof(*wm_state));
wm_state->thread0.grf_reg_count = I965_GRF_BLOCKS(PS_KERNEL_NUM_GRF);
- wm_state->thread0.kernel_start_pointer = render_kernels[PS_KERNEL].bo->offset >> 6;
+ wm_state->thread0.kernel_start_pointer = render_state->render_kernels[PS_KERNEL].bo->offset >> 6;
wm_state->thread1.single_program_flow = 1; /* XXX */
I915_GEM_DOMAIN_INSTRUCTION, 0,
wm_state->thread0.grf_reg_count << 1,
offsetof(struct i965_wm_unit_state, thread0),
- render_kernels[PS_KERNEL].bo);
+ render_state->render_kernels[PS_KERNEL].bo);
dri_bo_emit_reloc(render_state->wm.state,
I915_GEM_DOMAIN_INSTRUCTION, 0,
OUT_BATCH(ctx, 0);
OUT_BATCH(ctx, GEN6_3DSTATE_WM | (9 - 2));
- OUT_RELOC(ctx, render_kernels[kernel].bo,
+ OUT_RELOC(ctx, render_state->render_kernels[kernel].bo,
I915_GEM_DOMAIN_INSTRUCTION, 0,
0);
OUT_BATCH(ctx, (1 << GEN6_3DSTATE_WM_SAMPLER_COUNT_SHITF) |
sizeof(render_kernels_gen6[0])));
if (IS_GEN6(i965->intel.device_id))
- render_kernels = render_kernels_gen6;
+ memcpy(render_state->render_kernels, render_kernels_gen6, sizeof(render_state->render_kernels));
else if (IS_IRONLAKE(i965->intel.device_id))
- render_kernels = render_kernels_gen5;
+ memcpy(render_state->render_kernels, render_kernels_gen5, sizeof(render_state->render_kernels));
else
- render_kernels = render_kernels_gen4;
+ memcpy(render_state->render_kernels, render_kernels_gen4, sizeof(render_state->render_kernels));
for (i = 0; i < NUM_RENDER_KERNEL; i++) {
- struct i965_kernel *kernel = &render_kernels[i];
+ struct i965_kernel *kernel = &render_state->render_kernels[i];
if (!kernel->size)
continue;
render_state->curbe.bo = NULL;
for (i = 0; i < NUM_RENDER_KERNEL; i++) {
- struct i965_kernel *kernel = &render_kernels[i];
+ struct i965_kernel *kernel = &render_state->render_kernels[i];
dri_bo_unreference(kernel->bo);
kernel->bo = NULL;
#define MAX_SAMPLERS 16
#define MAX_RENDER_SURFACES (MAX_SAMPLERS + 1)
+#define NUM_RENDER_KERNEL 3
+
#include "i965_post_processing.h"
+struct i965_kernel;
+
struct i965_render_state
{
struct {
struct intel_region *draw_region;
int pp_flag; /* 0: disable, 1: enable */
- struct i965_post_processing_context pp_context;
+
+ struct i965_kernel render_kernels[3];
};
Bool i965_render_init(VADriverContextP ctx);
projects / platform / upstream / libva.git / commitdiff