(vec_concat:<VNARROWQ2>
(match_operand:<VNARROWQ> 1 "register_operand" "0")
(unspec:<VNARROWQ>
- [(match_operand:VQN 2 "register_operand" "w")] UNSPEC_SQXTUN2)))]
+ [(match_operand:VQN 2 "register_operand" "w")] UNSPEC_SQXTUN)))]
"TARGET_SIMD && !BYTES_BIG_ENDIAN"
"sqxtun2\\t%0.<V2ntype>, %2.<Vtype>"
[(set_attr "type" "neon_sat_shift_imm_narrow_q")]
[(set (match_operand:<VNARROWQ2> 0 "register_operand" "=w")
(vec_concat:<VNARROWQ2>
(unspec:<VNARROWQ>
- [(match_operand:VQN 2 "register_operand" "w")] UNSPEC_SQXTUN2)
+ [(match_operand:VQN 2 "register_operand" "w")] UNSPEC_SQXTUN)
(match_operand:<VNARROWQ> 1 "register_operand" "0")))]
"TARGET_SIMD && BYTES_BIG_ENDIAN"
"sqxtun2\\t%0.<V2ntype>, %2.<Vtype>"
[(match_operand:<VNARROWQ2> 0 "register_operand")
(match_operand:<VNARROWQ> 1 "register_operand")
(unspec:<VNARROWQ>
- [(match_operand:VQN 2 "register_operand")] UNSPEC_SQXTUN2)]
+ [(match_operand:VQN 2 "register_operand")] UNSPEC_SQXTUN)]
"TARGET_SIMD"
{
if (BYTES_BIG_ENDIAN)
UNSPEC_USQADD ; Used in aarch64-simd.md.
UNSPEC_SUQADD ; Used in aarch64-simd.md.
UNSPEC_SQXTUN ; Used in aarch64-simd.md.
- UNSPEC_SQXTUN2 ; Used in aarch64-simd.md.
UNSPEC_SSRA ; Used in aarch64-simd.md.
UNSPEC_USRA ; Used in aarch64-simd.md.
UNSPEC_SRSRA ; Used in aarch64-simd.md.