dts: starfive: enable usb2.0 when use pcie0

Enable usb2.0

Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>

diff --git a/arch/riscv/boot/dts/starfive/jh7110-evb-pcie-i2s-sd.dts b/arch/riscv/boot/dts/starfive/jh7110-evb-pcie-i2s-sd.dts
index 0ac88af..152ef0a 100644 (file)
--- a/arch/riscv/boot/dts/starfive/jh7110-evb-pcie-i2s-sd.dts
+++ b/arch/riscv/boot/dts/starfive/jh7110-evb-pcie-i2s-sd.dts
@@ -63,3 +63,24 @@
 &i2stx_4ch1 {
        status = "okay";
 };
+
+&usbdrd30 {
+       clocks = <&clkgen JH7110_USB_125M>,
+                <&clkgen JH7110_USB0_CLK_APP_125>,
+                <&clkgen JH7110_USB0_CLK_LPM>,
+                <&clkgen JH7110_USB0_CLK_STB>,
+                <&clkgen JH7110_USB0_CLK_USB_APB>,
+                <&clkgen JH7110_USB0_CLK_AXI>,
+                <&clkgen JH7110_USB0_CLK_UTMI_APB>;
+       clock-names = "125m","app","lpm","stb","apb","axi","utmi";
+       resets = <&rstgen RSTN_U0_CDN_USB_PWRUP>,
+                <&rstgen RSTN_U0_CDN_USB_APB>,
+                <&rstgen RSTN_U0_CDN_USB_AXI>,
+                <&rstgen RSTN_U0_CDN_USB_UTMI_APB>;
+       reset-names = "pwrup","apb","axi","utmi";
+       dr_mode = "host"; /*host or peripheral*/
+       starfive,usb2-only;
+       pinctrl-names = "default";
+       pinctrl-0 = <&usb_pins>;
+       status = "okay";
+};