clk: renesas: r8a779f0: Fix Ethernet Switch clocks
authorGeert Uytterhoeven <geert+renesas@glider.be>
Tue, 15 Nov 2022 08:34:14 +0000 (09:34 +0100)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Wed, 16 Nov 2022 08:05:59 +0000 (09:05 +0100)
The RSwitch2 and EtherTSN-IF clocks were accidentally mixed up.
While at it, rename them to better match the (future) documentation.

Fixes: a3b4137a4d4023e6 ("clk: renesas: r8a779f0: Add Ethernet Switch clocks")
Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/99b8b41bd2c5043c9e457862ef4bc144869eca58.1668501212.git.geert+renesas@glider.be
drivers/clk/renesas/r8a779f0-cpg-mssr.c

index 800fdc104edd657ff2ef151ea0f8241d75870571..f721835c7e21248b64d096e1124f5ded814bb33f 100644 (file)
@@ -163,8 +163,8 @@ static const struct mssr_mod_clk r8a779f0_mod_clks[] __initconst = {
        DEF_MOD("cmt3",         913,    R8A779F0_CLK_R),
        DEF_MOD("pfc0",         915,    R8A779F0_CLK_CL16M),
        DEF_MOD("tsc",          919,    R8A779F0_CLK_CL16M),
-       DEF_MOD("tsn",          1505,   R8A779F0_CLK_S0D2_HSC),
-       DEF_MOD("rsw",          1506,   R8A779F0_CLK_RSW2),
+       DEF_MOD("rswitch2",     1505,   R8A779F0_CLK_RSW2),
+       DEF_MOD("ether-serdes", 1506,   R8A779F0_CLK_S0D2_HSC),
        DEF_MOD("ufs",          1514,   R8A779F0_CLK_S0D4_HSC),
 };