fixed dirty bit support for 4M pages (L4 Pistachio fix)

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@549 c046a42c-6fe2-441c-8c8c-71466251a162

diff --git a/target-i386/helper2.c b/target-i386/helper2.c
index 2feccc3..d5c7727 100644 (file)
--- a/target-i386/helper2.c
+++ b/target-i386/helper2.c
@@ -304,7 +304,7 @@ int cpu_x86_handle_mmu_fault(CPUX86State *env, uint32_t addr,
     /* if PSE bit is set, then we use a 4MB page */
     if ((pde & PG_PSE_MASK) && (env->cr[4] & CR4_PSE_MASK)) {
         is_dirty = is_write && !(pde & PG_DIRTY_MASK);
-        if (!(pde & PG_ACCESSED_MASK)) {
+        if (!(pde & PG_ACCESSED_MASK) || is_dirty) {
             pde |= PG_ACCESSED_MASK;
             if (is_dirty)
                 pde |= PG_DIRTY_MASK;
@@ -363,7 +363,7 @@ int cpu_x86_handle_mmu_fault(CPUX86State *env, uint32_t addr,
                 prot |= PROT_WRITE;
         }
     }
-    
+
  do_mapping:
     pte = pte & a20_mask;