u16 reg = be32_to_cpup(paddr++);
u16 mask = be32_to_cpup(paddr++);
u16 val_bits = be32_to_cpup(paddr++);
- int val;
u32 regnum = mdiobus_c45_addr(devid, reg);
- val = 0;
+ int val = 0;
+
if (mask) {
val = phy_read(phydev, regnum);
if (val < 0) {
static void enable_broadcast(struct phy_device *phydev, int init_page, int on)
{
int val;
+
phy_write(phydev, PAGESEL, 0);
val = phy_read(phydev, PHYCR2);
if (on)
static int et1011c_config_aneg(struct phy_device *phydev)
{
- int ctl = 0;
- ctl = phy_read(phydev, MII_BMCR);
+ int ctl = phy_read(phydev, MII_BMCR);
+
if (ctl < 0)
return ctl;
ctl &= ~(BMCR_FULLDPLX | BMCR_SPEED100 | BMCR_SPEED1000 |
static int et1011c_read_status(struct phy_device *phydev)
{
+ static int speed;
int ret;
u32 val;
- static int speed;
+
ret = genphy_read_status(phydev);
if (speed != phydev->speed) {
static void mdiobus_release(struct device *d)
{
struct mii_bus *bus = to_mii_bus(d);
+
BUG_ON(bus->state != MDIOBUS_RELEASED &&
/* for compatibility with error handling in drivers */
bus->state != MDIOBUS_ALLOCATED);
static int qs6612_config_intr(struct phy_device *phydev)
{
int err;
+
if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
/* clear any interrupts before enabling them */
err = qs6612_ack_interrupt(phydev);