opcodes: blackfin: mark push/pop insns with a P6/P7 range as illegal

The push/pop multiple insn has a 3 bit field for the P register range,
but only values of 0...5 are valid (P0 - P5).  There is no such P6 or
P7 register, so mark these insns as illegal.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 3067e3c..f11938c 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,7 @@
+2010-09-22  Mike Frysinger  <vapier@gentoo.org>
+
+       * bfin-dis.c (decode_PushPopMultiple_0): Return 0 when pr > 5.
+
 2010-09-22  Robin Getz  <robin.getz@analog.com>
 
        * bfin-dis.c (decode_dsp32shiftimm_0): Add missing "S" flag.

diff --git a/opcodes/bfin-dis.c b/opcodes/bfin-dis.c
index a510db1..0ce0ecf 100644 (file)
--- a/opcodes/bfin-dis.c
+++ b/opcodes/bfin-dis.c
@@ -936,6 +936,9 @@ decode_PushPopMultiple_0 (TIword iw0, disassemble_info *outf)
   int dr = ((iw0 >> PushPopMultiple_dr_bits) & PushPopMultiple_dr_mask);
   int pr = ((iw0 >> PushPopMultiple_pr_bits) & PushPopMultiple_pr_mask);
 
+  if (pr > 5)
+    return 0;
+
   if (W == 1 && d == 1 && p == 1)
     {
       OUTS (outf, "[--SP] = (R7:");