* simops.c: Add shift support.

diff --git a/sim/v850/ChangeLog b/sim/v850/ChangeLog
index 546b2bdb6729a2be083811c88d45c2ce8b88a4d7..af163562283363b1fad6400790be52d1c6a4dd98 100644 (file)
--- a/sim/v850/ChangeLog
+++ b/sim/v850/ChangeLog
@@ -1,5 +1,7 @@
 Thu Aug 29 13:53:29 1996  Jeffrey A Law  (law@cygnus.com)
 
+       * simops.c: Add shift support.
+
        * simops.c: Add multiply & divide support.  Abort for system
        instructions.
 

diff --git a/sim/v850/simops.c b/sim/v850/simops.c
index a6c476835d62c4c87e52f58921fb8b766aec08be..8ec7871031c6a5ab3379b14d273d4bf247dac819 100644 (file)
--- a/sim/v850/simops.c
+++ b/sim/v850/simops.c
@@ -2,11 +2,6 @@
 #include "v850_sim.h"
 #include "simops.h"
 
-void
-OP_280 ()
-{
-}
-
 void
 OP_220 ()
 {
@@ -227,16 +222,6 @@ OP_40 ()
   State.regs[OP[1]] /= (State.regs[OP[0]] & 0xffff);
 }
 
-void
-OP_8007E0 ()
-{
-}
-
-void
-OP_C007E0 ()
-{
-}
-
 void
 OP_10720 ()
 {
@@ -257,11 +242,6 @@ OP_60 ()
 {
 }
 
-void
-OP_2A0 ()
-{
-}
-
 void
 OP_87C0 ()
 {
@@ -356,18 +336,70 @@ OP_20 ()
   State.regs[OP[1]] = ~State.regs[OP[0]];
 }
 
+/* sar zero_extend(imm5),reg1
+
+   XXX condition codes.  */
 void
-OP_A007E0 ()
+OP_2A0 ()
 {
+  int temp = State.regs[OP[1]];
+
+  temp >>= (OP[0] & 0x1f);
+
+  State.regs[OP[1]] = temp;
 }
 
+/* sar reg1, reg2
+
+   XXX condition codes.  */
 void
-OP_500 ()
+OP_A007E0 ()
 {
+  int temp = State.regs[OP[1]];
+
+  temp >>= (State.regs[OP[0]] & 0x1f);
+
+  State.regs[OP[1]] = temp;
 }
 
+/* shl zero_extend(imm5),reg1
+
+   XXX condition codes.  */
 void
 OP_2C0 ()
+{
+  State.regs[OP[1]] <<= (OP[0] & 0x1f);
+}
+
+/* shl reg1, reg2
+
+   XXX condition codes.  */
+void
+OP_C007E0 ()
+{
+  State.regs[OP[1]] <<= (State.regs[OP[0]] & 0x1f);
+}
+
+/* shr zero_extend(imm5),reg1
+
+   XXX condition codes.  */
+void
+OP_280 ()
+{
+  State.regs[OP[1]] >>= (OP[0] & 0x1f);
+}
+
+/* shr reg1, reg2
+
+   XXX condition codes.  */
+void
+OP_8007E0 ()
+{
+  State.regs[OP[1]] >>= (State.regs[OP[0]] & 0x1f);
+}
+
+void
+OP_500 ()
 {
 }