arm64: dts: ti: k3-j721s2-common-proc-board: Add USB support

The board uses lane 1 of SERDES for USB. Set the mux
accordingly.

The USB controller and EVM supports super-speed for USB0
on the Type-C port. However, the SERDES has a limitation
that up to 2 protocols can be used at a time. The SERDES is
wired for PCIe, eDP and USB super-speed. It has been
chosen to use PCIe and eDP as default. So restrict
USB0 to high-speed mode.

Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Matt Ranostay <mranostay@ti.com>
Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Link: https://lore.kernel.org/r/20230331090028.8373-6-r-gunasekaran@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>

diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
index 30a566fef19510501bbfc4fa88f3d8a722a3b346..f81a40bbdac0e750abb14f2ed4876d204f7d9811 100644 (file)
--- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
@@ -146,6 +146,12 @@
                        J721S2_IOPAD(0x020, PIN_INPUT, 7) /* (AA23) MCAN15_RX.GPIO0_8 */
                >;
        };
+
+       main_usbss0_pins_default: main-usbss0-pins-default {
+               pinctrl-single,pins = <
+                       J721S2_IOPAD(0x0ec, PIN_OUTPUT, 6) /* (AG25) TIMER_IO1.USB0_DRVVBUS */
+               >;
+       };
 };
 
 &wkup_pmx0 {
@@ -344,6 +350,23 @@
        };
 };
 
+&usb_serdes_mux {
+       idle-states = <1>; /* USB0 to SERDES lane 1 */
+};
+
+&usbss0 {
+       status = "okay";
+       pinctrl-0 = <&main_usbss0_pins_default>;
+       pinctrl-names = "default";
+       ti,vbus-divider;
+       ti,usb2-only;
+};
+
+&usb0 {
+       dr_mode = "otg";
+       maximum-speed = "high-speed";
+};
+
 &mcu_mcan0 {
        status = "okay";
        pinctrl-names = "default";