intel: Convert i915 engine type to intel in tools/ common/ and ds/

This ones were left to be done after initial conversion.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18975>

diff --git a/src/intel/common/intel_batch_decoder.c b/src/intel/common/intel_batch_decoder.c
index a73afdf..55b8087 100644 (file)
--- a/src/intel/common/intel_batch_decoder.c
+++ b/src/intel/common/intel_batch_decoder.c
@@ -51,7 +51,7 @@ intel_batch_decode_ctx_init(struct intel_batch_decode_ctx *ctx,
    ctx->fp = fp;
    ctx->flags = flags;
    ctx->max_vbo_decoded_lines = -1; /* No limit! */
-   ctx->engine = I915_ENGINE_CLASS_RENDER;
+   ctx->engine = INTEL_ENGINE_CLASS_RENDER;
 
    if (xml_path == NULL)
       ctx->spec = intel_spec_load(devinfo);

diff --git a/src/intel/common/intel_decoder.c b/src/intel/common/intel_decoder.c
index bc1ef54..56c74c5 100644 (file)
--- a/src/intel/common/intel_decoder.c
+++ b/src/intel/common/intel_decoder.c
@@ -166,9 +166,9 @@ create_group(struct parser_context *ctx,
    group->fixed_length = fixed_length;
    group->dword_length_field = NULL;
    group->dw_length = 0;
-   group->engine_mask = I915_ENGINE_CLASS_TO_MASK(I915_ENGINE_CLASS_RENDER) |
-                        I915_ENGINE_CLASS_TO_MASK(I915_ENGINE_CLASS_VIDEO) |
-                        I915_ENGINE_CLASS_TO_MASK(I915_ENGINE_CLASS_COPY);
+   group->engine_mask = INTEL_ENGINE_CLASS_TO_MASK(INTEL_ENGINE_CLASS_RENDER) |
+                        INTEL_ENGINE_CLASS_TO_MASK(INTEL_ENGINE_CLASS_VIDEO) |
+                        INTEL_ENGINE_CLASS_TO_MASK(INTEL_ENGINE_CLASS_COPY);
    group->bias = 1;
 
    for (int i = 0; atts[i]; i += 2) {
@@ -186,11 +186,11 @@ create_group(struct parser_context *ctx,
          group->engine_mask = 0;
          while (tok != NULL) {
             if (strcmp(tok, "render") == 0) {
-               group->engine_mask |= I915_ENGINE_CLASS_TO_MASK(I915_ENGINE_CLASS_RENDER);
+               group->engine_mask |= INTEL_ENGINE_CLASS_TO_MASK(INTEL_ENGINE_CLASS_RENDER);
             } else if (strcmp(tok, "video") == 0) {
-               group->engine_mask |= I915_ENGINE_CLASS_TO_MASK(I915_ENGINE_CLASS_VIDEO);
+               group->engine_mask |= INTEL_ENGINE_CLASS_TO_MASK(INTEL_ENGINE_CLASS_VIDEO);
             } else if (strcmp(tok, "blitter") == 0) {
-               group->engine_mask |= I915_ENGINE_CLASS_TO_MASK(I915_ENGINE_CLASS_COPY);
+               group->engine_mask |= INTEL_ENGINE_CLASS_TO_MASK(INTEL_ENGINE_CLASS_COPY);
             } else {
                fprintf(stderr, "unknown engine class defined for instruction \"%s\": %s\n", name, atts[i + 1]);
             }
@@ -751,13 +751,13 @@ void intel_spec_destroy(struct intel_spec *spec)
 
 struct intel_group *
 intel_spec_find_instruction(struct intel_spec *spec,
-                            enum drm_i915_gem_engine_class engine,
+                            enum intel_engine_class engine,
                             const uint32_t *p)
 {
    hash_table_foreach(spec->commands, entry) {
       struct intel_group *command = entry->data;
       uint32_t opcode = *p & command->opcode_mask;
-      if ((command->engine_mask & I915_ENGINE_CLASS_TO_MASK(engine)) &&
+      if ((command->engine_mask & INTEL_ENGINE_CLASS_TO_MASK(engine)) &&
            opcode == command->opcode)
          return command;
    }

diff --git a/src/intel/common/intel_decoder.h b/src/intel/common/intel_decoder.h
index 7a48826..1e0386d 100644 (file)
--- a/src/intel/common/intel_decoder.h
+++ b/src/intel/common/intel_decoder.h
@@ -32,7 +32,7 @@
 #include "util/hash_table.h"
 #include "util/bitset.h"
 
-#include "drm-uapi/i915_drm.h"
+#include "common/intel_engine.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -43,7 +43,7 @@ struct intel_group;
 struct intel_field;
 union intel_field_value;
 
-#define I915_ENGINE_CLASS_TO_MASK(x) BITSET_BIT(x)
+#define INTEL_ENGINE_CLASS_TO_MASK(x) BITSET_BIT(x)
 
 static inline uint32_t intel_make_gen(uint32_t major, uint32_t minor)
 {
@@ -59,7 +59,7 @@ struct intel_spec *intel_spec_load_filename(const char *filename);
 void intel_spec_destroy(struct intel_spec *spec);
 uint32_t intel_spec_get_gen(struct intel_spec *spec);
 struct intel_group *intel_spec_find_instruction(struct intel_spec *spec,
-                                                enum drm_i915_gem_engine_class engine,
+                                                enum intel_engine_class engine,
                                                 const uint32_t *p);
 struct intel_group *intel_spec_find_register(struct intel_spec *spec, uint32_t offset);
 struct intel_group *intel_spec_find_register_by_name(struct intel_spec *spec, const char *name);
@@ -251,7 +251,7 @@ struct intel_batch_decode_ctx {
 
    int max_vbo_decoded_lines;
 
-   enum drm_i915_gem_engine_class engine;
+   enum intel_engine_class engine;
 
    int n_batch_buffer_start;
    uint64_t acthd;

diff --git a/src/intel/ds/intel_driver_ds.cc b/src/intel/ds/intel_driver_ds.cc
index 4f96c13..c68de85 100644 (file)
--- a/src/intel/ds/intel_driver_ds.cc
+++ b/src/intel/ds/intel_driver_ds.cc
@@ -139,17 +139,6 @@ PERFETTO_DEFINE_DATA_SOURCE_STATIC_MEMBERS(IntelRenderpassDataSource);
 
 using perfetto::protos::pbzero::InternedGpuRenderStageSpecification_RenderStageCategory;
 
-InternedGpuRenderStageSpecification_RenderStageCategory
-i915_engine_class_to_category(enum drm_i915_gem_engine_class engine_class)
-{
-   switch (engine_class) {
-   case I915_ENGINE_CLASS_RENDER:
-      return InternedGpuRenderStageSpecification_RenderStageCategory::GRAPHICS;
-   default:
-      return InternedGpuRenderStageSpecification_RenderStageCategory::OTHER;
-   }
-}
-
 static void
 sync_timestamp(IntelRenderpassDataSource::TraceContext &ctx,
                struct intel_ds_device *device)

diff --git a/src/intel/ds/intel_pps_perf.cc b/src/intel/ds/intel_pps_perf.cc
index c4c7424..71b605c 100644 (file)
--- a/src/intel/ds/intel_pps_perf.cc
+++ b/src/intel/ds/intel_pps_perf.cc
@@ -12,8 +12,6 @@
 #include <util/ralloc.h>
 #include <utility>
 
-#include "drm-uapi/i915_drm.h"
-
 #include <pps/pps.h>
 #include <pps/pps_device.h>
 

diff --git a/src/intel/tools/aub_read.c b/src/intel/tools/aub_read.c
index 8b97ad5..2bcbe37 100644 (file)
--- a/src/intel/tools/aub_read.c
+++ b/src/intel/tools/aub_read.c
@@ -148,7 +148,7 @@ handle_trace_block(struct aub_read *read, const uint32_t *p)
    int type = p[1] & AUB_TRACE_TYPE_MASK;
    int address_space = p[1] & AUB_TRACE_ADDRESS_SPACE_MASK;
    int header_length = p[0] & 0xffff;
-   enum drm_i915_gem_engine_class engine = I915_ENGINE_CLASS_RENDER;
+   enum intel_engine_class engine = INTEL_ENGINE_CLASS_RENDER;
    const void *data = p + header_length + 2;
    uint64_t address = intel_48b_address((read->devinfo.ver >= 8 ? ((uint64_t) p[5] << 32) : 0) |
                                         ((uint64_t) p[3]));
@@ -163,13 +163,13 @@ handle_trace_block(struct aub_read *read, const uint32_t *p)
    case AUB_TRACE_OP_COMMAND_WRITE:
       switch (type) {
       case AUB_TRACE_TYPE_RING_PRB0:
-         engine = I915_ENGINE_CLASS_RENDER;
+         engine = INTEL_ENGINE_CLASS_RENDER;
          break;
       case AUB_TRACE_TYPE_RING_PRB1:
-         engine = I915_ENGINE_CLASS_VIDEO;
+         engine = INTEL_ENGINE_CLASS_VIDEO;
          break;
       case AUB_TRACE_TYPE_RING_PRB2:
-         engine = I915_ENGINE_CLASS_COPY;
+         engine = INTEL_ENGINE_CLASS_COPY;
          break;
       default:
          parse_error(read, p, "command write to unknown ring %d\n", type);
@@ -194,7 +194,7 @@ handle_memtrace_reg_write(struct aub_read *read, const uint32_t *p)
    if (read->reg_write)
       read->reg_write(read->user_data, offset, value);
 
-   enum drm_i915_gem_engine_class engine;
+   enum intel_engine_class engine;
    uint64_t context_descriptor;
 
    switch (offset) {
@@ -204,7 +204,7 @@ handle_memtrace_reg_write(struct aub_read *read, const uint32_t *p)
          return;
 
       read->render_elsp_index = 0;
-      engine = I915_ENGINE_CLASS_RENDER;
+      engine = INTEL_ENGINE_CLASS_RENDER;
       context_descriptor = (uint64_t)read->render_elsp[2] << 32 |
          read->render_elsp[3];
       break;
@@ -214,7 +214,7 @@ handle_memtrace_reg_write(struct aub_read *read, const uint32_t *p)
          return;
 
       read->video_elsp_index = 0;
-      engine = I915_ENGINE_CLASS_VIDEO;
+      engine = INTEL_ENGINE_CLASS_VIDEO;
       context_descriptor = (uint64_t)read->video_elsp[2] << 32 |
          read->video_elsp[3];
       break;
@@ -224,7 +224,7 @@ handle_memtrace_reg_write(struct aub_read *read, const uint32_t *p)
          return;
 
       read->blitter_elsp_index = 0;
-      engine = I915_ENGINE_CLASS_COPY;
+      engine = INTEL_ENGINE_CLASS_COPY;
       context_descriptor = (uint64_t)read->blitter_elsp[2] << 32 |
          read->blitter_elsp[3];
       break;
@@ -247,17 +247,17 @@ handle_memtrace_reg_write(struct aub_read *read, const uint32_t *p)
       read->blitter_elsp[2] = value;
       return;
    case RCSUNIT(EXECLIST_CONTROL): /* render elsc */
-      engine = I915_ENGINE_CLASS_RENDER;
+      engine = INTEL_ENGINE_CLASS_RENDER;
       context_descriptor = (uint64_t)read->render_elsp[2] << 32 |
          read->render_elsp[3];
       break;
    case VCSUNIT0(EXECLIST_CONTROL): /* video_elsc */
-      engine = I915_ENGINE_CLASS_VIDEO;
+      engine = INTEL_ENGINE_CLASS_VIDEO;
       context_descriptor = (uint64_t)read->video_elsp[2] << 32 |
          read->video_elsp[3];
       break;
    case BCSUNIT0(EXECLIST_CONTROL): /* blitter elsc */
-      engine = I915_ENGINE_CLASS_COPY;
+      engine = INTEL_ENGINE_CLASS_COPY;
       context_descriptor = (uint64_t)read->blitter_elsp[2] << 32 |
          read->blitter_elsp[3];
       break;

diff --git a/src/intel/tools/aub_read.h b/src/intel/tools/aub_read.h
index 6f2c38d..83f556c 100644 (file)
--- a/src/intel/tools/aub_read.h
+++ b/src/intel/tools/aub_read.h
@@ -28,7 +28,6 @@
 #include <stdint.h>
 
 #include "dev/intel_device_info.h"
-#include "drm-uapi/i915_drm.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -52,9 +51,9 @@ struct aub_read {
 
    void (*reg_write)(void *user_data, uint32_t reg_offset, uint32_t reg_value);
 
-   void (*ring_write)(void *user_data, enum drm_i915_gem_engine_class engine,
+   void (*ring_write)(void *user_data, enum intel_engine_class engine,
                       const void *data, uint32_t data_len);
-   void (*execlist_write)(void *user_data, enum drm_i915_gem_engine_class engine,
+   void (*execlist_write)(void *user_data, enum intel_engine_class engine,
                           uint64_t context_descriptor);
 
    /* Reader's data */

diff --git a/src/intel/tools/aub_write.c b/src/intel/tools/aub_write.c
index da36ade..1f44ffc 100644 (file)
--- a/src/intel/tools/aub_write.c
+++ b/src/intel/tools/aub_write.c
@@ -29,7 +29,6 @@
 #include <stdlib.h>
 #include <string.h>
 
-#include "drm-uapi/i915_drm.h"
 #include "intel_aub.h"
 #include "intel_context.h"
 
@@ -348,34 +347,34 @@ ppgtt_lookup(struct aub_file *aub, uint64_t ppgtt_addr)
 
 static const struct engine {
    const char *name;
-   enum drm_i915_gem_engine_class engine_class;
+   enum intel_engine_class engine_class;
    uint32_t hw_class;
    uint32_t elsp_reg;
    uint32_t elsq_reg;
    uint32_t status_reg;
    uint32_t control_reg;
 } engines[] = {
-   [I915_ENGINE_CLASS_RENDER] = {
+   [INTEL_ENGINE_CLASS_RENDER] = {
       .name = "RENDER",
-      .engine_class = I915_ENGINE_CLASS_RENDER,
+      .engine_class = INTEL_ENGINE_CLASS_RENDER,
       .hw_class = 1,
       .elsp_reg = RCSUNIT(EXECLIST_SUBMITPORT),
       .elsq_reg = RCSUNIT(EXECLIST_SQ_CONTENTS),
       .status_reg = RCSUNIT(EXECLIST_STATUS),
       .control_reg = RCSUNIT(EXECLIST_CONTROL),
    },
-   [I915_ENGINE_CLASS_VIDEO] = {
+   [INTEL_ENGINE_CLASS_VIDEO] = {
       .name = "VIDEO",
-      .engine_class = I915_ENGINE_CLASS_VIDEO,
+      .engine_class = INTEL_ENGINE_CLASS_VIDEO,
       .hw_class = 3,
       .elsp_reg = VCSUNIT0(EXECLIST_SUBMITPORT),
       .elsq_reg = VCSUNIT0(EXECLIST_SQ_CONTENTS),
       .status_reg = VCSUNIT0(EXECLIST_STATUS),
       .control_reg = VCSUNIT0(EXECLIST_CONTROL),
    },
-   [I915_ENGINE_CLASS_COPY] = {
+   [INTEL_ENGINE_CLASS_COPY] = {
       .name = "BLITTER",
-      .engine_class = I915_ENGINE_CLASS_COPY,
+      .engine_class = INTEL_ENGINE_CLASS_COPY,
       .hw_class = 2,
       .elsp_reg = BCSUNIT0(EXECLIST_SUBMITPORT),
       .elsq_reg = BCSUNIT0(EXECLIST_SQ_CONTENTS),
@@ -448,12 +447,12 @@ aub_write_ggtt(struct aub_file *aub, uint64_t virt_addr, uint64_t size, const vo
 }
 
 static const struct engine *
-engine_from_engine_class(enum drm_i915_gem_engine_class engine_class)
+engine_from_engine_class(enum intel_engine_class engine_class)
 {
    switch (engine_class) {
-   case I915_ENGINE_CLASS_RENDER:
-   case I915_ENGINE_CLASS_COPY:
-   case I915_ENGINE_CLASS_VIDEO:
+   case INTEL_ENGINE_CLASS_RENDER:
+   case INTEL_ENGINE_CLASS_COPY:
+   case INTEL_ENGINE_CLASS_VIDEO:
       return &engines[engine_class];
    default:
       unreachable("unknown ring");
@@ -463,19 +462,19 @@ engine_from_engine_class(enum drm_i915_gem_engine_class engine_class)
 static void
 get_context_init(const struct intel_device_info *devinfo,
                  const struct intel_context_parameters *params,
-                 enum drm_i915_gem_engine_class engine_class,
+                 enum intel_engine_class engine_class,
                  uint32_t *data,
                  uint32_t *size)
 {
    static const intel_context_init_t gfx8_contexts[] = {
-      [I915_ENGINE_CLASS_RENDER] = gfx8_render_context_init,
-      [I915_ENGINE_CLASS_COPY] = gfx8_blitter_context_init,
-      [I915_ENGINE_CLASS_VIDEO] = gfx8_video_context_init,
+      [INTEL_ENGINE_CLASS_RENDER] = gfx8_render_context_init,
+      [INTEL_ENGINE_CLASS_COPY] = gfx8_blitter_context_init,
+      [INTEL_ENGINE_CLASS_VIDEO] = gfx8_video_context_init,
    };
    static const intel_context_init_t gfx10_contexts[] = {
-      [I915_ENGINE_CLASS_RENDER] = gfx10_render_context_init,
-      [I915_ENGINE_CLASS_COPY] = gfx10_blitter_context_init,
-      [I915_ENGINE_CLASS_VIDEO] = gfx10_video_context_init,
+      [INTEL_ENGINE_CLASS_RENDER] = gfx10_render_context_init,
+      [INTEL_ENGINE_CLASS_COPY] = gfx10_blitter_context_init,
+      [INTEL_ENGINE_CLASS_VIDEO] = gfx10_video_context_init,
    };
 
    assert(devinfo->ver >= 8);
@@ -500,13 +499,13 @@ alloc_ggtt_address(struct aub_file *aub, uint64_t size)
 
 static void
 write_hwsp(struct aub_file *aub,
-           enum drm_i915_gem_engine_class engine_class)
+           enum intel_engine_class engine_class)
 {
    uint32_t reg = 0;
    switch (engine_class) {
-   case I915_ENGINE_CLASS_RENDER:  reg = RCSUNIT (HWS_PGA); break;
-   case I915_ENGINE_CLASS_COPY:    reg = BCSUNIT0(HWS_PGA); break;
-   case I915_ENGINE_CLASS_VIDEO:   reg = VCSUNIT0(HWS_PGA); break;
+   case INTEL_ENGINE_CLASS_RENDER:  reg = RCSUNIT (HWS_PGA); break;
+   case INTEL_ENGINE_CLASS_COPY:    reg = BCSUNIT0(HWS_PGA); break;
+   case INTEL_ENGINE_CLASS_VIDEO:   reg = VCSUNIT0(HWS_PGA); break;
    default:
       unreachable("unknown ring");
    }
@@ -518,7 +517,7 @@ static uint32_t
 write_engine_execlist_setup(struct aub_file *aub,
                             uint32_t ctx_id,
                             struct aub_hw_context *hw_ctx,
-                            enum drm_i915_gem_engine_class engine_class)
+                            enum intel_engine_class engine_class)
 {
    const struct engine *cs = engine_from_engine_class(engine_class);
    uint32_t context_size;
@@ -650,7 +649,7 @@ aub_context_find(struct aub_file *aub, uint32_t id)
 
 static struct aub_hw_context *
 aub_write_ensure_context(struct aub_file *aub, uint32_t ctx_id,
-                         enum drm_i915_gem_engine_class engine_class)
+                         enum intel_engine_class engine_class)
 {
    struct aub_context *ctx = aub_context_find(aub, ctx_id);
    assert(ctx != NULL);
@@ -773,15 +772,15 @@ static void
 aub_dump_ring_buffer_legacy(struct aub_file *aub,
                             uint64_t batch_offset,
                             uint64_t offset,
-                            enum drm_i915_gem_engine_class engine_class)
+                            enum intel_engine_class engine_class)
 {
    uint32_t ringbuffer[4096];
    unsigned aub_mi_bbs_len;
    int ring_count = 0;
    static const int engine_class_to_ring[] = {
-      [I915_ENGINE_CLASS_RENDER] = AUB_TRACE_TYPE_RING_PRB0,
-      [I915_ENGINE_CLASS_VIDEO]  = AUB_TRACE_TYPE_RING_PRB1,
-      [I915_ENGINE_CLASS_COPY]   = AUB_TRACE_TYPE_RING_PRB2,
+      [INTEL_ENGINE_CLASS_RENDER] = AUB_TRACE_TYPE_RING_PRB0,
+      [INTEL_ENGINE_CLASS_VIDEO]  = AUB_TRACE_TYPE_RING_PRB1,
+      [INTEL_ENGINE_CLASS_COPY]   = AUB_TRACE_TYPE_RING_PRB2,
    };
    int ring = engine_class_to_ring[engine_class];
 
@@ -810,7 +809,7 @@ aub_dump_ring_buffer_legacy(struct aub_file *aub,
 
 static void
 aub_write_ensure_hwsp(struct aub_file *aub,
-                      enum drm_i915_gem_engine_class engine_class)
+                      enum intel_engine_class engine_class)
 {
    uint64_t *hwsp_addr = &aub->engine_setup[engine_class].hwsp_addr;
 
@@ -823,7 +822,7 @@ aub_write_ensure_hwsp(struct aub_file *aub,
 
 void
 aub_write_exec(struct aub_file *aub, uint32_t ctx_id, uint64_t batch_addr,
-               uint64_t offset, enum drm_i915_gem_engine_class engine_class)
+               uint64_t offset, enum intel_engine_class engine_class)
 {
    const struct engine *cs = engine_from_engine_class(engine_class);
 
@@ -843,7 +842,7 @@ aub_write_exec(struct aub_file *aub, uint32_t ctx_id, uint64_t batch_addr,
 
 void
 aub_write_context_execlists(struct aub_file *aub, uint64_t context_addr,
-                            enum drm_i915_gem_engine_class engine_class)
+                            enum intel_engine_class engine_class)
 {
    const struct engine *cs = engine_from_engine_class(engine_class);
    uint64_t descriptor = ((uint64_t)1 << 62 | context_addr  | CONTEXT_FLAGS);

diff --git a/src/intel/tools/aub_write.h b/src/intel/tools/aub_write.h
index b4852d7..cd2652f 100644 (file)
--- a/src/intel/tools/aub_write.h
+++ b/src/intel/tools/aub_write.h
@@ -30,8 +30,6 @@
 #include <stdio.h>
 #include <stdlib.h>
 
-#include "drm-uapi/i915_drm.h"
-
 #include "dev/intel_device_info.h"
 #include "common/intel_gem.h"
 
@@ -74,7 +72,7 @@ struct aub_hw_context {
 /* GEM context, as seen from userspace */
 struct aub_context {
    uint32_t id;
-   struct aub_hw_context hw_contexts[I915_ENGINE_CLASS_VIDEO + 1];
+   struct aub_hw_context hw_contexts[INTEL_ENGINE_CLASS_VIDEO + 1];
 };
 
 struct aub_file {
@@ -96,7 +94,7 @@ struct aub_file {
 
    struct {
       uint64_t hwsp_addr;
-   } engine_setup[I915_ENGINE_CLASS_VIDEO_ENHANCE + 1];
+   } engine_setup[INTEL_ENGINE_CLASS_VIDEO_ENHANCE + 1];
 
    struct aub_context contexts[MAX_CONTEXT_COUNT];
    int num_contexts;
@@ -131,9 +129,9 @@ void aub_write_trace_block(struct aub_file *aub,
                            uint32_t type, void *virtual,
                            uint32_t size, uint64_t gtt_offset);
 void aub_write_exec(struct aub_file *aub, uint32_t ctx_id, uint64_t batch_addr,
-                    uint64_t offset, enum drm_i915_gem_engine_class engine_class);
+                    uint64_t offset, enum intel_engine_class engine_class);
 void aub_write_context_execlists(struct aub_file *aub, uint64_t context_addr,
-                                 enum drm_i915_gem_engine_class engine_class);
+                                 enum intel_engine_class engine_class);
 
 uint32_t aub_write_context_create(struct aub_file *aub, uint32_t *ctx_id);
 

diff --git a/src/intel/tools/aubinator.c b/src/intel/tools/aubinator.c
index cbe8a49..df613e0 100644 (file)
--- a/src/intel/tools/aubinator.c
+++ b/src/intel/tools/aubinator.c
@@ -148,7 +148,7 @@ get_bo(void *user_data, bool ppgtt, uint64_t addr)
 }
 
 static void
-handle_execlist_write(void *user_data, enum drm_i915_gem_engine_class engine, uint64_t context_descriptor)
+handle_execlist_write(void *user_data, enum intel_engine_class engine, uint64_t context_descriptor)
 {
    const uint32_t pphwsp_size = 4096;
    uint32_t pphwsp_addr = context_descriptor & 0xfffff000;
@@ -186,7 +186,7 @@ get_legacy_bo(void *user_data, bool ppgtt, uint64_t addr)
 }
 
 static void
-handle_ring_write(void *user_data, enum drm_i915_gem_engine_class engine,
+handle_ring_write(void *user_data, enum intel_engine_class engine,
                   const void *data, uint32_t data_len)
 {
    batch_ctx.user_data = &mem;

diff --git a/src/intel/tools/aubinator_error_decode.c b/src/intel/tools/aubinator_error_decode.c
index 74514f1..2021e9f 100644 (file)
--- a/src/intel/tools/aubinator_error_decode.c
+++ b/src/intel/tools/aubinator_error_decode.c
@@ -73,42 +73,42 @@ print_register(struct intel_spec *spec, const char *name, uint32_t reg)
 }
 
 struct ring_register_mapping {
-   enum drm_i915_gem_engine_class ring_class;
+   enum intel_engine_class ring_class;
    unsigned ring_instance;
    const char *register_name;
 };
 
 static const struct ring_register_mapping acthd_registers[] = {
-   { I915_ENGINE_CLASS_COPY, 0, "BCS_ACTHD_UDW" },
-   { I915_ENGINE_CLASS_VIDEO, 0, "VCS_ACTHD_UDW" },
-   { I915_ENGINE_CLASS_VIDEO, 1, "VCS2_ACTHD_UDW" },
-   { I915_ENGINE_CLASS_RENDER, 0, "ACTHD_UDW" },
-   { I915_ENGINE_CLASS_VIDEO_ENHANCE, 0, "VECS_ACTHD_UDW" },
+   { INTEL_ENGINE_CLASS_COPY, 0, "BCS_ACTHD_UDW" },
+   { INTEL_ENGINE_CLASS_VIDEO, 0, "VCS_ACTHD_UDW" },
+   { INTEL_ENGINE_CLASS_VIDEO, 1, "VCS2_ACTHD_UDW" },
+   { INTEL_ENGINE_CLASS_RENDER, 0, "ACTHD_UDW" },
+   { INTEL_ENGINE_CLASS_VIDEO_ENHANCE, 0, "VECS_ACTHD_UDW" },
 };
 
 static const struct ring_register_mapping ctl_registers[] = {
-   { I915_ENGINE_CLASS_COPY, 0, "BCS_RING_BUFFER_CTL" },
-   { I915_ENGINE_CLASS_VIDEO, 0, "VCS_RING_BUFFER_CTL" },
-   { I915_ENGINE_CLASS_VIDEO, 1, "VCS2_RING_BUFFER_CTL" },
-   { I915_ENGINE_CLASS_RENDER, 0, "RCS_RING_BUFFER_CTL" },
-   { I915_ENGINE_CLASS_VIDEO_ENHANCE, 0,  "VECS_RING_BUFFER_CTL" },
+   { INTEL_ENGINE_CLASS_COPY, 0, "BCS_RING_BUFFER_CTL" },
+   { INTEL_ENGINE_CLASS_VIDEO, 0, "VCS_RING_BUFFER_CTL" },
+   { INTEL_ENGINE_CLASS_VIDEO, 1, "VCS2_RING_BUFFER_CTL" },
+   { INTEL_ENGINE_CLASS_RENDER, 0, "RCS_RING_BUFFER_CTL" },
+   { INTEL_ENGINE_CLASS_VIDEO_ENHANCE, 0,  "VECS_RING_BUFFER_CTL" },
 };
 
 static const struct ring_register_mapping fault_registers[] = {
-   { I915_ENGINE_CLASS_COPY, 0, "BCS_FAULT_REG" },
-   { I915_ENGINE_CLASS_VIDEO, 0, "VCS_FAULT_REG" },
-   { I915_ENGINE_CLASS_RENDER, 0, "RCS_FAULT_REG" },
-   { I915_ENGINE_CLASS_VIDEO_ENHANCE, 0, "VECS_FAULT_REG" },
+   { INTEL_ENGINE_CLASS_COPY, 0, "BCS_FAULT_REG" },
+   { INTEL_ENGINE_CLASS_VIDEO, 0, "VCS_FAULT_REG" },
+   { INTEL_ENGINE_CLASS_RENDER, 0, "RCS_FAULT_REG" },
+   { INTEL_ENGINE_CLASS_VIDEO_ENHANCE, 0, "VECS_FAULT_REG" },
 };
 
 static int ring_name_to_class(const char *ring_name,
-                              enum drm_i915_gem_engine_class *class)
+                              enum intel_engine_class *class)
 {
    static const char *class_names[] = {
-      [I915_ENGINE_CLASS_RENDER] = "rcs",
-      [I915_ENGINE_CLASS_COPY] = "bcs",
-      [I915_ENGINE_CLASS_VIDEO] = "vcs",
-      [I915_ENGINE_CLASS_VIDEO_ENHANCE] = "vecs",
+      [INTEL_ENGINE_CLASS_RENDER] = "rcs",
+      [INTEL_ENGINE_CLASS_COPY] = "bcs",
+      [INTEL_ENGINE_CLASS_VIDEO] = "vcs",
+      [INTEL_ENGINE_CLASS_VIDEO_ENHANCE] = "vecs",
    };
    for (size_t i = 0; i < ARRAY_SIZE(class_names); i++) {
       if (strncmp(ring_name, class_names[i], strlen(class_names[i])))
@@ -123,11 +123,11 @@ static int ring_name_to_class(const char *ring_name,
       unsigned int class;
       int instance;
    } legacy_names[] = {
-      { "render", I915_ENGINE_CLASS_RENDER, 0 },
-      { "blt", I915_ENGINE_CLASS_COPY, 0 },
-      { "bsd", I915_ENGINE_CLASS_VIDEO, 0 },
-      { "bsd2", I915_ENGINE_CLASS_VIDEO, 1 },
-      { "vebox", I915_ENGINE_CLASS_VIDEO_ENHANCE, 0 },
+      { "render", INTEL_ENGINE_CLASS_RENDER, 0 },
+      { "blt", INTEL_ENGINE_CLASS_COPY, 0 },
+      { "bsd", INTEL_ENGINE_CLASS_VIDEO, 0 },
+      { "bsd2", INTEL_ENGINE_CLASS_VIDEO, 1 },
+      { "vebox", INTEL_ENGINE_CLASS_VIDEO_ENHANCE, 0 },
    };
    for (size_t i = 0; i < ARRAY_SIZE(legacy_names); i++) {
       if (strcmp(ring_name, legacy_names[i].name))
@@ -145,7 +145,7 @@ register_name_from_ring(const struct ring_register_mapping *mapping,
                         unsigned nb_mapping,
                         const char *ring_name)
 {
-   enum drm_i915_gem_engine_class class;
+   enum intel_engine_class class;
    int instance;
 
    instance = ring_name_to_class(ring_name, &class);
@@ -164,7 +164,7 @@ static const char *
 instdone_register_for_ring(const struct intel_device_info *devinfo,
                            const char *ring_name)
 {
-   enum drm_i915_gem_engine_class class;
+   enum intel_engine_class class;
    int instance;
 
    instance = ring_name_to_class(ring_name, &class);
@@ -172,16 +172,16 @@ instdone_register_for_ring(const struct intel_device_info *devinfo,
       return NULL;
 
    switch (class) {
-   case I915_ENGINE_CLASS_RENDER:
+   case INTEL_ENGINE_CLASS_RENDER:
       if (devinfo->ver == 6)
          return "INSTDONE_2";
       else
          return "INSTDONE_1";
 
-   case I915_ENGINE_CLASS_COPY:
+   case INTEL_ENGINE_CLASS_COPY:
       return "BCS_INSTDONE";
 
-   case I915_ENGINE_CLASS_VIDEO:
+   case INTEL_ENGINE_CLASS_VIDEO:
       switch (instance) {
       case 0:
          return "VCS_INSTDONE";
@@ -191,7 +191,7 @@ instdone_register_for_ring(const struct intel_device_info *devinfo,
          return NULL;
       }
 
-   case I915_ENGINE_CLASS_VIDEO_ENHANCE:
+   case INTEL_ENGINE_CLASS_VIDEO_ENHANCE:
       return "VECS_INSTDONE";
 
    default:
@@ -685,7 +685,7 @@ read_data_file(FILE *file)
 
 
    for (int s = 0; s < num_sections; s++) {
-      enum drm_i915_gem_engine_class class;
+      enum intel_engine_class class;
       ring_name_to_class(sections[s].ring_name, &class);
 
       printf("--- %s (%s) at 0x%08x %08x\n",

diff --git a/src/intel/tools/aubinator_viewer.cpp b/src/intel/tools/aubinator_viewer.cpp
index 022f4b8..01c339c 100644 (file)
--- a/src/intel/tools/aubinator_viewer.cpp
+++ b/src/intel/tools/aubinator_viewer.cpp
@@ -97,7 +97,7 @@ handle_mem_write(void *user_data, uint64_t phys_addr,
 }
 
 static void
-handle_ring_write(void *user_data, enum drm_i915_gem_engine_class engine,
+handle_ring_write(void *user_data, enum intel_engine_class engine,
                   const void *ring_data, uint32_t ring_data_len)
 {
    struct aub_file *file = (struct aub_file *) user_data;
@@ -695,7 +695,7 @@ update_batch_window(struct batch_window *window, bool reset, int exec_idx)
 }
 
 static void
-display_batch_ring_write(void *user_data, enum drm_i915_gem_engine_class engine,
+display_batch_ring_write(void *user_data, enum intel_engine_class engine,
                          const void *data, uint32_t data_len)
 {
    struct batch_window *window = (struct batch_window *) user_data;
@@ -707,7 +707,7 @@ display_batch_ring_write(void *user_data, enum drm_i915_gem_engine_class engine,
 
 static void
 display_batch_execlist_write(void *user_data,
-                             enum drm_i915_gem_engine_class engine,
+                             enum intel_engine_class engine,
                              uint64_t context_descriptor)
 {
    struct batch_window *window = (struct batch_window *) user_data;

diff --git a/src/intel/tools/aubinator_viewer.h b/src/intel/tools/aubinator_viewer.h
index defc6c1..7323cd5 100644 (file)
--- a/src/intel/tools/aubinator_viewer.h
+++ b/src/intel/tools/aubinator_viewer.h
@@ -70,7 +70,7 @@ struct aub_viewer_decode_ctx {
 
    const struct intel_device_info *devinfo;
    struct intel_spec *spec;
-   enum drm_i915_gem_engine_class engine;
+   enum intel_engine_class engine;
 
    struct aub_viewer_cfg *cfg;
    struct aub_viewer_decode_cfg *decode_cfg;

diff --git a/src/intel/tools/aubinator_viewer_decoder.cpp b/src/intel/tools/aubinator_viewer_decoder.cpp
index 3d9e7bd..024298c 100644 (file)
--- a/src/intel/tools/aubinator_viewer_decoder.cpp
+++ b/src/intel/tools/aubinator_viewer_decoder.cpp
@@ -43,7 +43,7 @@ aub_viewer_decode_ctx_init(struct aub_viewer_decode_ctx *ctx,
    ctx->get_state_size = get_state_size;
    ctx->user_data = user_data;
    ctx->devinfo = devinfo;
-   ctx->engine = I915_ENGINE_CLASS_RENDER;
+   ctx->engine = INTEL_ENGINE_CLASS_RENDER;
 
    ctx->cfg = cfg;
    ctx->decode_cfg = decode_cfg;

diff --git a/src/intel/tools/error2aub.c b/src/intel/tools/error2aub.c
index aa49766..97231ea 100644 (file)
--- a/src/intel/tools/error2aub.c
+++ b/src/intel/tools/error2aub.c
@@ -35,7 +35,6 @@
 #include "util/list.h"
 
 #include "aub_write.h"
-#include "drm-uapi/i915_drm.h"
 #include "intel_aub.h"
 
 #define fail_if(cond, ...) _fail_if(cond, NULL, __VA_ARGS__)
@@ -157,7 +156,7 @@ struct bo {
    uint8_t *data;
    uint64_t size;
 
-   enum drm_i915_gem_engine_class engine_class;
+   enum intel_engine_class engine_class;
    int engine_instance;
 
    struct list_head link;
@@ -166,7 +165,7 @@ struct bo {
 static struct bo *
 find_or_create(struct list_head *bo_list, uint64_t addr,
                enum address_space gtt,
-               enum drm_i915_gem_engine_class engine_class,
+               enum intel_engine_class engine_class,
                int engine_instance)
 {
    list_for_each_entry(struct bo, bo_entry, bo_list, link) {
@@ -189,24 +188,24 @@ find_or_create(struct list_head *bo_list, uint64_t addr,
 
 static void
 engine_from_name(const char *engine_name,
-                 enum drm_i915_gem_engine_class *engine_class,
+                 enum intel_engine_class *engine_class,
                  int *engine_instance)
 {
    const struct {
       const char *match;
-      enum drm_i915_gem_engine_class engine_class;
+      enum intel_engine_class engine_class;
       bool parse_instance;
    } rings[] = {
-      { "rcs", I915_ENGINE_CLASS_RENDER, true },
-      { "vcs", I915_ENGINE_CLASS_VIDEO, true },
-      { "vecs", I915_ENGINE_CLASS_VIDEO_ENHANCE, true },
-      { "bcs", I915_ENGINE_CLASS_COPY, true },
-      { "global", I915_ENGINE_CLASS_INVALID, false },
-      { "render command stream", I915_ENGINE_CLASS_RENDER, false },
-      { "blt command stream", I915_ENGINE_CLASS_COPY, false },
-      { "bsd command stream", I915_ENGINE_CLASS_VIDEO, false },
-      { "vebox command stream", I915_ENGINE_CLASS_VIDEO_ENHANCE, false },
-      { NULL, I915_ENGINE_CLASS_INVALID },
+      { "rcs", INTEL_ENGINE_CLASS_RENDER, true },
+      { "vcs", INTEL_ENGINE_CLASS_VIDEO, true },
+      { "vecs", INTEL_ENGINE_CLASS_VIDEO_ENHANCE, true },
+      { "bcs", INTEL_ENGINE_CLASS_COPY, true },
+      { "global", INTEL_ENGINE_CLASS_INVALID, false },
+      { "render command stream", INTEL_ENGINE_CLASS_RENDER, false },
+      { "blt command stream", INTEL_ENGINE_CLASS_COPY, false },
+      { "bsd command stream", INTEL_ENGINE_CLASS_VIDEO, false },
+      { "vebox command stream", INTEL_ENGINE_CLASS_VIDEO_ENHANCE, false },
+      { NULL, INTEL_ENGINE_CLASS_INVALID },
    }, *r;
 
    for (r = rings; r->match; r++) {
@@ -275,7 +274,7 @@ main(int argc, char *argv[])
 
    struct aub_file aub = {};
 
-   enum drm_i915_gem_engine_class active_engine_class = I915_ENGINE_CLASS_INVALID;
+   enum intel_engine_class active_engine_class = INTEL_ENGINE_CLASS_INVALID;
    int active_engine_instance = -1;
 
    enum address_space active_gtt = PPGTT;
@@ -286,7 +285,7 @@ main(int argc, char *argv[])
          uint32_t ring_buffer_head;
          uint32_t ring_buffer_tail;
       } instances[3];
-   } engines[I915_ENGINE_CLASS_VIDEO_ENHANCE + 1];
+   } engines[INTEL_ENGINE_CLASS_VIDEO_ENHANCE + 1];
    memset(engines, 0, sizeof(engines));
 
    int num_ring_bos = 0;
@@ -347,7 +346,7 @@ main(int argc, char *argv[])
 
       const char *global_start = "Pinned (global) [";
       if (strncmp(line, global_start, strlen(global_start)) == 0) {
-         active_engine_class = I915_ENGINE_CLASS_INVALID;
+         active_engine_class = INTEL_ENGINE_CLASS_INVALID;
          active_engine_instance = -1;
          active_gtt = GGTT;
          continue;
@@ -532,7 +531,7 @@ main(int argc, char *argv[])
       /* Use context id 0 -- if we are not using execlists it doesn't matter
        * anyway
        */
-      aub_write_exec(&aub, 0, batch_bo->addr, 0, I915_ENGINE_CLASS_RENDER);
+      aub_write_exec(&aub, 0, batch_bo->addr, 0, INTEL_ENGINE_CLASS_RENDER);
    }
 
    /* Cleanup */

diff --git a/src/intel/tools/intel_dump_gpu.c b/src/intel/tools/intel_dump_gpu.c
index f2f4133..a8f3e60 100644 (file)
--- a/src/intel/tools/intel_dump_gpu.c
+++ b/src/intel/tools/intel_dump_gpu.c
@@ -186,21 +186,21 @@ gem_mmap(int fd, uint32_t handle, uint64_t offset, uint64_t size)
    return (void *)(uintptr_t) mmap.addr_ptr;
 }
 
-static enum drm_i915_gem_engine_class
+static enum intel_engine_class
 engine_class_from_ring_flag(uint32_t ring_flag)
 {
    switch (ring_flag) {
    case I915_EXEC_DEFAULT:
    case I915_EXEC_RENDER:
-      return I915_ENGINE_CLASS_RENDER;
+      return INTEL_ENGINE_CLASS_RENDER;
    case I915_EXEC_BSD:
-      return I915_ENGINE_CLASS_VIDEO;
+      return INTEL_ENGINE_CLASS_VIDEO;
    case I915_EXEC_BLT:
-      return I915_ENGINE_CLASS_COPY;
+      return INTEL_ENGINE_CLASS_COPY;
    case I915_EXEC_VEBOX:
-      return I915_ENGINE_CLASS_VIDEO_ENHANCE;
+      return INTEL_ENGINE_CLASS_VIDEO_ENHANCE;
    default:
-      return I915_ENGINE_CLASS_INVALID;
+      return INTEL_ENGINE_CLASS_INVALID;
    }
 }
 

diff --git a/src/intel/tools/intel_noop_drm_shim.c b/src/intel/tools/intel_noop_drm_shim.c
index 0cc04c9..3f2a5a4 100644 (file)
--- a/src/intel/tools/intel_noop_drm_shim.c
+++ b/src/intel/tools/intel_noop_drm_shim.c
@@ -402,13 +402,13 @@ i915_ioctl_query(int fd, unsigned long request, void *arg)
 
             for (uint32_t e = 0; e < num_render; e++, info->num_engines++) {
                info->engines[info->num_engines].engine.engine_class =
-                  I915_ENGINE_CLASS_RENDER;
+                  INTEL_ENGINE_CLASS_RENDER;
                info->engines[info->num_engines].engine.engine_instance = e;
             }
 
             for (uint32_t e = 0; e < num_copy; e++, info->num_engines++) {
                info->engines[info->num_engines].engine.engine_class =
-                  I915_ENGINE_CLASS_COPY;
+                  INTEL_ENGINE_CLASS_COPY;
                info->engines[info->num_engines].engine.engine_instance = e;
             }