cpu-cluster.0-supply = <&buck2_reg>;
};
+&cmu_mif {
+ assigned-clocks = <&cmu_mif CLK_DIV_MIF_PRE>,
+ <&cmu_mif CLK_DIV_ACLK_CPIF_200>;
+ assigned-clock-rates = <400000000>, <100000000>;
+};
+
+&bus_g2d_400 {
+ devfreq-events = <&ppmu_d0_general_0>, <&ppmu_d1_general_0>;
+ vdd-supply = <&buck4_reg>;
+ exynos,saturation-ratio = <10>;
+ status = "okay";
+};
+
+&bus_g2d_266 {
+ devfreq = <&bus_g2d_400>;
+ status = "okay";
+};
+
+&bus_gscl {
+ devfreq = <&bus_g2d_400>;
+ status = "okay";
+};
+
+&bus_hevc {
+ devfreq = <&bus_g2d_400>;
+ status = "okay";
+};
+
+&bus_jpeg {
+ devfreq = <&bus_g2d_400>;
+ status = "okay";
+};
+
+&bus_mfc {
+ devfreq = <&bus_g2d_400>;
+ status = "okay";
+};
+
+&bus_mscl {
+ devfreq = <&bus_g2d_400>;
+ status = "okay";
+};
+
+&bus_noc0 {
+ devfreq = <&bus_g2d_400>;
+ status = "okay";
+};
+
+&bus_noc1 {
+ devfreq = <&bus_g2d_400>;
+ status = "okay";
+};
+
+&bus_noc2 {
+ devfreq = <&bus_g2d_400>;
+ status = "okay";
+};
+
+&bus_mif_400 {
+ devfreq-events = <&ppmu_d0_cpu_3>, <&ppmu_d1_cpu_3>;
+ vdd-supply = <&buck1_reg>;
+ exynos,saturation-ratio = <10>;
+ status = "okay";
+};
+
+&bus_mif_266 {
+ devfreq = <&bus_mif_400>;
+ status = "okay";
+};
+
+&bus_mif_200 {
+ devfreq = <&bus_mif_400>;
+ status = "okay";
+};
+
+&bus_mifnm_200 {
+ devfreq = <&bus_mif_400>;
+ status = "okay";
+};
+
+&bus_mifnd_133 {
+ devfreq = <&bus_mif_400>;
+ status = "okay";
+};
+
+&bus_mif_133 {
+ devfreq = <&bus_mif_400>;
+ status = "okay";
+};
+
+&bus_hpm_mif {
+ devfreq = <&bus_mif_400>;
+ status = "okay";
+};
+
&exynos_avs_cpu0 {
vdd-supply = <&buck3_reg>;
status = "okay";