[ARM64][AArch64] Update disassembler attributes to ARMv8.5 ISA with SVE extensions

This patch updates assembler attributes for AArch64 targets so we can disassemble newer instructions supported in ISA version 8.5 and SVE extensions.

Differential Revision: https://reviews.llvm.org/D62235

llvm-svn: 361451

diff --git a/lldb/source/Plugins/Disassembler/llvm/DisassemblerLLVMC.cpp b/lldb/source/Plugins/Disassembler/llvm/DisassemblerLLVMC.cpp
index 0df775a..36261a3 100644 (file)
--- a/lldb/source/Plugins/Disassembler/llvm/DisassemblerLLVMC.cpp
+++ b/lldb/source/Plugins/Disassembler/llvm/DisassemblerLLVMC.cpp
@@ -1188,10 +1188,10 @@ DisassemblerLLVMC::DisassemblerLLVMC(const ArchSpec &arch,
       features_str += "+dspr2,";
   }
 
-  // If any AArch64 variant, enable the ARMv8.2 ISA extensions so we can
-  // disassemble newer instructions.
+  // If any AArch64 variant, enable the ARMv8.5 ISA with SVE extensions so we
+  // can disassemble newer instructions.
   if (triple.getArch() == llvm::Triple::aarch64)
-    features_str += "+v8.2a";
+    features_str += "+v8.5a,+sve2";
 
   if (triple.getArch() == llvm::Triple::aarch64
       && triple.getVendor() == llvm::Triple::Apple) {