radeonsi: remove AMD_DEBUG=sisched option

sisched is not maintained anymore in LLVM.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4059>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4059>

diff --git a/docs/envvars.html b/docs/envvars.html
index eacd1b6..4a90185 100644 (file)
--- a/docs/envvars.html
+++ b/docs/envvars.html
@@ -712,8 +712,6 @@ Mesa EGL supports different sets of environment variables.  See the
   <dt><code>preoptir</code></dt>
   <dd>Print the LLVM IR before initial optimizations</dd>
   <h4>Shader compilation tuning flags:</h4>
-  <dt><code>sisched</code></dt>
-  <dd>Enable LLVM SI Machine Instruction Scheduler.</dd>
   <dt><code>gisel</code></dt>
   <dd>Enable LLVM global instruction selector.</dd>
   <dt><code>w32ge</code></dt>

diff --git a/src/amd/llvm/ac_llvm_util.c b/src/amd/llvm/ac_llvm_util.c
index ddc8fee..5cdb512 100644 (file)
--- a/src/amd/llvm/ac_llvm_util.c
+++ b/src/amd/llvm/ac_llvm_util.c
@@ -169,10 +169,9 @@ static LLVMTargetMachineRef ac_create_target_machine(enum radeon_family family,
        LLVMTargetRef target = ac_get_llvm_target(triple);
 
        snprintf(features, sizeof(features),
-                "+DumpCode,-fp32-denormals,+fp64-denormals%s%s%s%s%s%s",
+                "+DumpCode,-fp32-denormals,+fp64-denormals%s%s%s%s%s",
                 family >= CHIP_NAVI10 && !(tm_options & AC_TM_WAVE32) ?
                         ",+wavefrontsize64,-wavefrontsize32" : "",
-                tm_options & AC_TM_SISCHED ? ",+si-scheduler" : "",
                 tm_options & AC_TM_FORCE_ENABLE_XNACK ? ",+xnack" : "",
                 tm_options & AC_TM_FORCE_DISABLE_XNACK ? ",-xnack" : "",
                 tm_options & AC_TM_PROMOTE_ALLOCA_TO_SCRATCH ? ",-promote-alloca" : "",

diff --git a/src/amd/llvm/ac_llvm_util.h b/src/amd/llvm/ac_llvm_util.h
index de4ccfb..0037247 100644 (file)
--- a/src/amd/llvm/ac_llvm_util.h
+++ b/src/amd/llvm/ac_llvm_util.h
@@ -58,15 +58,14 @@ enum ac_func_attr {
 
 enum ac_target_machine_options {
        AC_TM_SUPPORTS_SPILL = (1 << 0),
-       AC_TM_SISCHED = (1 << 1),
-       AC_TM_FORCE_ENABLE_XNACK = (1 << 2),
-       AC_TM_FORCE_DISABLE_XNACK = (1 << 3),
-       AC_TM_PROMOTE_ALLOCA_TO_SCRATCH = (1 << 4),
-       AC_TM_CHECK_IR = (1 << 5),
-       AC_TM_ENABLE_GLOBAL_ISEL = (1 << 6),
-       AC_TM_CREATE_LOW_OPT = (1 << 7),
-       AC_TM_NO_LOAD_STORE_OPT = (1 << 8),
-       AC_TM_WAVE32 = (1 << 9),
+       AC_TM_FORCE_ENABLE_XNACK = (1 << 1),
+       AC_TM_FORCE_DISABLE_XNACK = (1 << 2),
+       AC_TM_PROMOTE_ALLOCA_TO_SCRATCH = (1 << 3),
+       AC_TM_CHECK_IR = (1 << 4),
+       AC_TM_ENABLE_GLOBAL_ISEL = (1 << 5),
+       AC_TM_CREATE_LOW_OPT = (1 << 6),
+       AC_TM_NO_LOAD_STORE_OPT = (1 << 7),
+       AC_TM_WAVE32 = (1 << 8),
 };
 
 enum ac_float_mode {

diff --git a/src/gallium/drivers/radeonsi/driinfo_radeonsi.h b/src/gallium/drivers/radeonsi/driinfo_radeonsi.h
index ff81a9b..59b3d0a 100644 (file)
--- a/src/gallium/drivers/radeonsi/driinfo_radeonsi.h
+++ b/src/gallium/drivers/radeonsi/driinfo_radeonsi.h
@@ -1,7 +1,6 @@
 // DriConf options specific to radeonsi
 DRI_CONF_SECTION_PERFORMANCE
     DRI_CONF_ADAPTIVE_SYNC("true")
-    DRI_CONF_RADEONSI_ENABLE_SISCHED("false")
     DRI_CONF_RADEONSI_ASSUME_NO_Z_FIGHTS("false")
     DRI_CONF_RADEONSI_COMMUTATIVE_BLEND_ADD("false")
     DRI_CONF_RADEONSI_ZERO_ALL_VRAM_ALLOCS("false")

diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c
index ea4f1bf..157a198 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -61,7 +61,6 @@ static const struct debug_named_value debug_options[] = {
        { "preoptir", DBG(PREOPT_IR), "Print the LLVM IR before initial optimizations" },
 
        /* Shader compiler options the shader cache should be aware of: */
-       { "sisched", DBG(SI_SCHED), "Enable LLVM SI Machine Instruction Scheduler." },
        { "gisel", DBG(GISEL), "Enable LLVM global instruction selector." },
        { "w32ge", DBG(W32_GE), "Use Wave32 for vertex, tessellation, and geometry shaders." },
        { "w32ps", DBG(W32_PS), "Use Wave32 for pixel shaders." },
@@ -141,7 +140,6 @@ void si_init_compiler(struct si_screen *sscreen, struct ac_llvm_compiler *compil
                                       sscreen->info.chip_class <= GFX8;
 
        enum ac_target_machine_options tm_options =
-               (sscreen->debug_flags & DBG(SI_SCHED) ? AC_TM_SISCHED : 0) |
                (sscreen->debug_flags & DBG(GISEL) ? AC_TM_ENABLE_GLOBAL_ISEL : 0) |
                (sscreen->info.chip_class >= GFX9 ? AC_TM_FORCE_ENABLE_XNACK : 0) |
                (sscreen->info.chip_class < GFX9 ? AC_TM_FORCE_DISABLE_XNACK : 0) |
@@ -929,7 +927,7 @@ static void si_disk_cache_create(struct si_screen *sscreen)
        disk_cache_format_hex_id(cache_id, sha1, 20 * 2);
 
        /* These flags affect shader compilation. */
-       #define ALL_FLAGS (DBG(SI_SCHED) | DBG(GISEL))
+       #define ALL_FLAGS (DBG(GISEL))
        uint64_t shader_debug_flags = sscreen->debug_flags & ALL_FLAGS;
 
        /* Add the high bits of 32-bit addresses, which affects
@@ -1029,8 +1027,6 @@ radeonsi_screen_create_impl(struct radeon_winsys *ws,
        if (driQueryOptionb(config->options,
                            "glsl_correct_derivatives_after_discard"))
                sscreen->debug_flags |= DBG(FS_CORRECT_DERIVS_AFTER_KILL);
-       if (driQueryOptionb(config->options, "radeonsi_enable_sisched"))
-               sscreen->debug_flags |= DBG(SI_SCHED);
 
        if (sscreen->debug_flags & DBG(INFO))
                ac_print_gpu_info(&sscreen->info);

diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h
index 5c349fb..41c5bd4 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_pipe.h
+++ b/src/gallium/drivers/radeonsi/si_pipe.h
@@ -150,7 +150,6 @@ enum {
 
        /* Shader compiler options the shader cache should be aware of: */
        DBG_FS_CORRECT_DERIVS_AFTER_KILL,
-       DBG_SI_SCHED,
        DBG_GISEL,
        DBG_W32_GE,
        DBG_W32_PS,

diff --git a/src/util/xmlpool/ca.po b/src/util/xmlpool/ca.po
index e8ab8eb..bedb5c9 100644 (file)
--- a/src/util/xmlpool/ca.po
+++ b/src/util/xmlpool/ca.po
@@ -279,10 +279,6 @@ msgid ""
 "(-1) CSMT is enabled on known thread-safe drivers."
 msgstr ""
 
-#: src/util/xmlpool/t_options.h:323
-msgid "Use the LLVM sisched option for shader compiles"
-msgstr ""
-
 #: src/util/xmlpool/t_options.h:328
 msgid ""
 "Assume no Z fights (enables aggressive out-of-order rasterization to improve "

diff --git a/src/util/xmlpool/de.po b/src/util/xmlpool/de.po
index a28a5ed..2baa93c 100644 (file)
--- a/src/util/xmlpool/de.po
+++ b/src/util/xmlpool/de.po
@@ -254,10 +254,6 @@ msgid ""
 "(-1) CSMT is enabled on known thread-safe drivers."
 msgstr ""
 
-#: src/util/xmlpool/t_options.h:323
-msgid "Use the LLVM sisched option for shader compiles"
-msgstr ""
-
 #: src/util/xmlpool/t_options.h:328
 msgid ""
 "Assume no Z fights (enables aggressive out-of-order rasterization to improve "

diff --git a/src/util/xmlpool/es.po b/src/util/xmlpool/es.po
index e6cf2d6..916a4d6 100644 (file)
--- a/src/util/xmlpool/es.po
+++ b/src/util/xmlpool/es.po
@@ -265,10 +265,6 @@ msgid ""
 "(-1) CSMT is enabled on known thread-safe drivers."
 msgstr ""
 
-#: src/util/xmlpool/t_options.h:323
-msgid "Use the LLVM sisched option for shader compiles"
-msgstr ""
-
 #: src/util/xmlpool/t_options.h:328
 msgid ""
 "Assume no Z fights (enables aggressive out-of-order rasterization to improve "

diff --git a/src/util/xmlpool/fr.po b/src/util/xmlpool/fr.po
index 110bb15..7722659 100644 (file)
--- a/src/util/xmlpool/fr.po
+++ b/src/util/xmlpool/fr.po
@@ -253,10 +253,6 @@ msgid ""
 "(-1) CSMT is enabled on known thread-safe drivers."
 msgstr ""
 
-#: src/util/xmlpool/t_options.h:323
-msgid "Use the LLVM sisched option for shader compiles"
-msgstr ""
-
 #: src/util/xmlpool/t_options.h:328
 msgid ""
 "Assume no Z fights (enables aggressive out-of-order rasterization to improve "

diff --git a/src/util/xmlpool/nl.po b/src/util/xmlpool/nl.po
index 9970583..16c8c28 100644 (file)
--- a/src/util/xmlpool/nl.po
+++ b/src/util/xmlpool/nl.po
@@ -249,10 +249,6 @@ msgid ""
 "(-1) CSMT is enabled on known thread-safe drivers."
 msgstr ""
 
-#: src/util/xmlpool/t_options.h:323
-msgid "Use the LLVM sisched option for shader compiles"
-msgstr ""
-
 #: src/util/xmlpool/t_options.h:328
 msgid ""
 "Assume no Z fights (enables aggressive out-of-order rasterization to improve "

diff --git a/src/util/xmlpool/sv.po b/src/util/xmlpool/sv.po
index ddbb0ae..f44860e 100644 (file)
--- a/src/util/xmlpool/sv.po
+++ b/src/util/xmlpool/sv.po
@@ -247,10 +247,6 @@ msgid ""
 "(-1) CSMT is enabled on known thread-safe drivers."
 msgstr ""
 
-#: src/util/xmlpool/t_options.h:323
-msgid "Use the LLVM sisched option for shader compiles"
-msgstr ""
-
 #: src/util/xmlpool/t_options.h:328
 msgid ""
 "Assume no Z fights (enables aggressive out-of-order rasterization to improve "

diff --git a/src/util/xmlpool/t_options.h b/src/util/xmlpool/t_options.h
index 1d8ea07..a00c937 100644 (file)
--- a/src/util/xmlpool/t_options.h
+++ b/src/util/xmlpool/t_options.h
@@ -373,11 +373,6 @@ DRI_CONF_OPT_END
  * \brief radeonsi specific configuration options
  */
 
-#define DRI_CONF_RADEONSI_ENABLE_SISCHED(def) \
-DRI_CONF_OPT_BEGIN_B(radeonsi_enable_sisched, def) \
-        DRI_CONF_DESC(en,gettext("Use the LLVM sisched option for shader compiles")) \
-DRI_CONF_OPT_END
-
 #define DRI_CONF_RADEONSI_ASSUME_NO_Z_FIGHTS(def) \
 DRI_CONF_OPT_BEGIN_B(radeonsi_assume_no_z_fights, def) \
         DRI_CONF_DESC(en,gettext("Assume no Z fights (enables aggressive out-of-order rasterization to improve performance; may cause rendering errors)")) \