sfn_log << SfnLog::trans << "Merge registers\n";
impl->remap_registers();
}
+
+ impl->get_array_info(pipe_shader->shader);
+
sfn_log << SfnLog::trans << "Finished translating to R600 IR\n";
return true;
}
m_output.push_back(InstructionBlock(m_nesting_depth, m_block_number++));
}
+void ShaderFromNirProcessor::get_array_info(r600_shader& shader) const
+{
+ shader.num_arrays = m_reg_arrays.size();
+ shader.arrays = (r600_shader_array *)calloc(shader.num_arrays, sizeof(r600_shader_array));
+ for (int i = 0; i < shader.num_arrays; ++i) {
+ shader.arrays[i].comp_mask = m_reg_arrays[i]->mask();
+ shader.arrays[i].gpr_start = m_reg_arrays[i]->sel();
+ shader.arrays[i].gpr_count = m_reg_arrays[i]->size();
+ }
+}
+
void ShaderFromNirProcessor::finalize()
{
do_finalize();
return m_atomic_base_map[base];
}
+ void get_array_info(r600_shader& shader) const;
+
protected:
void set_var_address(nir_deref_instr *instr);
uint32_t sel() const override;
+ uint32_t mask() const { return m_component_mask; };
+
size_t size() const {return m_values.size();}
PValue get_indirect(unsigned index, PValue indirect, unsigned component);
uint32_t mask = ((1 << a.ncomponents) - 1) << ncomponents;
- PValue array = PValue(new GPRArray(current_index, a.length, mask, ncomponents));
+ PGPRArray array = PGPRArray(new GPRArray(current_index, a.length, mask, ncomponents));
+
+ m_reg_arrays.push_back(array);
sfn_log << SfnLog::reg << "Add array at "<< current_index
<< " of size " << a.length << " with " << a.ncomponents
GPRVector get_temp_vec4();
+protected:
+ std::vector<PGPRArray> m_reg_arrays;
+
private:
unsigned get_ssa_register_index(const nir_ssa_def& ssa) const;
unsigned m_next_register_index;
- std::map<unsigned, PGPRArray> m_arrays_map;
std::map<uint32_t, PValue> m_literals;