I don't think any of these registers are used in contexts where this
would do anything yet.
return AMDGPU::NoRegister;
}
+
+bool SIRegisterInfo::isConstantPhysReg(MCRegister PhysReg) const {
+ switch (PhysReg) {
+ case AMDGPU::SGPR_NULL:
+ case AMDGPU::SRC_SHARED_BASE:
+ case AMDGPU::SRC_PRIVATE_BASE:
+ case AMDGPU::SRC_SHARED_LIMIT:
+ case AMDGPU::SRC_PRIVATE_LIMIT:
+ return true;
+ default:
+ return false;
+ }
+}
return isVGPR(MRI, Reg) || isAGPR(MRI, Reg);
}
+ bool isConstantPhysReg(MCRegister PhysReg) const override;
+
bool isDivergentRegClass(const TargetRegisterClass *RC) const override {
return !isSGPRClass(RC);
}