struct drm_psb_private * dev_priv = dev->dev_private;
struct drm_crtc * crtc = dbi_output->base.base.crtc;
struct psb_intel_crtc * psb_crtc = (crtc) ? to_psb_intel_crtc(crtc) : NULL;
- u32 dpll_reg = MRST_DPLL_A;
+ u32 dpll_reg = PSB_DSI_PLL_CTRL;
u32 pipeconf_reg = PSB_PIPECONF(PSB_PIPE_A);
u32 dspcntr_reg = PSB_DSPCNTR(PSB_PIPE_A);
u32 dspbase_reg = PSB_DSPBASE(PSB_PIPE_A);
return;
if(pipe == 2) {
- dpll_reg = MRST_DPLL_A;
+ dpll_reg = PSB_DSI_PLL_CTRL;
pipeconf_reg = PSB_PIPECONF(PSB_PIPE_C);
dspcntr_reg = PSB_DSPCNTR(PSB_PIPE_C);
dspbase_reg = PSB_DSPBASE(PSB_PIPE_C);
struct drm_crtc * crtc = dbi_output->base.base.crtc;
struct psb_intel_crtc * psb_crtc = (crtc) ? to_psb_intel_crtc(crtc) : NULL;
u32 reg_val;
- u32 dpll_reg = MRST_DPLL_A;
+ u32 dpll_reg = PSB_DSI_PLL_CTRL;
u32 pipeconf_reg = PSB_PIPECONF(PSB_PIPE_A);
u32 dspcntr_reg = PSB_DSPCNTR(PSB_PIPE_A);
return;
if(pipe == 2) {
- dpll_reg = MRST_DPLL_A;
+ dpll_reg = PSB_DSI_PLL_CTRL;
pipeconf_reg = PSB_PIPECONF(PSB_PIPE_C);
dspcntr_reg = PSB_DSPCNTR(PSB_PIPE_C);
}
static bool mdfld_dbi_is_in_dsr(struct drm_device * dev)
{
- if(REG_READ(MRST_DPLL_A) & DPLL_VCO_ENABLE)
+ if (REG_READ(PSB_DSI_PLL_CTRL) & DPLL_VCO_ENABLE)
return false;
if ((REG_READ(PSB_PIPECONF(PSB_PIPE_A)) & PIPEACONF_ENABLE) ||
(REG_READ(PSB_PIPECONF(PSB_PIPE_C)) & PIPEACONF_ENABLE))
struct mdfld_dbi_dpu_info * dpu_info = dev_priv->dbi_dpu_info;
bool pipe_updated[2];
unsigned long irq_flags;
- u32 dpll_reg = MRST_DPLL_A;
+ u32 dpll_reg = PSB_DSI_PLL_CTRL;
u32 dspcntr_reg = PSB_DSPCNTR(PSB_PIPE_A);
u32 pipeconf_reg = PSB_PIPECONF(PSB_PIPE_A);
u32 dsplinoff_reg = PSB_DSPLINOFF(PSB_PIPE_A);
struct drm_crtc * crtc = dbi_output->base.base.crtc;
struct psb_intel_crtc * psb_crtc = (crtc) ? to_psb_intel_crtc(crtc) : NULL;
u32 reg_val;
- u32 dpll_reg = MRST_DPLL_A;
+ u32 dpll_reg = PSB_DSI_PLL_CTRL;
u32 pipeconf_reg = PSB_PIPECONF(PSB_PIPE_A);
u32 dspcntr_reg = PSB_DSPCNTR(PSB_PIPE_A);
u32 dspbase_reg = PSB_DSPBASE(PSB_PIPE_A);
return -EAGAIN;
if(pipe == 2) {
- dpll_reg = MRST_DPLL_A;
+ dpll_reg = PSB_DSI_PLL_CTRL;
pipeconf_reg = PSB_PIPECONF(PSB_PIPE_C);
dspcntr_reg = PSB_DSPCNTR(PSB_PIPE_C);
dspbase_reg = MDFLD_DSPCBASE;
tc35876x_toshiba_bridge_panel_on(dev);
udelay(100);
/* Now start the DSI clock */
- REG_WRITE(MRST_DPLL_A, 0x00);
- REG_WRITE(MRST_FPA0, 0xC1);
- REG_WRITE(MRST_DPLL_A, 0x00800000);
+ REG_WRITE(PSB_DSI_PLL_CTRL, 0x00);
+ REG_WRITE(PSB_DSI_PLL_DIV_M1, 0xC1);
+ REG_WRITE(PSB_DSI_PLL_CTRL, 0x00800000);
udelay(500);
- REG_WRITE(MRST_DPLL_A, 0x80800000);
+ REG_WRITE(PSB_DSI_PLL_CTRL, 0x80800000);
if (REG_BIT_WAIT(pipeconf_reg, 1, 29))
dev_err(&dev->pdev->dev, "%s: DSI PLL lock timeout\n",
/*init regs*/
if(pipe == 0) {
- pkg_sender->dpll_reg = MRST_DPLL_A;
+ pkg_sender->dpll_reg = PSB_DSI_PLL_CTRL;
pkg_sender->dspcntr_reg = PSB_DSPCNTR(PSB_PIPE_A);
pkg_sender->pipeconf_reg = PSB_PIPECONF(PSB_PIPE_A);
pkg_sender->dsplinoff_reg = PSB_DSPLINOFF(PSB_PIPE_A);
pkg_sender->dspsurf_reg = PSB_DSPSURF(PSB_PIPE_A);
pkg_sender->pipestat_reg = PSB_PIPESTAT(PSB_PIPE_A);
} else if (pipe == 2) {
- pkg_sender->dpll_reg = MRST_DPLL_A;
+ pkg_sender->dpll_reg = PSB_DSI_PLL_CTRL;
pkg_sender->dspcntr_reg = PSB_DSPCNTR(PSB_PIPE_C);
pkg_sender->pipeconf_reg = PSB_PIPECONF(PSB_PIPE_C);
pkg_sender->dsplinoff_reg = PSB_DSPLINOFF(PSB_PIPE_C);
*/
void mdfld_disable_crtc (struct drm_device *dev, int pipe)
{
- int dpll_reg = MRST_DPLL_A;
+ int dpll_reg = PSB_DSI_PLL_CTRL;
int dspcntr_reg = PSB_DSPCNTR(PSB_PIPE_A);
int dspbase_reg = PSB_DSPBASE(PSB_PIPE_A);
int pipeconf_reg = PSB_PIPECONF(PSB_PIPE_A);
case 0:
break;
case 1:
- dpll_reg = MDFLD_DPLL_B;
+ dpll_reg = PSB_DPLL_CTRL;
dspcntr_reg = PSB_DSPCNTR(PSB_PIPE_B);
dspbase_reg = PSB_DSPSURF(PSB_PIPE_B);
pipeconf_reg = PSB_PIPECONF(PSB_PIPE_B);
break;
case 2:
- dpll_reg = MRST_DPLL_A;
+ dpll_reg = PSB_DSI_PLL_CTRL;
dspcntr_reg = PSB_DSPCNTR(PSB_PIPE_C);
dspbase_reg = PSB_DSPBASE(PSB_PIPE_C);
pipeconf_reg = PSB_PIPECONF(PSB_PIPE_C);
DRM_DRIVER_PRIVATE_T *dev_priv = dev->dev_private;
struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
int pipe = psb_intel_crtc->pipe;
- int dpll_reg = MRST_DPLL_A;
+ int dpll_reg = PSB_DSI_PLL_CTRL;
int dspcntr_reg = PSB_DSPCNTR(PSB_PIPE_A);
int dspbase_reg = PSB_DSPBASE(PSB_PIPE_A);
int pipeconf_reg = PSB_PIPECONF(PSB_PIPE_A);
pipeconf_reg = PSB_PIPECONF(PSB_PIPE_B);
pipeconf = dev_priv->pipeconf1;
dspcntr = dev_priv->dspcntr1;
- dpll_reg = MDFLD_DPLL_B;
+ dpll_reg = PSB_DPLL_CTRL;
break;
case 2:
- dpll_reg = MRST_DPLL_A;
+ dpll_reg = PSB_DSI_PLL_CTRL;
dspcntr_reg = PSB_DSPCNTR(PSB_PIPE_C);
dspbase_reg = PSB_DSPBASE(PSB_PIPE_C);
pipeconf_reg = PSB_PIPECONF(PSB_PIPE_C);
struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
DRM_DRIVER_PRIVATE_T *dev_priv = dev->dev_private;
int pipe = psb_intel_crtc->pipe;
- int fp_reg = MRST_FPA0;
- int dpll_reg = MRST_DPLL_A;
+ int fp_reg = PSB_DSI_PLL_DIV_M1;
+ int dpll_reg = PSB_DSI_PLL_CTRL;
int dspcntr_reg = PSB_DSPCNTR(PSB_PIPE_A);
int pipeconf_reg = PSB_PIPECONF(PSB_PIPE_A);
int htot_reg = PSB_HTOTAL(PSB_PIPE_A);
pipesrc_reg = PSB_PIPESRC(PSB_PIPE_B);
pipeconf = &dev_priv->pipeconf1;
dspcntr = &dev_priv->dspcntr1;
- fp_reg = MDFLD_DPLL_DIV0;
- dpll_reg = MDFLD_DPLL_B;
+ fp_reg = PSB_DPLL_DIV0;
+ dpll_reg = PSB_DPLL_CTRL;
break;
case 2:
- dpll_reg = MRST_DPLL_A;
+ dpll_reg = PSB_DSI_PLL_CTRL;
dspcntr_reg = PSB_DSPCNTR(PSB_PIPE_C);
pipeconf_reg = PSB_PIPECONF(PSB_PIPE_C);
htot_reg = PSB_HTOTAL(PSB_PIPE_C);
/*
* MOORESTOWN delta registers
*/
-#define MRST_DPLL_A 0x0f014
-#define MDFLD_DPLL_B 0x0f018
+#define PSB_DSI_PLL_CTRL 0x0f014
+#define PSB_DPLL_CTRL 0x0f018
#define MDFLD_INPUT_REF_SEL (1 << 14)
#define MDFLD_VCO_SEL (1 << 16)
#define DPLLA_MODE_LVDS (2 << 26) /* mrst */
#define MDFLD_PLL_LATCHEN (1 << 28)
#define MDFLD_PWR_GATE_EN (1 << 30)
#define MDFLD_P1_MASK (0x1FF << 17)
-#define MRST_FPA0 0x0f040
-#define MRST_FPA1 0x0f044
-#define MDFLD_DPLL_DIV0 0x0f048
-#define MDFLD_DPLL_DIV1 0x0f04c
+#define PSB_DSI_PLL_DIV_M1 0x0f040
+#define PSB_DPLL_DIV0 0x0f048
#define MRST_PERF_MODE 0x020f4
/* MEDFIELD HDMI registers */
switch (pipe) {
case 0:
- pr->pll_ctrl = PSB_RVDC32(MRST_DPLL_A);
- pr->pll_div = PSB_RVDC32(MRST_FPA0);
+ pr->pll_ctrl = PSB_RVDC32(PSB_DSI_PLL_CTRL);
+ pr->pll_div = PSB_RVDC32(PSB_DSI_PLL_DIV_M1);
pr->mipi_ctrl = PSB_RVDC32(MIPI_PORT_CONTROL(pipe));
break;
case 1:
- pr->pll_ctrl = PSB_RVDC32(MDFLD_DPLL_B);
- pr->pll_div = PSB_RVDC32(MDFLD_DPLL_DIV0);
-
+ pr->pll_ctrl = PSB_RVDC32(PSB_DPLL_CTRL);
+ pr->pll_div = PSB_RVDC32(PSB_DPLL_DIV0);
dev_priv->savePFIT_CONTROL = PSB_RVDC32(PFIT_CONTROL);
dev_priv->savePFIT_PGM_RATIOS = PSB_RVDC32(PFIT_PGM_RATIOS);
dev_priv->saveHDMIPHYMISCCTL = PSB_RVDC32(HDMIPHYMISCCTL);
switch (pipe) {
case 0:
- dpll_reg = MRST_DPLL_A;
- pll_div_reg = MRST_FPA0;
+ dpll_reg = PSB_DSI_PLL_CTRL;
+ pll_div_reg = PSB_DSI_PLL_DIV_M1;
dsi_config = dev_priv->dsi_configs[0];
break;
case 1:
- dpll_reg = MDFLD_DPLL_B;
- pll_div_reg = MDFLD_DPLL_DIV0;
+ dpll_reg = PSB_DPLL_CTRL;
+ pll_div_reg = PSB_DPLL_DIV0;
break;
case 2:
dsi_output = dev_priv->dbi_output2;
struct drm_crtc * crtc = dbi_output->base.base.crtc;
struct psb_intel_crtc * psb_crtc = (crtc) ? to_psb_intel_crtc(crtc) : NULL;
- u32 dpll_reg = MRST_DPLL_A;
+ u32 dpll_reg = PSB_DSI_PLL_CTRL;
u32 dspcntr_reg = PSB_DSPCNTR(PSB_PIPE_A);
u32 pipeconf_reg = PSB_PIPECONF(PSB_PIPE_A);
u32 dsplinoff_reg = PSB_DSPLINOFF(PSB_PIPE_A);