gfx: drv: rename PLL/PLL DIV registers according to the TRM
authorImre Deak <imre.deak@intel.com>
Tue, 6 Mar 2012 19:17:31 +0000 (21:17 +0200)
committerMarkus Lehtonen <markus.lehtonen@linux.intel.com>
Tue, 3 Jul 2012 09:30:30 +0000 (12:30 +0300)
Rename the PLL and PLL DIV registers according to the TRM and remove the
definitions for the non-existant MRST_FPA1 and MDFLD_DPLL_DIV1.

Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com>
drivers/staging/mrst/drv/mdfld_dsi_dbi.c
drivers/staging/mrst/drv/mdfld_dsi_dbi_dpu.c
drivers/staging/mrst/drv/mdfld_dsi_dpi.c
drivers/staging/mrst/drv/mdfld_dsi_pkg_sender.c
drivers/staging/mrst/drv/psb_intel_display.c
drivers/staging/mrst/drv/psb_intel_reg.h
drivers/staging/mrst/drv/psb_powermgmt.c
drivers/staging/mrst/drv/tpo_cmd.c

index 065a77a..cd1f725 100644 (file)
@@ -184,7 +184,7 @@ void mdfld_dsi_dbi_enter_dsr (struct mdfld_dsi_dbi_output * dbi_output, int pipe
        struct drm_psb_private * dev_priv = dev->dev_private;
        struct drm_crtc * crtc = dbi_output->base.base.crtc;
        struct psb_intel_crtc * psb_crtc = (crtc) ? to_psb_intel_crtc(crtc) : NULL; 
-       u32 dpll_reg = MRST_DPLL_A;
+       u32 dpll_reg = PSB_DSI_PLL_CTRL;
        u32 pipeconf_reg = PSB_PIPECONF(PSB_PIPE_A);
        u32 dspcntr_reg = PSB_DSPCNTR(PSB_PIPE_A);
        u32 dspbase_reg = PSB_DSPBASE(PSB_PIPE_A);
@@ -201,7 +201,7 @@ void mdfld_dsi_dbi_enter_dsr (struct mdfld_dsi_dbi_output * dbi_output, int pipe
                return;
                
        if(pipe == 2) {
-               dpll_reg = MRST_DPLL_A;
+               dpll_reg = PSB_DSI_PLL_CTRL;
                pipeconf_reg = PSB_PIPECONF(PSB_PIPE_C);
                dspcntr_reg = PSB_DSPCNTR(PSB_PIPE_C);
                dspbase_reg = PSB_DSPBASE(PSB_PIPE_C);
@@ -260,7 +260,7 @@ static void mdfld_dbi_output_exit_dsr (struct mdfld_dsi_dbi_output * dbi_output,
        struct drm_crtc * crtc = dbi_output->base.base.crtc;
        struct psb_intel_crtc * psb_crtc = (crtc) ? to_psb_intel_crtc(crtc) : NULL; 
        u32 reg_val;
-       u32 dpll_reg = MRST_DPLL_A;
+       u32 dpll_reg = PSB_DSI_PLL_CTRL;
        u32 pipeconf_reg = PSB_PIPECONF(PSB_PIPE_A);
        u32 dspcntr_reg = PSB_DSPCNTR(PSB_PIPE_A);
 
@@ -270,7 +270,7 @@ static void mdfld_dbi_output_exit_dsr (struct mdfld_dsi_dbi_output * dbi_output,
                return;
                
        if(pipe == 2) {
-               dpll_reg = MRST_DPLL_A;
+               dpll_reg = PSB_DSI_PLL_CTRL;
                pipeconf_reg = PSB_PIPECONF(PSB_PIPE_C);
                dspcntr_reg = PSB_DSPCNTR(PSB_PIPE_C);
        }
@@ -361,7 +361,7 @@ void mdfld_dsi_dbi_exit_dsr(struct drm_device *dev, u32 update_src)
 
 static bool mdfld_dbi_is_in_dsr(struct drm_device * dev)
 {
-       if(REG_READ(MRST_DPLL_A) & DPLL_VCO_ENABLE)
+       if (REG_READ(PSB_DSI_PLL_CTRL) & DPLL_VCO_ENABLE)
                return false;
        if ((REG_READ(PSB_PIPECONF(PSB_PIPE_A)) & PIPEACONF_ENABLE) ||
            (REG_READ(PSB_PIPECONF(PSB_PIPE_C)) & PIPEACONF_ENABLE))
index a95b590..5fa0bc6 100644 (file)
@@ -446,7 +446,7 @@ static int mdfld_dpu_update_fb(struct drm_device * dev) {
        struct mdfld_dbi_dpu_info * dpu_info = dev_priv->dbi_dpu_info;
        bool pipe_updated[2];
        unsigned long irq_flags;
-       u32 dpll_reg = MRST_DPLL_A;
+       u32 dpll_reg = PSB_DSI_PLL_CTRL;
        u32 dspcntr_reg = PSB_DSPCNTR(PSB_PIPE_A);
        u32 pipeconf_reg = PSB_PIPECONF(PSB_PIPE_A);
        u32 dsplinoff_reg = PSB_DSPLINOFF(PSB_PIPE_A);
@@ -520,7 +520,7 @@ static int __mdfld_dbi_exit_dsr(struct mdfld_dsi_dbi_output * dbi_output, int pi
        struct drm_crtc * crtc = dbi_output->base.base.crtc;
        struct psb_intel_crtc * psb_crtc = (crtc) ? to_psb_intel_crtc(crtc) : NULL; 
        u32 reg_val;
-       u32 dpll_reg = MRST_DPLL_A;
+       u32 dpll_reg = PSB_DSI_PLL_CTRL;
        u32 pipeconf_reg = PSB_PIPECONF(PSB_PIPE_A);
        u32 dspcntr_reg = PSB_DSPCNTR(PSB_PIPE_A);
        u32 dspbase_reg = PSB_DSPBASE(PSB_PIPE_A);
@@ -538,7 +538,7 @@ static int __mdfld_dbi_exit_dsr(struct mdfld_dsi_dbi_output * dbi_output, int pi
                return -EAGAIN;
                
        if(pipe == 2) {
-               dpll_reg = MRST_DPLL_A;
+               dpll_reg = PSB_DSI_PLL_CTRL;
                pipeconf_reg = PSB_PIPECONF(PSB_PIPE_C);
                dspcntr_reg = PSB_DSPCNTR(PSB_PIPE_C);
                dspbase_reg = MDFLD_DSPCBASE;
index 9250a8b..c52e970 100644 (file)
@@ -908,11 +908,11 @@ void mdfld_dsi_dpi_mode_set(struct drm_encoder * encoder,
                tc35876x_toshiba_bridge_panel_on(dev);
                udelay(100);
                /* Now start the DSI clock */
-               REG_WRITE(MRST_DPLL_A, 0x00);
-               REG_WRITE(MRST_FPA0, 0xC1);
-               REG_WRITE(MRST_DPLL_A, 0x00800000);
+               REG_WRITE(PSB_DSI_PLL_CTRL, 0x00);
+               REG_WRITE(PSB_DSI_PLL_DIV_M1, 0xC1);
+               REG_WRITE(PSB_DSI_PLL_CTRL, 0x00800000);
                udelay(500);
-               REG_WRITE(MRST_DPLL_A, 0x80800000);
+               REG_WRITE(PSB_DSI_PLL_CTRL, 0x80800000);
 
                if (REG_BIT_WAIT(pipeconf_reg, 1, 29))
                        dev_err(&dev->pdev->dev, "%s: DSI PLL lock timeout\n",
index 297ae22..e20ccf6 100644 (file)
@@ -804,14 +804,14 @@ int mdfld_dsi_pkg_sender_init(struct mdfld_dsi_connector * dsi_connector, int pi
        
        /*init regs*/
        if(pipe == 0) {
-               pkg_sender->dpll_reg = MRST_DPLL_A;
+               pkg_sender->dpll_reg = PSB_DSI_PLL_CTRL;
                pkg_sender->dspcntr_reg = PSB_DSPCNTR(PSB_PIPE_A);
                pkg_sender->pipeconf_reg = PSB_PIPECONF(PSB_PIPE_A);
                pkg_sender->dsplinoff_reg = PSB_DSPLINOFF(PSB_PIPE_A);
                pkg_sender->dspsurf_reg = PSB_DSPSURF(PSB_PIPE_A);
                pkg_sender->pipestat_reg = PSB_PIPESTAT(PSB_PIPE_A);
        } else if (pipe == 2) {
-               pkg_sender->dpll_reg = MRST_DPLL_A;
+               pkg_sender->dpll_reg = PSB_DSI_PLL_CTRL;
                pkg_sender->dspcntr_reg = PSB_DSPCNTR(PSB_PIPE_C);
                pkg_sender->pipeconf_reg = PSB_PIPECONF(PSB_PIPE_C);
                pkg_sender->dsplinoff_reg = PSB_DSPLINOFF(PSB_PIPE_C);
index 040896d..2ad83f4 100644 (file)
@@ -972,7 +972,7 @@ static int mdfld__intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
  */
 void mdfld_disable_crtc (struct drm_device *dev, int pipe)
 {
-       int dpll_reg = MRST_DPLL_A;
+       int dpll_reg = PSB_DSI_PLL_CTRL;
        int dspcntr_reg = PSB_DSPCNTR(PSB_PIPE_A);
        int dspbase_reg = PSB_DSPBASE(PSB_PIPE_A);
        int pipeconf_reg = PSB_PIPECONF(PSB_PIPE_A);
@@ -985,13 +985,13 @@ void mdfld_disable_crtc (struct drm_device *dev, int pipe)
        case 0:
                break;
        case 1:
-               dpll_reg = MDFLD_DPLL_B;
+               dpll_reg = PSB_DPLL_CTRL;
                dspcntr_reg = PSB_DSPCNTR(PSB_PIPE_B);
                dspbase_reg = PSB_DSPSURF(PSB_PIPE_B);
                pipeconf_reg = PSB_PIPECONF(PSB_PIPE_B);
                break;
        case 2:
-               dpll_reg = MRST_DPLL_A;
+               dpll_reg = PSB_DSI_PLL_CTRL;
                dspcntr_reg = PSB_DSPCNTR(PSB_PIPE_C);
                dspbase_reg = PSB_DSPBASE(PSB_PIPE_C);
                pipeconf_reg = PSB_PIPECONF(PSB_PIPE_C);
@@ -1066,7 +1066,7 @@ static void mdfld_crtc_dpms(struct drm_crtc *crtc, int mode)
        DRM_DRIVER_PRIVATE_T *dev_priv = dev->dev_private;
        struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
        int pipe = psb_intel_crtc->pipe;
-       int dpll_reg = MRST_DPLL_A;
+       int dpll_reg = PSB_DSI_PLL_CTRL;
        int dspcntr_reg = PSB_DSPCNTR(PSB_PIPE_A);
        int dspbase_reg = PSB_DSPBASE(PSB_PIPE_A);
        int pipeconf_reg = PSB_PIPECONF(PSB_PIPE_A);
@@ -1092,10 +1092,10 @@ static void mdfld_crtc_dpms(struct drm_crtc *crtc, int mode)
                pipeconf_reg = PSB_PIPECONF(PSB_PIPE_B);
                pipeconf = dev_priv->pipeconf1;
                dspcntr = dev_priv->dspcntr1;
-               dpll_reg = MDFLD_DPLL_B;
+               dpll_reg = PSB_DPLL_CTRL;
                break;
        case 2:
-               dpll_reg = MRST_DPLL_A;
+               dpll_reg = PSB_DSI_PLL_CTRL;
                dspcntr_reg = PSB_DSPCNTR(PSB_PIPE_C);
                dspbase_reg = PSB_DSPBASE(PSB_PIPE_C);
                pipeconf_reg = PSB_PIPECONF(PSB_PIPE_C);
@@ -1517,8 +1517,8 @@ static int mdfld_crtc_mode_set(struct drm_crtc *crtc,
        struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
        DRM_DRIVER_PRIVATE_T *dev_priv = dev->dev_private;
        int pipe = psb_intel_crtc->pipe;
-       int fp_reg = MRST_FPA0;
-       int dpll_reg = MRST_DPLL_A;
+       int fp_reg = PSB_DSI_PLL_DIV_M1;
+       int dpll_reg = PSB_DSI_PLL_CTRL;
        int dspcntr_reg = PSB_DSPCNTR(PSB_PIPE_A);
        int pipeconf_reg = PSB_PIPECONF(PSB_PIPE_A);
        int htot_reg = PSB_HTOTAL(PSB_PIPE_A);
@@ -1576,11 +1576,11 @@ static int mdfld_crtc_mode_set(struct drm_crtc *crtc,
                pipesrc_reg = PSB_PIPESRC(PSB_PIPE_B);
                pipeconf = &dev_priv->pipeconf1;
                dspcntr = &dev_priv->dspcntr1;
-               fp_reg = MDFLD_DPLL_DIV0;
-               dpll_reg = MDFLD_DPLL_B;
+               fp_reg = PSB_DPLL_DIV0;
+               dpll_reg = PSB_DPLL_CTRL;
                break;
        case 2:
-               dpll_reg = MRST_DPLL_A;
+               dpll_reg = PSB_DSI_PLL_CTRL;
                dspcntr_reg = PSB_DSPCNTR(PSB_PIPE_C);
                pipeconf_reg = PSB_PIPECONF(PSB_PIPE_C);
                htot_reg = PSB_HTOTAL(PSB_PIPE_C);
index caf3555..7357215 100644 (file)
@@ -677,18 +677,16 @@ struct dpst_guardband {
 /*
  * MOORESTOWN delta registers
  */
-#define MRST_DPLL_A            0x0f014
-#define MDFLD_DPLL_B           0x0f018
+#define PSB_DSI_PLL_CTRL       0x0f014
+#define PSB_DPLL_CTRL          0x0f018
 #define MDFLD_INPUT_REF_SEL    (1 << 14) 
 #define MDFLD_VCO_SEL          (1 << 16) 
 #define DPLLA_MODE_LVDS                (2 << 26)       /* mrst */
 #define MDFLD_PLL_LATCHEN      (1 << 28) 
 #define MDFLD_PWR_GATE_EN      (1 << 30) 
 #define MDFLD_P1_MASK          (0x1FF << 17) 
-#define MRST_FPA0              0x0f040
-#define MRST_FPA1              0x0f044
-#define MDFLD_DPLL_DIV0                0x0f048
-#define MDFLD_DPLL_DIV1                0x0f04c
+#define PSB_DSI_PLL_DIV_M1     0x0f040
+#define PSB_DPLL_DIV0          0x0f048
 #define MRST_PERF_MODE         0x020f4
 
 /* MEDFIELD HDMI registers */
index b966b8e..839bef7 100644 (file)
@@ -483,14 +483,13 @@ static int mdfld_save_display_registers(struct drm_device *dev, int pipe)
 
        switch (pipe) {
        case 0:
-               pr->pll_ctrl = PSB_RVDC32(MRST_DPLL_A);
-               pr->pll_div = PSB_RVDC32(MRST_FPA0);
+               pr->pll_ctrl = PSB_RVDC32(PSB_DSI_PLL_CTRL);
+               pr->pll_div = PSB_RVDC32(PSB_DSI_PLL_DIV_M1);
                pr->mipi_ctrl = PSB_RVDC32(MIPI_PORT_CONTROL(pipe));
                break;
        case 1:
-               pr->pll_ctrl = PSB_RVDC32(MDFLD_DPLL_B);
-               pr->pll_div = PSB_RVDC32(MDFLD_DPLL_DIV0);
-
+               pr->pll_ctrl = PSB_RVDC32(PSB_DPLL_CTRL);
+               pr->pll_div = PSB_RVDC32(PSB_DPLL_DIV0);
                dev_priv->savePFIT_CONTROL = PSB_RVDC32(PFIT_CONTROL);
                dev_priv->savePFIT_PGM_RATIOS = PSB_RVDC32(PFIT_PGM_RATIOS);
                dev_priv->saveHDMIPHYMISCCTL = PSB_RVDC32(HDMIPHYMISCCTL);
@@ -584,13 +583,13 @@ static int mdfld_restore_display_registers(struct drm_device *dev, int pipe)
 
        switch (pipe) {
        case 0:
-               dpll_reg = MRST_DPLL_A;
-               pll_div_reg = MRST_FPA0;
+               dpll_reg = PSB_DSI_PLL_CTRL;
+               pll_div_reg = PSB_DSI_PLL_DIV_M1;
                dsi_config = dev_priv->dsi_configs[0];
                break;
        case 1:
-               dpll_reg = MDFLD_DPLL_B;
-               pll_div_reg = MDFLD_DPLL_DIV0;
+               dpll_reg = PSB_DPLL_CTRL;
+               pll_div_reg = PSB_DPLL_DIV0;
                break;
        case 2:
                dsi_output = dev_priv->dbi_output2;
index 6f7c2ce..aa6347d 100644 (file)
@@ -412,7 +412,7 @@ static void mdfld_dsi_dbi_update_fb (struct mdfld_dsi_dbi_output * dbi_output, i
        struct drm_crtc * crtc = dbi_output->base.base.crtc;
        struct psb_intel_crtc * psb_crtc = (crtc) ? to_psb_intel_crtc(crtc) : NULL; 
 
-       u32 dpll_reg = MRST_DPLL_A;
+       u32 dpll_reg = PSB_DSI_PLL_CTRL;
        u32 dspcntr_reg = PSB_DSPCNTR(PSB_PIPE_A);
        u32 pipeconf_reg = PSB_PIPECONF(PSB_PIPE_A);
        u32 dsplinoff_reg = PSB_DSPLINOFF(PSB_PIPE_A);