arm: dts: exynos5422: change BPLL clock to 933MHz

This patch changes BPLL clock to 933MHz for DREX controller
can use maximum speed.

Change-Id: Ia06079c32ad532cb8a53d9dcae6a7fbacf80895a
Signed-off-by: Inki Dae <inki.dae@samsung.com>

diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
index 652274e..824d608 100644 (file)
--- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
+++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
@@ -122,6 +122,11 @@
        status = "okay";
 };
 
+&clock {
+       assigned-clocks = <&clock CLK_FOUT_BPLL>;
+       assigned-clock-rates = <933000000>;
+};
+
 &cpu0 {
        cpu-supply = <&buck6_reg>;
 };