KVM: PPC: Book3S HV: Access XICS in BE

On the exit path from the guest we check what type of interrupt we received
if we received one. This means we're doing hardware access to the XICS interrupt
controller.

However, when running on a little endian system, this access is byte reversed.

So let's make sure to swizzle the bytes back again and virtually make XICS
accesses big endian.

Signed-off-by: Alexander Graf <agraf@suse.de>

diff --git a/arch/powerpc/kvm/book3s_hv_rmhandlers.S b/arch/powerpc/kvm/book3s_hv_rmhandlers.S
index bf5270e..364ca0c 100644 (file)
--- a/arch/powerpc/kvm/book3s_hv_rmhandlers.S
+++ b/arch/powerpc/kvm/book3s_hv_rmhandlers.S
@@ -2350,7 +2350,18 @@ kvmppc_read_intr:
        cmpdi   r6, 0
        beq-    1f
        lwzcix  r0, r6, r7
-       rlwinm. r3, r0, 0, 0xffffff
+       /*
+        * Save XIRR for later. Since we get in in reverse endian on LE
+        * systems, save it byte reversed and fetch it back in host endian.
+        */
+       li      r3, HSTATE_SAVED_XIRR
+       STWX_BE r0, r3, r13
+#ifdef __LITTLE_ENDIAN__
+       lwz     r3, HSTATE_SAVED_XIRR(r13)
+#else
+       mr      r3, r0
+#endif
+       rlwinm. r3, r3, 0, 0xffffff
        sync
        beq     1f                      /* if nothing pending in the ICP */
 
@@ -2382,10 +2393,9 @@ kvmppc_read_intr:
        li      r3, -1
 1:     blr
 
-42:    /* It's not an IPI and it's for the host, stash it in the PACA
-        * before exit, it will be picked up by the host ICP driver
+42:    /* It's not an IPI and it's for the host. We saved a copy of XIRR in
+        * the PACA earlier, it will be picked up by the host ICP driver
         */
-       stw     r0, HSTATE_SAVED_XIRR(r13)
        li      r3, 1
        b       1b