bool "Support flea3"
select CPU_ARM1136
-config TARGET_MX35PDK
- bool "Support mx35pdk"
- select BOARD_LATE_INIT
- select CPU_ARM1136
-
config ARCH_BCM283X
bool "Broadcom BCM283X family"
select DM
development platform that supports the QorIQ LS2080A
Layerscape Architecture processor.
-config TARGET_LS2080A_SIMU
- bool "Support ls2080a_simu"
- select ARCH_LS2080A
- select ARM64
- select ARMV8_MULTIENTRY
- select BOARD_LATE_INIT
- help
- Support for Freescale LS2080A_SIMU platform.
- The LS2080A Development System (QDS) is a pre silicon
- development platform that supports the QorIQ LS2080A
- Layerscape Architecture processor.
-
config TARGET_LS1088AQDS
bool "Support ls1088aqds"
select ARCH_LS1088A
source "board/cirrus/edb93xx/Kconfig"
source "board/eets/pdu001/Kconfig"
source "board/emulation/qemu-arm/Kconfig"
-source "board/freescale/ls2080a/Kconfig"
source "board/freescale/ls2080aqds/Kconfig"
source "board/freescale/ls2080ardb/Kconfig"
source "board/freescale/ls1088a/Kconfig"
source "board/freescale/ls1012ardb/Kconfig"
source "board/freescale/ls1012afrdm/Kconfig"
source "board/freescale/lx2160a/Kconfig"
-source "board/freescale/mx35pdk/Kconfig"
source "board/freescale/s32v234evb/Kconfig"
source "board/grinn/chiliboard/Kconfig"
source "board/hisilicon/hikey/Kconfig"
default y
select ARM_SMCCC if OF_CONTROL
depends on !ARCH_EXYNOS7 && !ARCH_BCM283X && \
- !TARGET_LS2080A_SIMU && !TARGET_LS2080AQDS && \
+ !TARGET_LS2080AQDS && \
!TARGET_LS2080ARDB && !TARGET_LS2080A_EMU && \
!TARGET_LS1088ARDB && !TARGET_LS1088AQDS && \
!TARGET_LS1012ARDB && !TARGET_LS1012AFRDM && \
kirkwood-atl-sbx81lifxcat.dtb \
kirkwood-blackarmor-nas220.dtb \
kirkwood-d2net.dtb \
- kirkwood-db-88f6281.dtb \
- kirkwood-db-88f6281-spi.dtb \
kirkwood-dns325.dtb \
kirkwood-dockstar.dtb \
kirkwood-dreamplug.dtb \
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Marvell DB-88F6281-BP Development Board Setup
- *
- * Saeed Bishara <saeed@marvell.com>
- * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
- *
- */
-
-/dts-v1/;
-
-#include "kirkwood-db-88f6281.dts"
-
-/ {
- aliases {
- spi0 = &spi0;
- };
-};
-
-&spi0 {
- status = "okay";
-
- flash@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "st,m25p128", "jedec,spi-nor", "spi-flash";
- reg = <0>;
- spi-max-frequency = <50000000>;
- mode = <0>;
-
- partition@u-boot {
- reg = <0x00000000 0x00c00000>;
- label = "u-boot";
- };
- partition@u-boot-env {
- reg = <0x00c00000 0x00040000>;
- label = "u-boot-env";
- };
- partition@unused {
- reg = <0x00100000 0x00f00000>;
- label = "unused";
- };
- };
-};
-
-&nand {
- status = "disabled";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Marvell DB-88F6281-BP Development Board Setup
- *
- * Saeed Bishara <saeed@marvell.com>
- * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
- *
- */
-
-/dts-v1/;
-
-#include "kirkwood-db.dtsi"
-#include "kirkwood-6281.dtsi"
-
-/ {
- model = "Marvell DB-88F6281-BP Development Board";
- compatible = "marvell,db-88f6281-bp", "marvell,kirkwood-88f6281", "marvell,kirkwood";
-};
-
-&pciec {
- status = "okay";
-};
-
-&pcie0 {
- status = "okay";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Marvell DB-{88F6281,88F6282}-BP Development Board Setup
- *
- * Saeed Bishara <saeed@marvell.com>
- * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
- *
- * This file contains the definitions that are common between the 6281
- * and 6282 variants of the Marvell Kirkwood Development Board.
- */
-
-#include "kirkwood.dtsi"
-
-/ {
- memory {
- device_type = "memory";
- reg = <0x00000000 0x20000000>; /* 512 MB */
- };
-
- chosen {
- bootargs = "console=ttyS0,115200n8 earlyprintk";
- stdout-path = &uart0;
- };
-
- aliases {
- ethernet0 = ð0;
- spi0 = &spi0;
- };
-
- ocp@f1000000 {
- pin-controller@10000 {
- pmx_sdio_gpios: pmx-sdio-gpios {
- marvell,pins = "mpp37", "mpp38";
- marvell,function = "gpio";
- };
- };
-
- serial@12000 {
- status = "okay";
- };
-
- sata@80000 {
- nr-ports = <2>;
- status = "okay";
- };
-
- ehci@50000 {
- status = "okay";
- };
-
- mvsdio@90000 {
- pinctrl-0 = <&pmx_sdio_gpios>;
- pinctrl-names = "default";
- wp-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
- cd-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
- status = "okay";
- };
- };
-};
-
-&nand {
- chip-delay = <25>;
- status = "okay";
-
- partition@0 {
- label = "uboot";
- reg = <0x0 0x100000>;
- };
-
- partition@100000 {
- label = "uImage";
- reg = <0x100000 0x400000>;
- };
-
- partition@500000 {
- label = "root";
- reg = <0x500000 0x1fb00000>;
- };
-};
-
-&mdio {
- status = "okay";
-
- ethphy0: ethernet-phy@8 {
- reg = <8>;
- };
-};
-
-ð0 {
- status = "okay";
- ethernet0-port@0 {
- phy-handle = <ðphy0>;
- };
-};
prompt "MX28 board select"
optional
-config TARGET_APX4DEVKIT
- bool "Support apx4devkit"
-
config TARGET_BG0900
bool "Support bg0900"
config SYS_SOC
default "mxs"
-source "board/bluegiga/apx4devkit/Kconfig"
source "board/freescale/mx28evk/Kconfig"
source "board/liebherr/xea/Kconfig"
source "board/ppcag/bg0900/Kconfig"
config TARGET_SBx81LIFXCAT
bool "Allied Telesis SBx81GP24/SBx81GT24"
-config TARGET_DB_88F6281_BP
- bool "Marvell DB-88F6281-BP"
-
endchoice
config SYS_SOC
source "board/zyxel/nsa310s/Kconfig"
source "board/alliedtelesis/SBx81LIFKW/Kconfig"
source "board/alliedtelesis/SBx81LIFXCAT/Kconfig"
-source "board/Marvell/db-88f6281-bp/Kconfig"
endif
bool "Support MPC8541CDS"
select ARCH_MPC8541
-config TARGET_MPC8544DS
- bool "Support MPC8544DS"
- select ARCH_MPC8544
- imply PANIC_HANG
-
config TARGET_MPC8548CDS
bool "Support MPC8548CDS"
select ARCH_MPC8548
bool "Support MPC8569MDS"
select ARCH_MPC8569
-config TARGET_MPC8572DS
- bool "Support MPC8572DS"
- select ARCH_MPC8572
-# Use DDR3 controller with DDR2 DIMMs on this board
- select SYS_FSL_DDRC_GEN3
- imply SCSI
- imply PANIC_HANG
-
config TARGET_P1010RDB_PA
bool "Support P1010RDB_PA"
select ARCH_P1010
source "board/freescale/corenet_ds/Kconfig"
source "board/freescale/mpc8541cds/Kconfig"
-source "board/freescale/mpc8544ds/Kconfig"
source "board/freescale/mpc8548cds/Kconfig"
source "board/freescale/mpc8555cds/Kconfig"
source "board/freescale/mpc8568mds/Kconfig"
source "board/freescale/mpc8569mds/Kconfig"
-source "board/freescale/mpc8572ds/Kconfig"
source "board/freescale/p1010rdb/Kconfig"
source "board/freescale/p1_p2_rdb_pc/Kconfig"
source "board/freescale/p2041rdb/Kconfig"
select ARCH_MPC8641
select BOARD_EARLY_INIT_F
-config TARGET_MPC8610HPCD
- bool "Support MPC8610HPCD"
- select ARCH_MPC8610
- select BOARD_EARLY_INIT_F
-
-config TARGET_MPC8641HPCN
- bool "Support MPC8641HPCN"
- select ARCH_MPC8641
- select FSL_DDR_INTERACTIVE
- imply SCSI
-
config TARGET_XPEDITE517X
bool "Support xpedite517x"
select ARCH_MPC8641
Number of local access windows. This is fixed per SoC.
If not sure, do not change.
-source "board/freescale/mpc8610hpcd/Kconfig"
-source "board/freescale/mpc8641hpcn/Kconfig"
source "board/sbc8641d/Kconfig"
source "board/xes/xpedite517x/Kconfig"
config CPU_SH4
bool
-config CPU_SH4A
- bool
- select CPU_SH4
-
-config SH_32BIT
- bool "32bit mode"
- depends on CPU_SH4A
- default n
- help
- SH4A has 2 physical memory maps. This use 32bit mode.
- And this is board specific. Please check your board if you
- want to use this.
-
choice
prompt "Target select"
optional
-config TARGET_MIGOR
- bool "Migo-R"
- select CPU_SH4
-
config TARGET_R2DPLUS
bool "Renesas R2D-PLUS"
select CPU_SH4
-config TARGET_R7780MP
- bool "R7780MP board"
- select CPU_SH4A
-
-config TARGET_SH7752EVB
- bool "SH7752EVB"
- select CPU_SH4A
-
-config TARGET_SH7753EVB
- bool "SH7753EVB"
- select CPU_SH4
-
-config TARGET_SH7757LCR
- bool "SH7757LCR"
- select CPU_SH4A
-
-config TARGET_SH7763RDP
- bool "SH7763RDP"
- select CPU_SH4
-
endchoice
config SYS_ARCH
source "arch/sh/lib/Kconfig"
-source "board/renesas/MigoR/Kconfig"
source "board/renesas/r2dplus/Kconfig"
-source "board/renesas/r7780mp/Kconfig"
-source "board/renesas/sh7752evb/Kconfig"
-source "board/renesas/sh7753evb/Kconfig"
-source "board/renesas/sh7757lcr/Kconfig"
-source "board/renesas/sh7763rdp/Kconfig"
endmenu
# error "Unknown SH4 variant"
#endif
-#if defined(CONFIG_SH_32BIT)
-#define PMB_ADDR_ARRAY 0xf6100000
-#define PMB_ADDR_ENTRY 8
-#define PMB_VPN 24
-
-#define PMB_DATA_ARRAY 0xf7100000
-#define PMB_DATA_ENTRY 8
-#define PMB_PPN 24
-#define PMB_UB 9 /* Buffered write */
-#define PMB_V 8 /* Valid */
-#define PMB_SZ1 7 /* Page size (upper bit) */
-#define PMB_SZ0 4 /* Page size (lower bit) */
-#define PMB_C 3 /* Cacheability */
-#define PMB_WT 0 /* Write-through */
-
-#define PMB_ADDR_BASE(entry) (PMB_ADDR_ARRAY + (entry << PMB_ADDR_ENTRY))
-#define PMB_DATA_BASE(entry) (PMB_DATA_ARRAY + (entry << PMB_DATA_ENTRY))
-#define mk_pmb_addr_val(vpn) ((vpn << PMB_VPN))
-#define mk_pmb_data_val(ppn, ub, v, sz1, sz0, c, wt) \
- ((ppn << PMB_PPN) | (ub << PMB_UB) | \
- (v << PMB_V) | (sz1 << PMB_SZ1) | \
- (sz0 << PMB_SZ0) | (c << PMB_C) | \
- (wt << PMB_WT))
-#endif
-
#endif /* _ASM_CPU_SH4_H_ */
{
}
-#ifdef CONFIG_CPU_SH4A
-#define __icbi() \
-{ \
- unsigned long __addr; \
- __addr = 0xa8000000; \
- __asm__ __volatile__( \
- "icbi %0\n\t" \
- : /* no output */ \
- : "m" (__m(__addr))); \
-}
-#endif
-
static inline unsigned long tas(volatile int *m)
{
unsigned long retval;
* effect. On newer cores (like the sh4a and sh5) this is accomplished
* with icbi.
*
- * Also note that on sh4a in the icbi case we can forego a synco for the
- * write barrier, as it's not necessary for control registers.
- *
* Historically we have only done this type of barrier for the MMUCR, but
* it's also necessary for the CCR, so we make it generic here instead.
*/
-#ifdef CONFIG_CPU_SH4A
-#define mb() __asm__ __volatile__ ("synco": : :"memory")
-#define rmb() mb()
-#define wmb() __asm__ __volatile__ ("synco": : :"memory")
-#define ctrl_barrier() __icbi()
-#define read_barrier_depends() do { } while(0)
-#else
#define mb() __asm__ __volatile__ ("": : :"memory")
#define rmb() mb()
#define wmb() __asm__ __volatile__ ("": : :"memory")
#define ctrl_barrier() __asm__ __volatile__ ("nop;nop;nop;nop;nop;nop;nop;nop")
#define read_barrier_depends() do { } while(0)
-#endif
#ifdef CONFIG_SMP
#define smp_mb() mb()
+++ /dev/null
-#ifndef __ASM_SH_UNALIGNED_SH4A_H
-#define __ASM_SH_UNALIGNED_SH4A_H
-
-/*
- * SH-4A has support for unaligned 32-bit loads, and 32-bit loads only.
- * Support for 64-bit accesses are done through shifting and masking
- * relative to the endianness. Unaligned stores are not supported by the
- * instruction encoding, so these continue to use the packed
- * struct.
- *
- * The same note as with the movli.l/movco.l pair applies here, as long
- * as the load is gauranteed to be inlined, nothing else will hook in to
- * r0 and we get the return value for free.
- *
- * NOTE: Due to the fact we require r0 encoding, care should be taken to
- * avoid mixing these heavily with other r0 consumers, such as the atomic
- * ops. Failure to adhere to this can result in the compiler running out
- * of spill registers and blowing up when building at low optimization
- * levels. See http://gcc.gnu.org/bugzilla/show_bug.cgi?id=34777.
- */
-#include <linux/types.h>
-#include <asm/byteorder.h>
-
-static __always_inline u32 __get_unaligned_cpu32(const u8 *p)
-{
- unsigned long unaligned;
-
- __asm__ __volatile__ (
- "movua.l @%1, %0\n\t"
- : "=z" (unaligned)
- : "r" (p)
- );
-
- return unaligned;
-}
-
-struct __una_u16 { u16 x __attribute__((packed)); };
-struct __una_u32 { u32 x __attribute__((packed)); };
-struct __una_u64 { u64 x __attribute__((packed)); };
-
-static inline u16 __get_unaligned_cpu16(const u8 *p)
-{
-#ifdef __LITTLE_ENDIAN
- return p[0] | p[1] << 8;
-#else
- return p[0] << 8 | p[1];
-#endif
-}
-
-/*
- * Even though movua.l supports auto-increment on the read side, it can
- * only store to r0 due to instruction encoding constraints, so just let
- * the compiler sort it out on its own.
- */
-static inline u64 __get_unaligned_cpu64(const u8 *p)
-{
-#ifdef __LITTLE_ENDIAN
- return (u64)__get_unaligned_cpu32(p + 4) << 32 |
- __get_unaligned_cpu32(p);
-#else
- return (u64)__get_unaligned_cpu32(p) << 32 |
- __get_unaligned_cpu32(p + 4);
-#endif
-}
-
-static inline u16 get_unaligned_le16(const void *p)
-{
- return le16_to_cpu(__get_unaligned_cpu16(p));
-}
-
-static inline u32 get_unaligned_le32(const void *p)
-{
- return le32_to_cpu(__get_unaligned_cpu32(p));
-}
-
-static inline u64 get_unaligned_le64(const void *p)
-{
- return le64_to_cpu(__get_unaligned_cpu64(p));
-}
-
-static inline u16 get_unaligned_be16(const void *p)
-{
- return be16_to_cpu(__get_unaligned_cpu16(p));
-}
-
-static inline u32 get_unaligned_be32(const void *p)
-{
- return be32_to_cpu(__get_unaligned_cpu32(p));
-}
-
-static inline u64 get_unaligned_be64(const void *p)
-{
- return be64_to_cpu(__get_unaligned_cpu64(p));
-}
-
-static inline void __put_le16_noalign(u8 *p, u16 val)
-{
- *p++ = val;
- *p++ = val >> 8;
-}
-
-static inline void __put_le32_noalign(u8 *p, u32 val)
-{
- __put_le16_noalign(p, val);
- __put_le16_noalign(p + 2, val >> 16);
-}
-
-static inline void __put_le64_noalign(u8 *p, u64 val)
-{
- __put_le32_noalign(p, val);
- __put_le32_noalign(p + 4, val >> 32);
-}
-
-static inline void __put_be16_noalign(u8 *p, u16 val)
-{
- *p++ = val >> 8;
- *p++ = val;
-}
-
-static inline void __put_be32_noalign(u8 *p, u32 val)
-{
- __put_be16_noalign(p, val >> 16);
- __put_be16_noalign(p + 2, val);
-}
-
-static inline void __put_be64_noalign(u8 *p, u64 val)
-{
- __put_be32_noalign(p, val >> 32);
- __put_be32_noalign(p + 4, val);
-}
-
-static inline void put_unaligned_le16(u16 val, void *p)
-{
-#ifdef __LITTLE_ENDIAN
- ((struct __una_u16 *)p)->x = val;
-#else
- __put_le16_noalign(p, val);
-#endif
-}
-
-static inline void put_unaligned_le32(u32 val, void *p)
-{
-#ifdef __LITTLE_ENDIAN
- ((struct __una_u32 *)p)->x = val;
-#else
- __put_le32_noalign(p, val);
-#endif
-}
-
-static inline void put_unaligned_le64(u64 val, void *p)
-{
-#ifdef __LITTLE_ENDIAN
- ((struct __una_u64 *)p)->x = val;
-#else
- __put_le64_noalign(p, val);
-#endif
-}
-
-static inline void put_unaligned_be16(u16 val, void *p)
-{
-#ifdef __BIG_ENDIAN
- ((struct __una_u16 *)p)->x = val;
-#else
- __put_be16_noalign(p, val);
-#endif
-}
-
-static inline void put_unaligned_be32(u32 val, void *p)
-{
-#ifdef __BIG_ENDIAN
- ((struct __una_u32 *)p)->x = val;
-#else
- __put_be32_noalign(p, val);
-#endif
-}
-
-static inline void put_unaligned_be64(u64 val, void *p)
-{
-#ifdef __BIG_ENDIAN
- ((struct __una_u64 *)p)->x = val;
-#else
- __put_be64_noalign(p, val);
-#endif
-}
-
-/*
- * Cause a link-time error if we try an unaligned access other than
- * 1,2,4 or 8 bytes long
- */
-extern void __bad_unaligned_access_size(void);
-
-#define __get_unaligned_le(ptr) ((__force typeof(*(ptr)))({ \
- __builtin_choose_expr(sizeof(*(ptr)) == 1, *(ptr), \
- __builtin_choose_expr(sizeof(*(ptr)) == 2, get_unaligned_le16((ptr)), \
- __builtin_choose_expr(sizeof(*(ptr)) == 4, get_unaligned_le32((ptr)), \
- __builtin_choose_expr(sizeof(*(ptr)) == 8, get_unaligned_le64((ptr)), \
- __bad_unaligned_access_size())))); \
- }))
-
-#define __get_unaligned_be(ptr) ((__force typeof(*(ptr)))({ \
- __builtin_choose_expr(sizeof(*(ptr)) == 1, *(ptr), \
- __builtin_choose_expr(sizeof(*(ptr)) == 2, get_unaligned_be16((ptr)), \
- __builtin_choose_expr(sizeof(*(ptr)) == 4, get_unaligned_be32((ptr)), \
- __builtin_choose_expr(sizeof(*(ptr)) == 8, get_unaligned_be64((ptr)), \
- __bad_unaligned_access_size())))); \
- }))
-
-#define __put_unaligned_le(val, ptr) ({ \
- void *__gu_p = (ptr); \
- switch (sizeof(*(ptr))) { \
- case 1: \
- *(u8 *)__gu_p = (__force u8)(val); \
- break; \
- case 2: \
- put_unaligned_le16((__force u16)(val), __gu_p); \
- break; \
- case 4: \
- put_unaligned_le32((__force u32)(val), __gu_p); \
- break; \
- case 8: \
- put_unaligned_le64((__force u64)(val), __gu_p); \
- break; \
- default: \
- __bad_unaligned_access_size(); \
- break; \
- } \
- (void)0; })
-
-#define __put_unaligned_be(val, ptr) ({ \
- void *__gu_p = (ptr); \
- switch (sizeof(*(ptr))) { \
- case 1: \
- *(u8 *)__gu_p = (__force u8)(val); \
- break; \
- case 2: \
- put_unaligned_be16((__force u16)(val), __gu_p); \
- break; \
- case 4: \
- put_unaligned_be32((__force u32)(val), __gu_p); \
- break; \
- case 8: \
- put_unaligned_be64((__force u64)(val), __gu_p); \
- break; \
- default: \
- __bad_unaligned_access_size(); \
- break; \
- } \
- (void)0; })
-
-#ifdef __LITTLE_ENDIAN
-# define get_unaligned __get_unaligned_le
-# define put_unaligned __put_unaligned_le
-#else
-# define get_unaligned __get_unaligned_be
-# define put_unaligned __put_unaligned_be
-#endif
-
-#endif /* __ASM_SH_UNALIGNED_SH4A_H */
/* Copy from linux-kernel. */
-#ifdef CONFIG_CPU_SH4A
-/* SH-4A can handle unaligned loads in a relatively neutered fashion. */
-#include <asm/unaligned-sh4a.h>
-#else
-/* Otherwise, SH can't handle unaligned accesses. */
+/* Other than SH4A, SH can't handle unaligned accesses. */
#include <linux/compiler.h>
#if defined(__BIG_ENDIAN__)
#define get_unaligned __get_unaligned_be
#include <linux/unaligned/le_byteshift.h>
#include <linux/unaligned/be_byteshift.h>
#include <linux/unaligned/generic.h>
-#endif
#endif /* _ASM_SH_UNALIGNED_H */
+++ /dev/null
-kwbimage.cfg
+++ /dev/null
-if TARGET_DB_88F6281_BP
-
-config SYS_BOARD
- default "db-88f6281-bp"
-
-config SYS_VENDOR
- default "Marvell"
-
-config SYS_CONFIG_NAME
- default "db-88f6281-bp"
-
-endif
+++ /dev/null
-DB_88F6820_AMC BOARD
-M: Chris Packham <judge.packham@gmail.com>
-S: Maintained
-F: arch/arm/dts/kirkwood-db-88f6281.dts
-F: arch/arm/dts/kirkwood-db-88f6281-spi.dts
-F: arch/arm/dts/kirkwood-db.dtsi
-F: board/Marvell/db-88f6281-bp/
-F: include/configs/db-88f6281-bp.h
-F: configs/db-88f6281-bp-nand_defconfig
-F: configs/db-88f6281-bp-spi_defconfig
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0+
-
-obj-y := db-88f6281-bp.o
-extra-y := kwbimage.cfg
-
-quiet_cmd_sed = SED $@
- cmd_sed = sed $(SEDFLAGS_$(@F)) $< >$(dir $@)$(@F)
-
-SEDFLAGS_kwbimage.cfg = -e "s/^\#@BOOT_FROM.*/BOOT_FROM $(if $(CONFIG_CMD_NAND),nand,spi)/"
-$(obj)/kwbimage.cfg: $(src)/kwbimage.cfg.in include/autoconf.mk \
- include/config/auto.conf
- $(call if_changed,sed)
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-
-#include <common.h>
-#include <init.h>
-#include <net.h>
-#include <linux/bitops.h>
-#include <linux/io.h>
-#include <miiphy.h>
-#include <netdev.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/soc.h>
-#include <asm/arch/mpp.h>
-#include <asm/arch/gpio.h>
-
-#define DB_88F6281_OE_LOW ~(BIT(7))
-#define DB_88F6281_OE_HIGH ~(BIT(15) | BIT(14) | BIT(13) | BIT(4))
-#define DB_88F6281_OE_VAL_LOW BIT(7)
-#define DB_88F6281_OE_VAL_HIGH 0
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_early_init_f(void)
-{
- mvebu_config_gpio(DB_88F6281_OE_VAL_LOW,
- DB_88F6281_OE_VAL_HIGH,
- DB_88F6281_OE_LOW, DB_88F6281_OE_HIGH);
-
- /* Multi-Purpose Pins Functionality configuration */
- static const u32 kwmpp_config[] = {
-#ifdef CONFIG_CMD_NAND
- MPP0_NF_IO2,
- MPP1_NF_IO3,
- MPP2_NF_IO4,
- MPP3_NF_IO5,
-#else
- MPP0_SPI_SCn,
- MPP1_SPI_MOSI,
- MPP2_SPI_SCK,
- MPP3_SPI_MISO,
-#endif
- MPP4_NF_IO6,
- MPP5_NF_IO7,
- MPP6_SYSRST_OUTn,
- MPP7_GPO,
- MPP8_TW_SDA,
- MPP9_TW_SCK,
- MPP10_UART0_TXD,
- MPP11_UART0_RXD,
- MPP12_SD_CLK,
- MPP13_SD_CMD,
- MPP14_SD_D0,
- MPP15_SD_D1,
- MPP16_SD_D2,
- MPP17_SD_D3,
- MPP18_NF_IO0,
- MPP19_NF_IO1,
- MPP20_SATA1_ACTn,
- MPP21_SATA0_ACTn,
- MPP22_GPIO,
- MPP23_GPIO,
- MPP24_GPIO,
- MPP25_GPIO,
- MPP26_GPIO,
- MPP27_GPIO,
- MPP28_GPIO,
- MPP29_GPIO,
- MPP30_GPIO,
- MPP31_GPIO,
- MPP32_GPIO,
- MPP33_GPIO,
- MPP34_GPIO,
- MPP35_GPIO,
- MPP36_GPIO,
- MPP37_GPIO,
- MPP38_GPIO,
- MPP39_GPIO,
- MPP40_GPIO,
- MPP41_GPIO,
- MPP42_GPIO,
- MPP43_GPIO,
- MPP44_GPIO,
- MPP45_GPIO,
- MPP46_GPIO,
- MPP47_GPIO,
- MPP48_GPIO,
- MPP49_GPIO,
- 0
- };
- kirkwood_mpp_conf(kwmpp_config, NULL);
-
- return 0;
-}
-
-int board_init(void)
-{
- gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
-
- return 0;
-}
-
-#ifdef CONFIG_RESET_PHY_R
-/* automatically defined by kirkwood config.h */
-void reset_phy(void)
-{
-}
-#endif
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0+
-
-# Boot Media configurations
-#@BOOT_FROM
-
-DATA 0xd00100e0 0x1b1b1b9b
-DATA 0xd0020134 0xbbbbbbbb
-DATA 0xd0020138 0x00bbbbbb
-DATA 0xd0020154 0x00000200
-DATA 0xd002014c 0x00001c00
-DATA 0xd0020148 0x00000001
-
-DATA 0xd0001400 0x43000c30
-DATA 0xd0001404 0x39543000
-DATA 0xd0001408 0x22125451
-DATA 0xd000140c 0x00000833
-DATA 0xd0001410 0x000000cc
-DATA 0xd0001414 0x00000000
-DATA 0xd0001418 0x00000000
-DATA 0xd000141c 0x00000c52
-DATA 0xd0001420 0x00000044
-DATA 0xd0001424 0x0000f1ff
-DATA 0xd0001428 0x00085520
-DATA 0xd000147c 0x00008552
-DATA 0xd0001504 0x0ffffff1
-DATA 0xd0001508 0x10000000
-DATA 0xd000150c 0x0ffffff5
-DATA 0xd0001514 0x00000000
-DATA 0xd000151c 0x00000000
-DATA 0xd0001494 0x84210000
-DATA 0xd0001498 0x00000000
-DATA 0xd000149c 0x0000f40f
-DATA 0xd0001480 0x00000001
-
-# End of Header extension
-DATA 0x0 0x0
+++ /dev/null
-if TARGET_APX4DEVKIT
-
-config SYS_BOARD
- default "apx4devkit"
-
-config SYS_VENDOR
- default "bluegiga"
-
-config SYS_SOC
- default "mxs"
-
-config SYS_CONFIG_NAME
- default "apx4devkit"
-
-endif
+++ /dev/null
-APX4DEVKIT BOARD
-M: Lauri Hintsala <lauri.hintsala@bluegiga.com>
-S: Maintained
-F: board/bluegiga/apx4devkit/
-F: include/configs/apx4devkit.h
-F: configs/apx4devkit_defconfig
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-
-ifndef CONFIG_SPL_BUILD
-obj-y := apx4devkit.o
-else
-obj-y := spl_boot.o
-endif
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Bluegiga APX4 Development Kit
- *
- * Copyright (C) 2012 Bluegiga Technologies Oy
- *
- * Authors:
- * Veli-Pekka Peltola <veli-pekka.peltola@bluegiga.com>
- * Lauri Hintsala <lauri.hintsala@bluegiga.com>
- *
- * Based on m28evk.c:
- * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
- * on behalf of DENX Software Engineering GmbH
- */
-
-#include <common.h>
-#include <init.h>
-#include <net.h>
-#include <asm/gpio.h>
-#include <asm/io.h>
-#include <asm/setup.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/iomux-mx28.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/sys_proto.h>
-#include <env.h>
-#include <linux/mii.h>
-#include <miiphy.h>
-#include <netdev.h>
-#include <errno.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* Functions */
-int board_early_init_f(void)
-{
- /* IO0 clock at 480MHz */
- mxs_set_ioclk(MXC_IOCLK0, 480000);
- /* IO1 clock at 480MHz */
- mxs_set_ioclk(MXC_IOCLK1, 480000);
-
- /* SSP0 clock at 96MHz */
- mxs_set_sspclk(MXC_SSPCLK0, 96000, 0);
-
- return 0;
-}
-
-int dram_init(void)
-{
- return mxs_dram_init();
-}
-
-int board_init(void)
-{
- /* Adress of boot parameters */
- gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
-
- return 0;
-}
-
-#ifdef CONFIG_CMD_MMC
-int board_mmc_init(struct bd_info *bis)
-{
- return mxsmmc_initialize(bis, 0, NULL, NULL);
-}
-#endif
-
-
-#ifdef CONFIG_CMD_NET
-
-#define MII_PHY_CTRL2 0x1f
-int fecmxc_mii_postcall(int phy)
-{
- /* change PHY RMII clock to 50MHz */
- miiphy_write("FEC", 0, MII_PHY_CTRL2, 0x8180);
-
- return 0;
-}
-
-int board_eth_init(struct bd_info *bis)
-{
- int ret;
- struct eth_device *dev;
-
- ret = cpu_eth_init(bis);
- if (ret) {
- printf("FEC MXS: Unable to init FEC clocks\n");
- return ret;
- }
-
- ret = fecmxc_initialize(bis);
- if (ret) {
- printf("FEC MXS: Unable to init FEC\n");
- return ret;
- }
-
- dev = eth_get_dev_by_name("FEC");
- if (!dev) {
- printf("FEC MXS: Unable to get FEC device entry\n");
- return -EINVAL;
- }
-
- ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall);
- if (ret) {
- printf("FEC MXS: Unable to register FEC MII postcall\n");
- return ret;
- }
-
- return ret;
-}
-#endif
-
-#ifdef CONFIG_SERIAL_TAG
-#define MXS_OCOTP_MAX_TIMEOUT 1000000
-void get_board_serial(struct tag_serialnr *serialnr)
-{
- struct mxs_ocotp_regs *ocotp_regs =
- (struct mxs_ocotp_regs *)MXS_OCOTP_BASE;
-
- serialnr->high = 0;
- serialnr->low = 0;
-
- writel(OCOTP_CTRL_RD_BANK_OPEN, &ocotp_regs->hw_ocotp_ctrl_set);
-
- if (mxs_wait_mask_clr(&ocotp_regs->hw_ocotp_ctrl_reg, OCOTP_CTRL_BUSY,
- MXS_OCOTP_MAX_TIMEOUT)) {
- printf("MXS: Can't get serial number from OCOTP\n");
- return;
- }
-
- serialnr->low = readl(&ocotp_regs->hw_ocotp_cust3);
-}
-#endif
-
-#ifdef CONFIG_REVISION_TAG
-u32 get_board_rev(void)
-{
- if (env_get("revision#") != NULL)
- return simple_strtoul(env_get("revision#"), NULL, 10);
- return 0;
-}
-#endif
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Bluegiga APX4 Development Kit
- *
- * Copyright (C) 2012 Bluegiga Technologies Oy
- *
- * Authors:
- * Veli-Pekka Peltola <veli-pekka.peltola@bluegiga.com>
- * Lauri Hintsala <lauri.hintsala@bluegiga.com>
- *
- * Based on spl_boot.c:
- * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
- * on behalf of DENX Software Engineering GmbH
- */
-
-#include <common.h>
-#include <config.h>
-#include <asm/gpio.h>
-#include <asm/io.h>
-#include <asm/arch/iomux-mx28.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/sys_proto.h>
-
-#define MUX_CONFIG_SSP0 (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP)
-#define MUX_CONFIG_GPMI (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL)
-#define MUX_CONFIG_ENET (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP)
-#define MUX_CONFIG_EMI (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL)
-
-const iomux_cfg_t iomux_setup[] = {
- /* DUART */
- MX28_PAD_PWM0__DUART_RX,
- MX28_PAD_PWM1__DUART_TX,
-
- /* LED */
- MX28_PAD_PWM3__GPIO_3_28,
-
- /* MMC0 */
- MX28_PAD_SSP0_DATA0__SSP0_D0 | MUX_CONFIG_SSP0,
- MX28_PAD_SSP0_DATA1__SSP0_D1 | MUX_CONFIG_SSP0,
- MX28_PAD_SSP0_DATA2__SSP0_D2 | MUX_CONFIG_SSP0,
- MX28_PAD_SSP0_DATA3__SSP0_D3 | MUX_CONFIG_SSP0,
- MX28_PAD_SSP0_CMD__SSP0_CMD | MUX_CONFIG_SSP0,
- MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT |
- (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_NOPULL),
- MX28_PAD_SSP0_SCK__SSP0_SCK |
- (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
-
- /* GPMI NAND */
- MX28_PAD_GPMI_D00__GPMI_D0 | MUX_CONFIG_GPMI,
- MX28_PAD_GPMI_D01__GPMI_D1 | MUX_CONFIG_GPMI,
- MX28_PAD_GPMI_D02__GPMI_D2 | MUX_CONFIG_GPMI,
- MX28_PAD_GPMI_D03__GPMI_D3 | MUX_CONFIG_GPMI,
- MX28_PAD_GPMI_D04__GPMI_D4 | MUX_CONFIG_GPMI,
- MX28_PAD_GPMI_D05__GPMI_D5 | MUX_CONFIG_GPMI,
- MX28_PAD_GPMI_D06__GPMI_D6 | MUX_CONFIG_GPMI,
- MX28_PAD_GPMI_D07__GPMI_D7 | MUX_CONFIG_GPMI,
- MX28_PAD_GPMI_CE0N__GPMI_CE0N | MUX_CONFIG_GPMI,
- MX28_PAD_GPMI_RDY0__GPMI_READY0 | MUX_CONFIG_GPMI,
- MX28_PAD_GPMI_RDN__GPMI_RDN |
- (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP),
- MX28_PAD_GPMI_WRN__GPMI_WRN | MUX_CONFIG_GPMI,
- MX28_PAD_GPMI_ALE__GPMI_ALE | MUX_CONFIG_GPMI,
- MX28_PAD_GPMI_CLE__GPMI_CLE | MUX_CONFIG_GPMI,
- MX28_PAD_GPMI_RESETN__GPMI_RESETN | MUX_CONFIG_GPMI,
-
- /* FEC0 */
- MX28_PAD_ENET0_MDC__ENET0_MDC | MUX_CONFIG_ENET,
- MX28_PAD_ENET0_MDIO__ENET0_MDIO | MUX_CONFIG_ENET,
- MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | MUX_CONFIG_ENET,
- MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | MUX_CONFIG_ENET,
- MX28_PAD_ENET0_RXD0__ENET0_RXD0 | MUX_CONFIG_ENET,
- MX28_PAD_ENET0_RXD1__ENET0_RXD1 | MUX_CONFIG_ENET,
- MX28_PAD_ENET0_TXD0__ENET0_TXD0 | MUX_CONFIG_ENET,
- MX28_PAD_ENET0_TXD1__ENET0_TXD1 | MUX_CONFIG_ENET,
- MX28_PAD_ENET_CLK__CLKCTRL_ENET | MUX_CONFIG_ENET,
-
- /* I2C */
- MX28_PAD_I2C0_SCL__I2C0_SCL,
- MX28_PAD_I2C0_SDA__I2C0_SDA,
-
- /* EMI */
- MX28_PAD_EMI_D00__EMI_DATA0 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_D01__EMI_DATA1 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_D02__EMI_DATA2 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_D03__EMI_DATA3 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_D04__EMI_DATA4 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_D05__EMI_DATA5 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_D06__EMI_DATA6 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_D07__EMI_DATA7 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_D08__EMI_DATA8 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_D09__EMI_DATA9 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_D10__EMI_DATA10 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_D11__EMI_DATA11 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_D12__EMI_DATA12 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_D13__EMI_DATA13 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_D14__EMI_DATA14 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_D15__EMI_DATA15 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_ODT0__EMI_ODT0 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_ODT1__EMI_ODT1 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK | MUX_CONFIG_EMI,
- MX28_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI,
- MX28_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN | MUX_CONFIG_EMI,
-
- MX28_PAD_EMI_A00__EMI_ADDR0 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_A01__EMI_ADDR1 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_A02__EMI_ADDR2 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_A03__EMI_ADDR3 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_A04__EMI_ADDR4 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_A05__EMI_ADDR5 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_A06__EMI_ADDR6 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_A07__EMI_ADDR7 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_A08__EMI_ADDR8 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_A09__EMI_ADDR9 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_A10__EMI_ADDR10 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_A11__EMI_ADDR11 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_A12__EMI_ADDR12 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_A13__EMI_ADDR13 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_A14__EMI_ADDR14 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_BA2__EMI_BA2 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI,
- MX28_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI,
- MX28_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI,
- MX28_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI,
- MX28_PAD_EMI_CE1N__EMI_CE1N | MUX_CONFIG_EMI,
- MX28_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI,
-};
-
-void board_init_ll(const uint32_t arg, const uint32_t *resptr)
-{
- mxs_common_spl_init(arg, resptr, iomux_setup, ARRAY_SIZE(iomux_setup));
-
- /* switch LED on */
- gpio_direction_output(MX28_PAD_PWM3__GPIO_3_28, 0);
-}
-
-void mxs_adjust_memory_params(uint32_t *dram_vals)
-{
- /*
- * All address lines are routed from CPU to memory chip.
- * ADDR_PINS field is set to zero.
- */
- dram_vals[0x74 >> 2] = 0x0f02000a;
-
- /* Used memory has 4 banks. EIGHT_BANK_MODE bit is disabled. */
- dram_vals[0x7c >> 2] = 0x00000101;
-}
obj-$(CONFIG_TARGET_MPC8555CDS) += cds_pci_ft.o
obj-$(CONFIG_TARGET_MPC8536DS) += ics307_clk.o
-obj-$(CONFIG_TARGET_MPC8572DS) += ics307_clk.o
obj-$(CONFIG_TARGET_P1022DS) += ics307_clk.o
obj-$(CONFIG_P2020DS) += ics307_clk.o
obj-$(CONFIG_TARGET_P3041DS) += ics307_clk.o
u8 vtempmax[2];
u8 res2[4];
} __attribute__ ((packed)) pixis_t;
-
-#elif defined(CONFIG_TARGET_MPC8544DS)
-typedef struct pixis {
- u8 id;
- u8 ver;
- u8 pver;
- u8 csr;
- u8 rst;
- u8 pwr;
- u8 aux1;
- u8 spd;
- u8 res[8];
- u8 vctl;
- u8 vstat;
- u8 vcfgen0;
- u8 vcfgen1;
- u8 vcore0;
- u8 res1;
- u8 vboot;
- u8 vspeed[2];
- u8 vclkh;
- u8 vclkl;
- u8 watch;
- u8 led;
- u8 vspeed2;
- u8 res2[34];
-} __attribute__ ((packed)) pixis_t;
-
-#elif defined(CONFIG_TARGET_MPC8572DS)
-typedef struct pixis {
- u8 id;
- u8 ver;
- u8 pver;
- u8 csr;
- u8 rst;
- u8 pwr1;
- u8 aux1;
- u8 spd;
- u8 aux2;
- u8 res[7];
- u8 vctl;
- u8 vstat;
- u8 vcfgen0;
- u8 vcfgen1;
- u8 vcore0;
- u8 res1;
- u8 vboot;
- u8 vspeed[3];
- u8 res2[2];
- u8 sclk[3];
- u8 dclk[3];
- u8 res3[2];
- u8 watch;
- u8 led;
- u8 res4[25];
-} __attribute__ ((packed)) pixis_t;
-
-#elif defined(CONFIG_TARGET_MPC8610HPCD)
-typedef struct pixis {
- u8 id;
- u8 ver; /* also called arch */
- u8 pver;
- u8 csr;
- u8 rst;
- u8 pwr;
- u8 aux;
- u8 spd;
- u8 brdcfg0;
- u8 brdcfg1;
- u8 res[4];
- u8 led;
- u8 serno;
- u8 vctl;
- u8 vstat;
- u8 vcfgen0;
- u8 vcfgen1;
- u8 vcore0;
- u8 res1;
- u8 vboot;
- u8 vspeed[2];
- u8 res2;
- u8 sclk[3];
- u8 res3;
- u8 watch;
- u8 res4[33];
-} __attribute__ ((packed)) pixis_t;
-
-#elif defined(CONFIG_TARGET_MPC8641HPCN)
-typedef struct pixis {
- u8 id;
- u8 ver;
- u8 pver;
- u8 csr;
- u8 rst;
- u8 pwr;
- u8 aux;
- u8 spd;
- u8 res[8];
- u8 vctl;
- u8 vstat;
- u8 vcfgen0;
- u8 vcfgen1;
- u8 vcore0;
- u8 res1;
- u8 vboot;
- u8 vspeed[2];
- u8 vclkh;
- u8 vclkl;
- u8 watch;
- u8 res3[36];
-} __attribute__ ((packed)) pixis_t;
#else
#error Need to define pixis_t for this board
#endif
+++ /dev/null
-if TARGET_LS2080A_EMU
-
-config SYS_BOARD
- default "ls2080a"
-
-config SYS_VENDOR
- default "freescale"
-
-config SYS_SOC
- default "fsl-layerscape"
-
-config SYS_CONFIG_NAME
- default "ls2080a_emu"
-
-source "board/freescale/common/Kconfig"
-
-endif
-
-if TARGET_LS2080A_SIMU
-
-config SYS_BOARD
- default "ls2080a"
-
-config SYS_VENDOR
- default "freescale"
-
-config SYS_SOC
- default "fsl-layerscape"
-
-config SYS_CONFIG_NAME
- default "ls2080a_simu"
-
-source "board/freescale/common/Kconfig"
-
-endif
+++ /dev/null
-LS2080A BOARD
-M: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
-M: Priyanka Jain <priyanka.jain@nxp.com>
-S: Maintained
-F: board/freescale/ls2080a/
-F: include/configs/ls2080a_emu.h
-F: configs/ls2080a_emu_defconfig
-F: include/configs/ls2080a_simu.h
-F: configs/ls2080a_simu_defconfig
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright 2014-15 Freescale Semiconductor
-
-obj-y += ls2080a.o
-obj-y += ddr.o
+++ /dev/null
-Freescale ls2080a_emu
-
-This is a emulator target with limited peripherals.
-
-Memory map from core's view
-
-0x00_0000_0000 .. 0x00_000F_FFFF Boot Rom
-0x00_0100_0000 .. 0x00_0FFF_FFFF CCSR
-0x00_1800_0000 .. 0x00_181F_FFFF OCRAM
-0x00_3000_0000 .. 0x00_3FFF_FFFF IFC region #1
-0x00_8000_0000 .. 0x00_FFFF_FFFF DDR region #1
-0x05_1000_0000 .. 0x05_FFFF_FFFF IFC region #2
-0x80_8000_0000 .. 0xFF_FFFF_FFFF DDR region #2
-
-Other addresses are either reserved, or not used directly by U-Boot.
-This list should be updated when more addresses are used.
-
-Booting Linux flavors which do not support 48-bit VA (< Linux 3.18)
--------------------------------------------------------------------
-One needs to use appropriate bootargs to boot Linux flavors which do
-not support 48-bit VA (for e.g. < Linux 3.18) by appending mem=2048M, as shown
-below:
-
-=> setenv bootargs 'console=ttyS1,115200 root=/dev/ram
- earlycon=uart8250,mmio,0x21c0600,115200 default_hugepagesz=2m hugepagesz=2m
- hugepages=16 mem=2048M'
-
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2014 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-#include <log.h>
-#include <asm/arch/soc.h>
-#include <asm/arch/clock.h>
-#include "ddr.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void fsl_ddr_board_options(memctl_options_t *popts,
- dimm_params_t *pdimm,
- unsigned int ctrl_num)
-{
- const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
- ulong ddr_freq;
-
- if (ctrl_num > 3) {
- printf("Not supported controller number %d\n", ctrl_num);
- return;
- }
- if (!pdimm->n_ranks)
- return;
-
- /*
- * we use identical timing for all slots. If needed, change the code
- * to pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num];
- */
- if (popts->registered_dimm_en)
- pbsp = rdimms[ctrl_num];
- else
- pbsp = udimms[ctrl_num];
-
-
- /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
- * freqency and n_banks specified in board_specific_parameters table.
- */
- ddr_freq = get_ddr_freq(0) / 1000000;
- while (pbsp->datarate_mhz_high) {
- if (pbsp->n_ranks == pdimm->n_ranks &&
- (pdimm->rank_density >> 30) >= pbsp->rank_gb) {
- if (ddr_freq <= pbsp->datarate_mhz_high) {
- popts->clk_adjust = pbsp->clk_adjust;
- popts->wrlvl_start = pbsp->wrlvl_start;
- popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
- popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
- goto found;
- }
- pbsp_highest = pbsp;
- }
- pbsp++;
- }
-
- if (pbsp_highest) {
- printf("Error: board specific timing not found for data rate %lu MT/s\n"
- "Trying to use the highest speed (%u) parameters\n",
- ddr_freq, pbsp_highest->datarate_mhz_high);
- popts->clk_adjust = pbsp_highest->clk_adjust;
- popts->wrlvl_start = pbsp_highest->wrlvl_start;
- popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
- popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
- } else {
- panic("DIMM is not supported by this board");
- }
-found:
- debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
- "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, wrlvl_ctrl_3 0x%x\n",
- pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
- pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
- pbsp->wrlvl_ctl_3);
-#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
- if (ctrl_num == CONFIG_DP_DDR_CTRL) {
- /* force DDR bus width to 32 bits */
- popts->data_bus_width = 1;
- popts->otf_burst_chop_en = 0;
- popts->burst_length = DDR_BL8;
- popts->bstopre = 0; /* enable auto precharge */
- }
-#endif
- /*
- * Factors to consider for half-strength driver enable:
- * - number of DIMMs installed
- */
- popts->half_strength_driver_enable = 1;
- /*
- * Write leveling override
- */
- popts->wrlvl_override = 1;
- popts->wrlvl_sample = 0xf;
-
- /*
- * Rtt and Rtt_WR override
- */
- popts->rtt_override = 0;
-
- /* Enable ZQ calibration */
- popts->zq_en = 1;
-
-#ifdef CONFIG_SYS_FSL_DDR4
- popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
- popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) |
- DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */
-#else
- /* DHC_EN =1, ODT = 75 Ohm */
- popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
- popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
-#endif
-}
-
-#ifdef CONFIG_SYS_DDR_RAW_TIMING
-dimm_params_t ddr_raw_timing = {
- .n_ranks = 2,
- .rank_density = 1073741824u,
- .capacity = 2147483648,
- .primary_sdram_width = 64,
- .ec_sdram_width = 0,
- .registered_dimm = 0,
- .mirrored_dimm = 0,
- .n_row_addr = 14,
- .n_col_addr = 10,
- .n_banks_per_sdram_device = 8,
- .edc_config = 0,
- .burst_lengths_bitmask = 0x0c,
-
- .tckmin_x_ps = 937,
- .caslat_x = 0x6FC << 4, /* 14,13,11,10,9,8,7,6 */
- .taa_ps = 13090,
- .twr_ps = 15000,
- .trcd_ps = 13090,
- .trrd_ps = 5000,
- .trp_ps = 13090,
- .tras_ps = 33000,
- .trc_ps = 46090,
- .trfc_ps = 160000,
- .twtr_ps = 7500,
- .trtp_ps = 7500,
- .refresh_rate_ps = 7800000,
- .tfaw_ps = 25000,
-};
-
-int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
- unsigned int controller_number,
- unsigned int dimm_number)
-{
- const char dimm_model[] = "Fixed DDR on board";
-
- if (((controller_number == 0) && (dimm_number == 0)) ||
- ((controller_number == 1) && (dimm_number == 0))) {
- memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
- memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
- memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
- }
-
- return 0;
-}
-#endif
-
-int fsl_initdram(void)
-{
- puts("Initializing DDR....");
-
- puts("using SPD\n");
- gd->ram_size = fsl_ddr_sdram();
-
- return 0;
-}
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2014 Freescale Semiconductor, Inc.
- */
-
-#ifndef __DDR_H__
-#define __DDR_H__
-struct board_specific_parameters {
- u32 n_ranks;
- u32 datarate_mhz_high;
- u32 rank_gb;
- u32 clk_adjust;
- u32 wrlvl_start;
- u32 wrlvl_ctl_2;
- u32 wrlvl_ctl_3;
-};
-
-/*
- * These tables contain all valid speeds we want to override with board
- * specific parameters. datarate_mhz_high values need to be in ascending order
- * for each n_ranks group.
- */
-
-static const struct board_specific_parameters udimm0[] = {
- /*
- * memory controller 0
- * num| hi| rank| clk| wrlvl | wrlvl | wrlvl
- * ranks| mhz| GB |adjst| start | ctl2 | ctl3
- */
- {2, 2140, 0, 4, 4, 0x0, 0x0},
- {1, 2140, 0, 4, 4, 0x0, 0x0},
- {}
-};
-
-/* DP-DDR DIMM */
-static const struct board_specific_parameters udimm2[] = {
- /*
- * memory controller 2
- * num| hi| rank| clk| wrlvl | wrlvl | wrlvl
- * ranks| mhz| GB |adjst| start | ctl2 | ctl3
- */
- {2, 2140, 0, 4, 4, 0x0, 0x0},
- {1, 2140, 0, 4, 4, 0x0, 0x0},
- {}
-};
-
-static const struct board_specific_parameters rdimm0[] = {
- /*
- * memory controller 0
- * num| hi| rank| clk| wrlvl | wrlvl | wrlvl
- * ranks| mhz| GB |adjst| start | ctl2 | ctl3
- */
- {4, 2140, 0, 5, 4, 0x0, 0x0},
- {2, 2140, 0, 5, 4, 0x0, 0x0},
- {1, 2140, 0, 4, 4, 0x0, 0x0},
- {}
-};
-
-/* DP-DDR DIMM */
-static const struct board_specific_parameters rdimm2[] = {
- /*
- * memory controller 2
- * num| hi| rank| clk| wrlvl | wrlvl | wrlvl
- * ranks| mhz| GB |adjst| start | ctl2 | ctl3
- */
- {4, 2140, 0, 5, 4, 0x0, 0x0},
- {2, 2140, 0, 5, 4, 0x0, 0x0},
- {1, 2140, 0, 4, 4, 0x0, 0x0},
- {}
-};
-
-static const struct board_specific_parameters *udimms[] = {
- udimm0,
- udimm0,
- udimm2,
-};
-
-static const struct board_specific_parameters *rdimms[] = {
- rdimm0,
- rdimm0,
- rdimm2,
-};
-
-
-#endif
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2014 Freescale Semiconductor
- */
-#include <common.h>
-#include <init.h>
-#include <malloc.h>
-#include <errno.h>
-#include <net.h>
-#include <netdev.h>
-#include <fsl_ifc.h>
-#include <fsl_ddr.h>
-#include <asm/io.h>
-#include <fdt_support.h>
-#include <linux/libfdt.h>
-#include <fsl-mc/fsl_mc.h>
-#include <env_internal.h>
-#include <asm/arch/soc.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_init(void)
-{
- init_final_memctl_regs();
-
-#ifdef CONFIG_ENV_IS_NOWHERE
- gd->env_addr = (ulong)&default_environment[0];
-#endif
-
- return 0;
-}
-
-int board_early_init_f(void)
-{
- fsl_lsch3_early_init_f();
- return 0;
-}
-
-void detail_board_ddr_info(void)
-{
- puts("\nDDR ");
- print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
- print_ddr_info(0);
-#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
- if (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) {
- puts("\nDP-DDR ");
- print_size(gd->bd->bi_dram[2].size, "");
- print_ddr_info(CONFIG_DP_DDR_CTRL);
- }
-#endif
-}
-
-int board_eth_init(struct bd_info *bis)
-{
- int error = 0;
-
-#ifdef CONFIG_SMC91111
- error = smc91111_initialize(0, CONFIG_SMC91111_BASE);
-#endif
-
-#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
- error = cpu_eth_init(bis);
-#endif
- return error;
-}
-
-#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
-void fdt_fixup_board_enet(void *fdt)
-{
- int offset;
-
- offset = fdt_path_offset(fdt, "/soc/fsl-mc");
-
- /*
- * TODO: Remove this when backward compatibility
- * with old DT node (/fsl-mc) is no longer needed.
- */
- if (offset < 0)
- offset = fdt_path_offset(fdt, "/fsl-mc");
-
- if (offset < 0) {
- printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
- __func__, offset);
- return;
- }
-
- if (get_mc_boot_status() == 0 &&
- (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0))
- fdt_status_okay(fdt, offset);
- else
- fdt_status_fail(fdt, offset);
-}
-
-void board_quiesce_devices(void)
-{
- fsl_mc_ldpaa_exit(gd->bd);
-}
-#endif
-
-#ifdef CONFIG_OF_BOARD_SETUP
-int ft_board_setup(void *blob, struct bd_info *bd)
-{
- u64 base[CONFIG_NR_DRAM_BANKS];
- u64 size[CONFIG_NR_DRAM_BANKS];
-
- ft_cpu_setup(blob, bd);
-
- /* fixup DT for the two GPP DDR banks */
- base[0] = gd->bd->bi_dram[0].start;
- size[0] = gd->bd->bi_dram[0].size;
- base[1] = gd->bd->bi_dram[1].start;
- size[1] = gd->bd->bi_dram[1].size;
-
-#ifdef CONFIG_RESV_RAM
- /* reduce size if reserved memory is within this bank */
- if (gd->arch.resv_ram >= base[0] &&
- gd->arch.resv_ram < base[0] + size[0])
- size[0] = gd->arch.resv_ram - base[0];
- else if (gd->arch.resv_ram >= base[1] &&
- gd->arch.resv_ram < base[1] + size[1])
- size[1] = gd->arch.resv_ram - base[1];
-#endif
-
- fdt_fixup_memory_banks(blob, base, size, 2);
-
- fdt_fsl_mc_fixup_iommu_map_entry(blob);
-
-#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
- fdt_fixup_board_enet(blob);
-#endif
-
- return 0;
-}
-#endif
-
-#if defined(CONFIG_RESET_PHY_R)
-void reset_phy(void)
-{
-}
-#endif
-
-#ifdef CONFIG_TFABOOT
-void *env_sf_get_env_addr(void)
-{
- return (void *)(CONFIG_SYS_FSL_QSPI_BASE1 + CONFIG_ENV_OFFSET);
-}
-#endif
+++ /dev/null
-if TARGET_MPC8544DS
-
-config SYS_BOARD
- default "mpc8544ds"
-
-config SYS_VENDOR
- default "freescale"
-
-config SYS_CONFIG_NAME
- default "MPC8544DS"
-
-endif
+++ /dev/null
-MPC8544DS BOARD
-M: Priyanka Jain <priyanka.jain@nxp.com>
-S: Maintained
-F: board/freescale/mpc8544ds/
-F: include/configs/MPC8544DS.h
-F: configs/MPC8544DS_defconfig
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright 2007 Freescale Semiconductor, Inc.
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-
-obj-y += mpc8544ds.o
-obj-y += ddr.o
-obj-y += law.o
-obj-y += tlb.o
+++ /dev/null
-Overview
---------
-The MPC8544DS system is similar to the 85xx CDS systems such
-as the MPC8548CDS due to the similar E500 core. However, it
-is placed on the same board as the 8641 HPCN system.
-
-
-Flash Banks
------------
-Like the 85xx CDS systems, the 8544 DS board has two flash banks.
-They are both present on boot, but there locations can be swapped
-using the dip-switch SW10, bit 2.
-
-However, unlike the CDS systems, but similar to the 8641 HPCN
-board, a runtime reset through the FPGA can also affect a swap
-on the flash bank mappings for the next reset cycle.
-
-Irrespective of the switch SW10[2], booting is always from the
-boot bank at 0xfff8_0000.
-
-
-Memory Map
-----------
-
-0xff80_0000 - 0xffbf_ffff Alternate bank 4MB
-0xffc0_0000 - 0xffff_ffff Boot bank 4MB
-
-0xffb8_0000 Alternate image start 512KB
-0xfff8_0000 Boot image start 512KB
-
-
-Flashing Images
----------------
-
-For example, to place a new image in the alternate flash bank
-and then reset with that new image temporarily, use this:
-
- tftp 1000000 u-boot.bin.8544ds
- erase ffb80000 ffbfffff
- cp.b 1000000 ffb80000 80000
- pixis_reset altbank
-
-
-To overwrite the image in the boot flash bank:
-
- tftp 1000000 u-boot.bin.8544ds
- protect off all
- erase fff80000 ffffffff
- cp.b 1000000 fff80000 80000
-
-Other example U-Boot image and flash manipulations examples
-can be found in the README.mpc85xxcds file as well.
-
-
-The pixis_reset command
------------------------
-A new command, "pixis_reset", is introduced to reset mpc8641hpcn board
-using the FPGA sequencer. When the board restarts, it has the option
-of using either the current or alternate flash bank as the boot
-image, with or without the watchdog timer enabled, and finally with
-or without frequency changes.
-
-Usage is;
-
- pixis_reset
- pixis_reset altbank
- pixis_reset altbank wd
- pixis_reset altbank cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
- pixis_reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
-
-Examples;
-
- /* reset to current bank, like "reset" command */
- pixis_reset
-
- /* reset board but use the to alternate flash bank */
- pixis_reset altbank
-
- /* reset board, use alternate flash bank with watchdog timer enabled*/
- pixis_reset altbank wd
-
- /* reset board to alternate bank with frequency changed.
- * 40 is SYSCLK, 2.5 is COREPLL ratio, 10 is MPXPLL ratio
- */
- pixis-reset altbank cf 40 2.5 10
-
-Valid clock choices are in the 8641 Reference Manuals.
-
-
-Using the Device Tree Source File
----------------------------------
-To create the DTB (Device Tree Binary) image file,
-use a command similar to this:
-
- dtc -b 0 -f -I dts -O dtb mpc8544ds.dts > mpc8544ds.dtb
-
-Likely, that .dts file will come from here;
-
- linux-2.6/arch/powerpc/boot/dts/mpc8544ds.dts
-
-After placing the DTB file in your TFTP disk area,
-you can download that dtb file using a command like:
-
- tftp 900000 mpc8544ds.dtb
-
-Burn it to flash if you want.
-
-
-Booting Linux
--------------
-
-Place a linux uImage in the TFTP disk area too.
-
- tftp 1000000 uImage.8544
- tftp 900000 mpc8544ds.dtb
- bootm 1000000 - 900000
-
-Watch your ethact, netdev and bootargs U-Boot environment variables.
-You may want to do something like this too:
-
- setenv ethact eTSEC3
- setenv netdev eth1
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright 2008 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-
-void fsl_ddr_board_options(memctl_options_t *popts,
- dimm_params_t *pdimm,
- unsigned int ctrl_num)
-{
- /*
- * Factors to consider for clock adjust:
- * - number of chips on bus
- * - position of slot
- * - DDR1 vs. DDR2?
- * - ???
- *
- * This needs to be determined on a board-by-board basis.
- * 0110 3/4 cycle late
- * 0111 7/8 cycle late
- */
- popts->clk_adjust = 7;
-
- /*
- * Factors to consider for CPO:
- * - frequency
- * - ddr1 vs. ddr2
- */
- popts->cpo_override = 10;
-
- /*
- * Factors to consider for write data delay:
- * - number of DIMMs
- *
- * 1 = 1/4 clock delay
- * 2 = 1/2 clock delay
- * 3 = 3/4 clock delay
- * 4 = 1 clock delay
- * 5 = 5/4 clock delay
- * 6 = 3/2 clock delay
- */
- popts->write_data_delay = 3;
-
- /* 2T timing enable */
- popts->twot_en = 1;
-
- /*
- * Factors to consider for half-strength driver enable:
- * - number of DIMMs installed
- */
- popts->half_strength_driver_enable = 0;
-}
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2008, 2010 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- */
-
-#include <common.h>
-#include <asm/fsl_law.h>
-#include <asm/mmu.h>
-
-struct law_entry law_table[] = {
- SET_LAW(CONFIG_SYS_LBC_NONCACHE_BASE, LAW_SIZE_128M, LAW_TRGT_IF_LBC),
-};
-
-int num_law_entries = ARRAY_SIZE(law_table);
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2007,2009-2010 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <command.h>
-#include <init.h>
-#include <net.h>
-#include <pci.h>
-#include <asm/processor.h>
-#include <asm/mmu.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_pci.h>
-#include <fsl_ddr_sdram.h>
-#include <asm/fsl_serdes.h>
-#include <asm/io.h>
-#include <miiphy.h>
-#include <linux/libfdt.h>
-#include <fdt_support.h>
-#include <fsl_mdio.h>
-#include <tsec.h>
-#include <netdev.h>
-
-#include "../common/sgmii_riser.h"
-
-int checkboard (void)
-{
- volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
- volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
- u8 vboot;
- u8 *pixis_base = (u8 *)PIXIS_BASE;
-
- if ((uint)&gur->porpllsr != 0xe00e0000) {
- printf("immap size error %lx\n",(ulong)&gur->porpllsr);
- }
- printf ("Board: MPC8544DS, Sys ID: 0x%02x, "
- "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
- in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
- in_8(pixis_base + PIXIS_PVER));
-
- vboot = in_8(pixis_base + PIXIS_VBOOT);
- if (vboot & PIXIS_VBOOT_FMAP)
- printf ("vBank: %d\n", ((vboot & PIXIS_VBOOT_FBANK) >> 6));
- else
- puts ("Promjet\n");
-
- lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */
- lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */
- ecm->eedr = 0xffffffff; /* Clear ecm errors */
- ecm->eeer = 0xffffffff; /* Enable ecm errors */
-
- return 0;
-}
-
-#ifdef CONFIG_PCI1
-static struct pci_controller pci1_hose;
-#endif
-
-#ifdef CONFIG_PCIE3
-static struct pci_controller pcie3_hose;
-#endif
-
-void pci_init_board(void)
-{
- volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- struct fsl_pci_info pci_info;
- u32 devdisr, pordevsr, io_sel;
- u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel;
- int first_free_busno = 0;
-
- int pcie_ep, pcie_configured;
-
- devdisr = in_be32(&gur->devdisr);
- pordevsr = in_be32(&gur->pordevsr);
- porpllsr = in_be32(&gur->porpllsr);
- io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
-
- debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel);
-
- puts("\n");
-
-#ifdef CONFIG_PCIE3
- pcie_configured = is_serdes_configured(PCIE3);
-
- if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)){
- /* contains both PCIE3 MEM & IO space */
- set_next_law(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_4M,
- LAW_TRGT_IF_PCIE_3);
- SET_STD_PCIE_INFO(pci_info, 3);
- pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info.regs);
-
- /* outbound memory */
- pci_set_region(&pcie3_hose.regions[0],
- CONFIG_SYS_PCIE3_MEM_BUS2,
- CONFIG_SYS_PCIE3_MEM_PHYS2,
- CONFIG_SYS_PCIE3_MEM_SIZE2,
- PCI_REGION_MEM);
-
- pcie3_hose.region_count = 1;
-
- printf("PCIE3: connected to ULI as %s (base addr %lx)\n",
- pcie_ep ? "Endpoint" : "Root Complex",
- pci_info.regs);
- first_free_busno = fsl_pci_init_port(&pci_info,
- &pcie3_hose, first_free_busno);
-
- /*
- * Activate ULI1575 legacy chip by performing a fake
- * memory access. Needed to make ULI RTC work.
- */
- in_be32((u32 *)CONFIG_SYS_PCIE3_MEM_BUS);
- } else {
- printf("PCIE3: disabled\n");
- }
- puts("\n");
-#else
- setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE3); /* disable */
-#endif
-
-#ifdef CONFIG_PCIE1
- SET_STD_PCIE_INFO(pci_info, 1);
- first_free_busno = fsl_pcie_init_ctrl(first_free_busno, devdisr, PCIE1, &pci_info);
-#else
- setbits_be32(&gur->devdisr, _DEVDISR_PCIE1); /* disable */
-#endif
-
-#ifdef CONFIG_PCIE2
- SET_STD_PCIE_INFO(pci_info, 2);
- first_free_busno = fsl_pcie_init_ctrl(first_free_busno, devdisr, PCIE2, &pci_info);
-#else
- setbits_be32(&gur->devdisr, _DEVDISR_PCIE2); /* disable */
-#endif
-
-#ifdef CONFIG_PCI1
- pci_speed = 66666000;
- pci_32 = 1;
- pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
- pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
-
- if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
- SET_STD_PCI_INFO(pci_info, 1);
- set_next_law(pci_info.mem_phys,
- law_size_bits(pci_info.mem_size), pci_info.law);
- set_next_law(pci_info.io_phys,
- law_size_bits(pci_info.io_size), pci_info.law);
-
- pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs);
- printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
- (pci_32) ? 32 : 64,
- (pci_speed == 33333000) ? "33" :
- (pci_speed == 66666000) ? "66" : "unknown",
- pci_clk_sel ? "sync" : "async",
- pci_agent ? "agent" : "host",
- pci_arb ? "arbiter" : "external-arbiter",
- pci_info.regs);
-
- first_free_busno = fsl_pci_init_port(&pci_info,
- &pci1_hose, first_free_busno);
- } else {
- printf("PCI: disabled\n");
- }
-
- puts("\n");
-#else
- setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
-#endif
-}
-
-int last_stage_init(void)
-{
- return 0;
-}
-
-
-unsigned long
-get_board_sys_clk(ulong dummy)
-{
- u8 i, go_bit, rd_clks;
- ulong val = 0;
- u8 *pixis_base = (u8 *)PIXIS_BASE;
-
- go_bit = in_8(pixis_base + PIXIS_VCTL);
- go_bit &= 0x01;
-
- rd_clks = in_8(pixis_base + PIXIS_VCFGEN0);
- rd_clks &= 0x1C;
-
- /*
- * Only if both go bit and the SCLK bit in VCFGEN0 are set
- * should we be using the AUX register. Remember, we also set the
- * GO bit to boot from the alternate bank on the on-board flash
- */
-
- if (go_bit) {
- if (rd_clks == 0x1c)
- i = in_8(pixis_base + PIXIS_AUX);
- else
- i = in_8(pixis_base + PIXIS_SPD);
- } else {
- i = in_8(pixis_base + PIXIS_SPD);
- }
-
- i &= 0x07;
-
- switch (i) {
- case 0:
- val = 33333333;
- break;
- case 1:
- val = 40000000;
- break;
- case 2:
- val = 50000000;
- break;
- case 3:
- val = 66666666;
- break;
- case 4:
- val = 83000000;
- break;
- case 5:
- val = 100000000;
- break;
- case 6:
- val = 133333333;
- break;
- case 7:
- val = 166666666;
- break;
- }
-
- return val;
-}
-
-
-#define MIIM_CIS8204_SLED_CON 0x1b
-#define MIIM_CIS8204_SLEDCON_INIT 0x1115
-/*
- * Hack to write all 4 PHYs with the LED values
- */
-int board_phy_config(struct phy_device *phydev)
-{
- static int do_once;
- uint phyid;
- struct mii_dev *bus = phydev->bus;
-
- if (phydev->drv->config)
- phydev->drv->config(phydev);
- if (do_once)
- return 0;
-
- for (phyid = 0; phyid < 4; phyid++)
- bus->write(bus, phyid, MDIO_DEVAD_NONE, MIIM_CIS8204_SLED_CON,
- MIIM_CIS8204_SLEDCON_INIT);
-
- do_once = 1;
-
- return 0;
-}
-
-
-int board_eth_init(struct bd_info *bis)
-{
-#ifdef CONFIG_TSEC_ENET
- struct fsl_pq_mdio_info mdio_info;
- struct tsec_info_struct tsec_info[2];
- int num = 0;
-
-#ifdef CONFIG_TSEC1
- SET_STD_TSEC_INFO(tsec_info[num], 1);
- if (is_serdes_configured(SGMII_TSEC1)) {
- puts("eTSEC1 is in sgmii mode.\n");
- tsec_info[num].flags |= TSEC_SGMII;
- }
- num++;
-#endif
-#ifdef CONFIG_TSEC3
- SET_STD_TSEC_INFO(tsec_info[num], 3);
- if (is_serdes_configured(SGMII_TSEC3)) {
- puts("eTSEC3 is in sgmii mode.\n");
- tsec_info[num].flags |= TSEC_SGMII;
- }
- num++;
-#endif
-
- if (!num) {
- printf("No TSECs initialized\n");
-
- return 0;
- }
-
- if (is_serdes_configured(SGMII_TSEC1) ||
- is_serdes_configured(SGMII_TSEC3)) {
- fsl_sgmii_riser_init(tsec_info, num);
- }
-
- mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
- mdio_info.name = DEFAULT_MII_NAME;
- fsl_pq_mdio_init(bis, &mdio_info);
-
- tsec_eth_init(bis, tsec_info, num);
-#endif
- return pci_eth_init(bis);
-}
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-int ft_board_setup(void *blob, struct bd_info *bd)
-{
- ft_cpu_setup(blob, bd);
-
- FT_FSL_PCI_SETUP;
-
-#ifdef CONFIG_FSL_SGMII_RISER
- fsl_sgmii_riser_fdt_fixup(blob);
-#endif
-
- return 0;
-}
-#endif
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2008 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- */
-
-#include <common.h>
-#include <asm/mmu.h>
-
-struct fsl_e_tlb_entry tlb_table[] = {
- /* TLB 0 - for temp stack in cache */
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- /*
- * TLB 0: 64M Non-cacheable, guarded
- * 0xfc000000 64M Covers FLASH at 0xFE800000 and 0xFF800000
- * Out of reset this entry is only 4K.
- */
- SET_TLB_ENTRY(1, CONFIG_SYS_BOOT_BLOCK, CONFIG_SYS_BOOT_BLOCK,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 0, BOOKE_PAGESZ_64M, 1),
- /*
- * TLB 1: 1G Non-cacheable, guarded
- * 0x80000000 1G PCIE 8,9,a,b
- */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE_VIRT, CONFIG_SYS_PCIE_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 1, BOOKE_PAGESZ_1G, 1),
-
- /*
- * TLB 2: 256M Non-cacheable, guarded
- */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCI_VIRT, CONFIG_SYS_PCI_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 2, BOOKE_PAGESZ_256M, 1),
-
- /*
- * TLB 3: 256M Non-cacheable, guarded
- */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCI_VIRT + 0x10000000, CONFIG_SYS_PCI_PHYS + 0x10000000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 3, BOOKE_PAGESZ_256M, 1),
-
- /*
- * TLB 4: 64M Non-cacheable, guarded
- * 0xe000_0000 1M CCSRBAR
- * 0xe100_0000 255M PCI IO range
- */
- SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 4, BOOKE_PAGESZ_64M, 1),
-
- /*
- * TLB 5: 64M Non-cacheable, guarded
- * 0xf8000000 64M PIXIS 0xF8000000 - 0xFBFFFFFF
- */
- SET_TLB_ENTRY(1, CONFIG_SYS_LBC_NONCACHE_BASE, CONFIG_SYS_LBC_NONCACHE_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 5, BOOKE_PAGESZ_64M, 1),
-};
-
-int num_tlb_entries = ARRAY_SIZE(tlb_table);
+++ /dev/null
-if TARGET_MPC8572DS
-
-config SYS_BOARD
- default "mpc8572ds"
-
-config SYS_VENDOR
- default "freescale"
-
-config SYS_CONFIG_NAME
- default "MPC8572DS"
-
-endif
+++ /dev/null
-MPC8572DS BOARD
-M: Priyanka Jain <priyanka.jain@nxp.com>
-S: Maintained
-F: board/freescale/mpc8572ds/
-F: include/configs/MPC8572DS.h
-F: configs/MPC8572DS_defconfig
-F: configs/MPC8572DS_36BIT_defconfig
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright 2007 Freescale Semiconductor, Inc.
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-
-obj-y += mpc8572ds.o
-obj-y += ddr.o
-obj-y += law.o
-obj-y += tlb.o
+++ /dev/null
-Overview
---------
-MPC8572DS is a high-performance computing, evaluation and development platform
-supporting the mpc8572 PowerTM processor.
-
-Building U-Boot
------------
- make MPC8572DS_config
- make
-
-Flash Banks
------------
-MPC8572DS board has two flash banks. They are both present on boot, but their
-locations can be swapped using the dip-switch SW9[1:2].
-
-Booting is always from the boot bank at 0xec00_0000.
-
-
-Memory Map
-----------
-
-0xe800_0000 - 0xebff_ffff Alternate bank 64MB
-0xec00_0000 - 0xefff_ffff Boot bank 64MB
-
-0xebf8_0000 - 0xebff_ffff Alternate U-Boot address 512KB
-0xeff8_0000 - 0xefff_ffff Boot U-Boot address 512KB
-
-
-Flashing Images
----------------
-
-To place a new U-Boot image in the alternate flash bank and then reset with that
- new image temporarily, use this:
-
- tftp 1000000 u-boot.bin
- erase ebf80000 ebffffff
- cp.b 1000000 ebf80000 80000
- pixis_reset altbank
-
-
-To program the image in the boot flash bank:
-
- tftp 1000000 u-boot.bin
- protect off all
- erase eff80000 ffffffff
- cp.b 1000000 eff80000 80000
-
-
-The pixis_reset command
------------------------
-The command - "pixis_reset", is introduced to reset mpc8572ds board
-using the FPGA sequencer. When the board restarts, it has the option
-of using either the current or alternate flash bank as the boot
-image, with or without the watchdog timer enabled, and finally with
-or without frequency changes.
-
-Usage is;
-
- pixis_reset
- pixis_reset altbank
- pixis_reset altbank wd
- pixis_reset altbank cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
- pixis_reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
-
-Examples:
-
- /* reset to current bank, like "reset" command */
- pixis_reset
-
- /* reset board but use the to alternate flash bank */
- pixis_reset altbank
-
-
-Using the Device Tree Source File
----------------------------------
-To create the DTB (Device Tree Binary) image file,
-use a command similar to this:
-
- dtc -b 0 -f -I dts -O dtb mpc8572ds.dts > mpc8572ds.dtb
-
-Likely, that .dts file will come from here;
-
- linux-2.6/arch/powerpc/boot/dts/mpc8572ds.dts
-
-
-Booting Linux
--------------
-
-Place a linux uImage in the TFTP disk area.
-
- tftp 1000000 uImage.8572
- tftp c00000 mpc8572ds.dtb
- bootm 1000000 - c00000
-
-
-Implementing AMP(Asymmetric MultiProcessing)
--------------
-1. Build kernel image for core0:
-
- a. $ make 85xx/mpc8572_ds_defconfig
-
- b. $ make menuconfig
- - un-select "Processor support"->"Symetric multi-processing support"
-
- c. $ make uImage
-
- d. $ cp arch/powerpc/boot/uImage /tftpboot/uImage.core0
-
-2. Build kernel image for core1:
-
- a. $ make 85xx/mpc8572_ds_defconfig
-
- b. $ make menuconfig
- - Un-select "Processor support"->"Symetric multi-processing support"
- - Select "Advanced setup" -> " Prompt for advanced kernel
- configuration options"
- - Select "Set physical address where the kernel is loaded" and
- set it to 0x20000000, assuming core1 will start from 512MB.
- - Select "Set custom page offset address"
- - Select "Set custom kernel base address"
- - Select "Set maximum low memory"
- - "Exit" and save the selection.
-
- c. $ make uImage
-
- d. $ cp arch/powerpc/boot/uImage /tftpboot/uImage.core1
-
-3. Create dtb for core0:
-
- $ dtc -I dts -O dtb -f -b 0 arch/powerpc/boot/dts/mpc8572ds_core0.dts > /tftpboot/mpc8572ds_core0.dtb
-
-4. Create dtb for core1:
-
- $ dtc -I dts -O dtb -f -b 1 arch/powerpc/boot/dts/mpc8572ds_core1.dts > /tftpboot/mpc8572ds_core1.dtb
-
-5. Bring up two cores separately:
-
- a. Power on the board, under U-Boot prompt:
- => setenv <serverip>
- => setenv <ipaddr>
- => setenv bootargs root=/dev/ram rw console=ttyS0,115200
- b. Bring up core1's kernel first:
- => setenv bootm_low 0x20000000
- => setenv bootm_size 0x10000000
- => tftp 21000000 8572/uImage.core1
- => tftp 22000000 8572/ramdiskfile
- => tftp 20c00000 8572/mpc8572ds_core1.dtb
- => interrupts off
- => bootm start 21000000 22000000 20c00000
- => bootm loados
- => bootm ramdisk
- => bootm fdt
- => fdt boardsetup
- => fdt chosen $initrd_start $initrd_end
- => bootm prep
- => cpu 1 release $bootm_low - $fdtaddr -
- c. Bring up core0's kernel(on the same U-Boot console):
- => setenv bootm_low 0
- => setenv bootm_size 0x20000000
- => tftp 1000000 8572/uImage.core0
- => tftp 2000000 8572/ramdiskfile
- => tftp c00000 8572/mpc8572ds_core0.dtb
- => bootm 1000000 2000000 c00000
-
-Please note only core0 will run U-Boot, core1 starts kernel directly after
-"cpu release" command is issued.
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright 2008 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-
-struct board_specific_parameters {
- u32 n_ranks;
- u32 datarate_mhz_high;
- u32 clk_adjust;
- u32 cpo;
- u32 write_data_delay;
- u32 force_2t;
-};
-
-/*
- * This table contains all valid speeds we want to override with board
- * specific parameters. datarate_mhz_high values need to be in ascending order
- * for each n_ranks group.
- *
- * For DDR2 DIMM, all combinations of clk_adjust and write_data_delay have been
- * tested. For RDIMM, clk_adjust = 4 and write_data_delay = 3 is optimized for
- * all clocks from 400MT/s to 800MT/s, verified with Kingston KVR800D2D8P6/2G.
- * For UDIMM, clk_adjust = 8 and write_delay = 5 is optimized for all clocks
- * from 400MT/s to 800MT/s, verified with Micron MT18HTF25672AY-800E1.
- *
- * CPO value doesn't matter if workaround for errata 111 and 134 enabled.
- */
-static const struct board_specific_parameters udimm0[] = {
- /*
- * memory controller 0
- * num| hi| clk| cpo|wrdata|2T
- * ranks| mhz|adjst| | delay|
- */
- {2, 333, 8, 7, 5, 0},
- {2, 400, 8, 9, 5, 0},
- {2, 549, 8, 11, 5, 0},
- {2, 680, 8, 10, 5, 0},
- {2, 850, 8, 12, 5, 1},
- {1, 333, 6, 7, 3, 0},
- {1, 400, 6, 9, 3, 0},
- {1, 549, 6, 11, 3, 0},
- {1, 680, 1, 10, 5, 0},
- {1, 850, 1, 12, 5, 0},
- {}
-};
-
-static const struct board_specific_parameters udimm1[] = {
- /*
- * memory controller 1
- * num| hi| clk| cpo|wrdata|2T
- * ranks| mhz|adjst| | delay|
- */
- {2, 333, 8, 7, 5, 0},
- {2, 400, 8, 9, 5, 0},
- {2, 549, 8, 11, 5, 0},
- {2, 680, 8, 11, 5, 0},
- {2, 850, 8, 13, 5, 1},
- {1, 333, 6, 7, 3, 0},
- {1, 400, 6, 9, 3, 0},
- {1, 549, 6, 11, 3, 0},
- {1, 680, 1, 11, 6, 0},
- {1, 850, 1, 13, 6, 0},
- {}
-};
-
-static const struct board_specific_parameters *udimms[] = {
- udimm0,
- udimm1,
-};
-
-static const struct board_specific_parameters rdimm0[] = {
- /*
- * memory controller 0
- * num| hi| clk| cpo|wrdata|2T
- * ranks| mhz|adjst| | delay|
- */
- {2, 333, 4, 7, 3, 0},
- {2, 400, 4, 9, 3, 0},
- {2, 549, 4, 11, 3, 0},
- {2, 680, 4, 10, 3, 0},
- {2, 850, 4, 12, 3, 1},
- {}
-};
-
-static const struct board_specific_parameters rdimm1[] = {
- /*
- * memory controller 1
- * num| hi| clk| cpo|wrdata|2T
- * ranks| mhz|adjst| | delay|
- */
- {2, 333, 4, 7, 3, 0},
- {2, 400, 4, 9, 3, 0},
- {2, 549, 4, 11, 3, 0},
- {2, 680, 4, 11, 3, 0},
- {2, 850, 4, 13, 3, 1},
- {}
-};
-
-static const struct board_specific_parameters *rdimms[] = {
- rdimm0,
- rdimm1,
-};
-
-void fsl_ddr_board_options(memctl_options_t *popts,
- dimm_params_t *pdimm,
- unsigned int ctrl_num)
-{
- const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
- ulong ddr_freq;
-
- if (ctrl_num > 1) {
- printf("Wrong parameter for controller number %d", ctrl_num);
- return;
- }
- if (!pdimm->n_ranks)
- return;
-
- if (popts->registered_dimm_en)
- pbsp = rdimms[ctrl_num];
- else
- pbsp = udimms[ctrl_num];
-
- /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
- * freqency and n_banks specified in board_specific_parameters table.
- */
- ddr_freq = get_ddr_freq(0) / 1000000;
- while (pbsp->datarate_mhz_high) {
- if (pbsp->n_ranks == pdimm->n_ranks) {
- if (ddr_freq <= pbsp->datarate_mhz_high) {
- popts->clk_adjust = pbsp->clk_adjust;
- popts->cpo_override = pbsp->cpo;
- popts->write_data_delay =
- pbsp->write_data_delay;
- popts->twot_en = pbsp->force_2t;
- goto found;
- }
- pbsp_highest = pbsp;
- }
- pbsp++;
- }
-
- if (pbsp_highest) {
- printf("Error: board specific timing not found "
- "for data rate %lu MT/s!\n"
- "Trying to use the highest speed (%u) parameters\n",
- ddr_freq, pbsp_highest->datarate_mhz_high);
- popts->clk_adjust = pbsp->clk_adjust;
- popts->cpo_override = pbsp->cpo;
- popts->write_data_delay = pbsp->write_data_delay;
- popts->twot_en = pbsp->force_2t;
- } else {
- panic("DIMM is not supported by this board");
- }
-
-found:
- /*
- * Factors to consider for half-strength driver enable:
- * - number of DIMMs installed
- */
- popts->half_strength_driver_enable = 0;
-}
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2008, 2010 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- */
-
-#include <common.h>
-#include <asm/fsl_law.h>
-#include <asm/mmu.h>
-
-struct law_entry law_table[] = {
- SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
- SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC),
- SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
-};
-
-int num_law_entries = ARRAY_SIZE(law_table);
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2007-2011 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <command.h>
-#include <env.h>
-#include <image.h>
-#include <init.h>
-#include <log.h>
-#include <net.h>
-#include <pci.h>
-#include <asm/processor.h>
-#include <asm/mmu.h>
-#include <asm/cache.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_pci.h>
-#include <fsl_ddr_sdram.h>
-#include <asm/io.h>
-#include <asm/fsl_serdes.h>
-#include <miiphy.h>
-#include <linux/delay.h>
-#include <linux/libfdt.h>
-#include <fdt_support.h>
-#include <tsec.h>
-#include <fsl_mdio.h>
-#include <netdev.h>
-
-#include "../common/sgmii_riser.h"
-
-int checkboard (void)
-{
- u8 vboot;
- u8 *pixis_base = (u8 *)PIXIS_BASE;
-
- printf("Board: MPC8572DS Sys ID: 0x%02x, "
- "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
- in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
- in_8(pixis_base + PIXIS_PVER));
-
- vboot = in_8(pixis_base + PIXIS_VBOOT);
- switch ((vboot & PIXIS_VBOOT_LBMAP) >> 6) {
- case PIXIS_VBOOT_LBMAP_NOR0:
- puts ("vBank: 0\n");
- break;
- case PIXIS_VBOOT_LBMAP_PJET:
- puts ("Promjet\n");
- break;
- case PIXIS_VBOOT_LBMAP_NAND:
- puts ("NAND\n");
- break;
- case PIXIS_VBOOT_LBMAP_NOR1:
- puts ("vBank: 1\n");
- break;
- }
-
- return 0;
-}
-
-
-#if !defined(CONFIG_SPD_EEPROM)
-/*
- * Fixed sdram init -- doesn't use serial presence detect.
- */
-
-phys_size_t fixed_sdram (void)
-{
- volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
- struct ccsr_ddr __iomem *ddr = &immap->im_ddr;
- uint d_init;
-
- ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
- ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
-
- ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
- ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
- ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
- ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
- ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
- ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
- ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
- ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
- ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
- ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
-
-#if defined (CONFIG_DDR_ECC)
- ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN;
- ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS;
- ddr->err_sbe = CONFIG_SYS_DDR_SBE;
-#endif
- asm("sync;isync");
-
- udelay(500);
-
- ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
-
-#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
- d_init = 1;
- debug("DDR - 1st controller: memory initializing\n");
- /*
- * Poll until memory is initialized.
- * 512 Meg at 400 might hit this 200 times or so.
- */
- while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) {
- udelay(1000);
- }
- debug("DDR: memory initialized\n\n");
- asm("sync; isync");
- udelay(500);
-#endif
-
- return 512 * 1024 * 1024;
-}
-
-#endif
-
-#ifdef CONFIG_PCI
-void pci_init_board(void)
-{
- struct pci_controller *hose;
-
- fsl_pcie_init_board(0);
-
- hose = find_hose_by_cfg_addr((void *)(CONFIG_SYS_PCIE3_ADDR));
-
- if (hose) {
- u32 temp32;
- u8 uli_busno = hose->first_busno + 2;
-
- /*
- * Activate ULI1575 legacy chip by performing a fake
- * memory access. Needed to make ULI RTC work.
- * Device 1d has the first on-board memory BAR.
- */
- pci_hose_read_config_dword(hose, PCI_BDF(uli_busno, 0x1d, 0),
- PCI_BASE_ADDRESS_1, &temp32);
-
- if (temp32 >= CONFIG_SYS_PCIE3_MEM_BUS) {
- void *p = pci_mem_to_virt(PCI_BDF(uli_busno, 0x1d, 0),
- temp32, 4, 0);
- debug(" uli1572 read to %p\n", p);
- in_be32(p);
- }
- }
-}
-#endif
-
-int board_early_init_r(void)
-{
- const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
- int flash_esel = find_tlb_idx((void *)flashbase, 1);
-
- /*
- * Remap Boot flash + PROMJET region to caching-inhibited
- * so that flash can be erased properly.
- */
-
- /* Flush d-cache and invalidate i-cache of any FLASH data */
- flush_dcache();
- invalidate_icache();
-
- if (flash_esel == -1) {
- /* very unlikely unless something is messed up */
- puts("Error: Could not find TLB for FLASH BASE\n");
- flash_esel = 2; /* give our best effort to continue */
- } else {
- /* invalidate existing TLB entry for flash + promjet */
- disable_tlb(flash_esel);
- }
-
- set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
- 0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */
-
- return 0;
-}
-
-int board_eth_init(struct bd_info *bis)
-{
-#ifdef CONFIG_TSEC_ENET
- struct fsl_pq_mdio_info mdio_info;
- struct tsec_info_struct tsec_info[4];
- int num = 0;
-
-#ifdef CONFIG_TSEC1
- SET_STD_TSEC_INFO(tsec_info[num], 1);
- if (is_serdes_configured(SGMII_TSEC1)) {
- puts("eTSEC1 is in sgmii mode.\n");
- tsec_info[num].flags |= TSEC_SGMII;
- }
- num++;
-#endif
-#ifdef CONFIG_TSEC2
- SET_STD_TSEC_INFO(tsec_info[num], 2);
- if (is_serdes_configured(SGMII_TSEC2)) {
- puts("eTSEC2 is in sgmii mode.\n");
- tsec_info[num].flags |= TSEC_SGMII;
- }
- num++;
-#endif
-#ifdef CONFIG_TSEC3
- SET_STD_TSEC_INFO(tsec_info[num], 3);
- if (is_serdes_configured(SGMII_TSEC3)) {
- puts("eTSEC3 is in sgmii mode.\n");
- tsec_info[num].flags |= TSEC_SGMII;
- }
- num++;
-#endif
-#ifdef CONFIG_TSEC4
- SET_STD_TSEC_INFO(tsec_info[num], 4);
- if (is_serdes_configured(SGMII_TSEC4)) {
- puts("eTSEC4 is in sgmii mode.\n");
- tsec_info[num].flags |= TSEC_SGMII;
- }
- num++;
-#endif
-
- if (!num) {
- printf("No TSECs initialized\n");
-
- return 0;
- }
-
-#ifdef CONFIG_FSL_SGMII_RISER
- fsl_sgmii_riser_init(tsec_info, num);
-#endif
-
- mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
- mdio_info.name = DEFAULT_MII_NAME;
- fsl_pq_mdio_init(bis, &mdio_info);
-
- tsec_eth_init(bis, tsec_info, num);
-#endif
-
- return pci_eth_init(bis);
-}
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-int ft_board_setup(void *blob, struct bd_info *bd)
-{
- phys_addr_t base;
- phys_size_t size;
-
- ft_cpu_setup(blob, bd);
-
- base = env_get_bootm_low();
- size = env_get_bootm_size();
-
- fdt_fixup_memory(blob, (u64)base, (u64)size);
-
- FT_FSL_PCI_SETUP;
-
-#ifdef CONFIG_FSL_SGMII_RISER
- fsl_sgmii_riser_fdt_fixup(blob);
-#endif
-
- return 0;
-}
-#endif
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2008-2010 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- */
-
-#include <common.h>
-#include <asm/mmu.h>
-
-struct fsl_e_tlb_entry tlb_table[] = {
- /* TLB 0 - for temp stack in cache */
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
-
- /* TLB 1 */
- /* *I*** - Covers boot page */
- SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 0, BOOKE_PAGESZ_4K, 1),
-
- /* *I*G* - CCSRBAR */
- SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 1, BOOKE_PAGESZ_1M, 1),
-
- /* W**G* - Flash/promjet, localbus */
- /* This will be changed to *I*G* after relocation to RAM. */
- SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
- MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
- 0, 2, BOOKE_PAGESZ_256M, 1),
-
-#ifndef CONFIG_NAND_SPL
- /* *I*G* - PCI */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 3, BOOKE_PAGESZ_1G, 1),
-
- /* *I*G* - PCI */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x40000000, CONFIG_SYS_PCIE3_MEM_PHYS + 0x40000000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 4, BOOKE_PAGESZ_256M, 1),
-
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x50000000, CONFIG_SYS_PCIE3_MEM_PHYS + 0x50000000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 5, BOOKE_PAGESZ_256M, 1),
-
- /* *I*G* - PCI I/O */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_VIRT, CONFIG_SYS_PCIE3_IO_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 6, BOOKE_PAGESZ_256K, 1),
-#endif
-
- /* *I*G - NAND */
- SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 7, BOOKE_PAGESZ_1M, 1),
-
- SET_TLB_ENTRY(1, PIXIS_BASE, PIXIS_BASE_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 8, BOOKE_PAGESZ_4K, 1),
-
-#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
- /* *I*G - L2SRAM */
- SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR,
- CONFIG_SYS_INIT_L2_ADDR_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 9, BOOKE_PAGESZ_256K, 1),
- SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000,
- CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 10, BOOKE_PAGESZ_256K, 1),
-#endif
-};
-
-int num_tlb_entries = ARRAY_SIZE(tlb_table);
+++ /dev/null
-if TARGET_MPC8610HPCD
-
-config SYS_BOARD
- default "mpc8610hpcd"
-
-config SYS_VENDOR
- default "freescale"
-
-config SYS_CONFIG_NAME
- default "MPC8610HPCD"
-
-endif
+++ /dev/null
-MPC8610HPCD BOARD
-M: Priyanka Jain <priyanka.jain@nxp.com>
-S: Maintained
-F: board/freescale/mpc8610hpcd/
-F: include/configs/MPC8610HPCD.h
-F: configs/MPC8610HPCD_defconfig
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0+
-# Copyright 2007 Freescale Semiconductor, Inc.
-
-obj-y += mpc8610hpcd.o
-obj-$(CONFIG_SYS_FSL_DDR2) += ddr.o
-obj-y += law.o
-obj-$(CONFIG_FSL_DIU_FB) += mpc8610hpcd_diu.o
+++ /dev/null
-Freescale MPC8610HPCD board
-===========================
-
-
-Building U-Boot
----------------
-
- $ make MPC8610HPCD_config
- Configuring for MPC8610HPCD board...
-
- $ make
-
-
-Flashing U-Boot
----------------
-The flash is 128M starting at 0xF800_0000.
-
-The alternate image is at 0xFBF0_0000
-The boot image is at 0xFFF0_0000.
-
-
-To Flash U-Boot into the booting bank:
-
- tftp 1000000 u-boot.bin
- protect off all
- erase fff00000 +$filesize
- cp.b 1000000 fff00000 $filesize
-
-
-To Flash U-Boot into the alternate bank
-
- tftp 1000000 u-boot.bin
- erase fbf00000 +$filesize
- cp.b 1000000 fbf00000 $filesize
-
-
-pixis_reset command
--------------------
-A new command, "pixis_reset", is introduced to reset mpc8610hpcd board
-using the FPGA sequencer. When the board restarts, it has the option
-of using either the current or alternate flash bank as the boot
-image, with or without the watchdog timer enabled, and finally with
-or without frequency changes.
-
-Usage is;
-
- pixis_reset
- pixis_reset altbank
- pixis_reset altbank wd
- pixis_reset altbank cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
- pixis_reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
-
-Examples;
-
- /* reset to current bank, like "reset" command */
- pixis_reset
-
- /* reset board but use the to alternate flash bank */
- pixis_reset altbank
-
- /* reset board, use alternate flash bank with watchdog timer enabled*/
- pixis_reset altbank wd
-
- /* reset board to alternate bank with frequency changed.
- * 40 is SYSCLK, 2.5 is COREPLL ratio, 10 is MPXPLL ratio
- */
- pixis-reset altbank cf 40 2.5 10
-
-
-DIP Switch Settings
--------------------
-To manually switch the flash banks using the DIP switch
-settings, toggle both SW6:1 and SW6:2.
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright 2008 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-
-void fsl_ddr_board_options(memctl_options_t *popts,
- dimm_params_t *pdimm,
- unsigned int ctrl_num)
-{
- /*
- * Factors to consider for clock adjust:
- * - number of chips on bus
- * - position of slot
- * - DDR1 vs. DDR2?
- * - ???
- *
- * This needs to be determined on a board-by-board basis.
- * 0110 3/4 cycle late
- * 0111 7/8 cycle late
- */
- popts->clk_adjust = 7;
-
- /*
- * Factors to consider for CPO:
- * - frequency
- * - ddr1 vs. ddr2
- */
- popts->cpo_override = 10;
-
- /*
- * Factors to consider for write data delay:
- * - number of DIMMs
- *
- * 1 = 1/4 clock delay
- * 2 = 1/2 clock delay
- * 3 = 3/4 clock delay
- * 4 = 1 clock delay
- * 5 = 5/4 clock delay
- * 6 = 3/2 clock delay
- */
- popts->write_data_delay = 3;
-
- /* 2T timing enable */
- popts->twot_en = 1;
-
- /*
- * Factors to consider for half-strength driver enable:
- * - number of DIMMs installed
- */
- popts->half_strength_driver_enable = 0;
-}
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2008,2010 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- */
-
-#include <common.h>
-#include <asm/fsl_law.h>
-#include <asm/mmu.h>
-
-struct law_entry law_table[] = {
-#if !defined(CONFIG_SPD_EEPROM)
- SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR_1),
-#endif
- SET_LAW(PIXIS_BASE, LAW_SIZE_2M, LAW_TRGT_IF_LBC),
- SET_LAW(CONFIG_SYS_FLASH_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
-};
-
-int num_law_entries = ARRAY_SIZE(law_table);
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2007,2009-2011 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <command.h>
-#include <init.h>
-#include <log.h>
-#include <net.h>
-#include <pci.h>
-#include <asm/processor.h>
-#include <asm/immap_86xx.h>
-#include <asm/fsl_pci.h>
-#include <fsl_ddr_sdram.h>
-#include <asm/fsl_serdes.h>
-#include <i2c.h>
-#include <asm/io.h>
-#include <linux/delay.h>
-#include <linux/libfdt.h>
-#include <fdt_support.h>
-#include <spd_sdram.h>
-#include <netdev.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void sdram_init(void);
-phys_size_t fixed_sdram(void);
-int mpc8610hpcd_diu_init(void);
-
-
-/* called before any console output */
-int board_early_init_f(void)
-{
- volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
- volatile ccsr_gur_t *gur = &immap->im_gur;
-
- gur->gpiocr |= 0x88aa5500; /* DIU16, IR1, UART0, UART2 */
-
- return 0;
-}
-
-int misc_init_r(void)
-{
- u8 tmp_val, version;
- u8 *pixis_base = (u8 *)PIXIS_BASE;
-
- /*Do not use 8259PIC*/
- tmp_val = in_8(pixis_base + PIXIS_BRDCFG0);
- out_8(pixis_base + PIXIS_BRDCFG0, tmp_val | 0x80);
-
- /*For FPGA V7 or higher, set the IRQMAPSEL to 0 to use MAP0 interrupt*/
- version = in_8(pixis_base + PIXIS_PVER);
- if(version >= 0x07) {
- tmp_val = in_8(pixis_base + PIXIS_BRDCFG0);
- out_8(pixis_base + PIXIS_BRDCFG0, tmp_val & 0xbf);
- }
-
- /* Using this for DIU init before the driver in linux takes over
- * Enable the TFP410 Encoder (I2C address 0x38)
- */
-
- tmp_val = 0xBF;
- i2c_write(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
- /* Verify if enabled */
- tmp_val = 0;
- i2c_read(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
- debug("DVI Encoder Read: 0x%02x\n", tmp_val);
-
- tmp_val = 0x10;
- i2c_write(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
- /* Verify if enabled */
- tmp_val = 0;
- i2c_read(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
- debug("DVI Encoder Read: 0x%02x\n", tmp_val);
-
- return 0;
-}
-
-int checkboard(void)
-{
- volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
- volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm;
- u8 *pixis_base = (u8 *)PIXIS_BASE;
-
- printf ("Board: MPC8610HPCD, Sys ID: 0x%02x, "
- "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
- in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
- in_8(pixis_base + PIXIS_PVER));
-
- /*
- * The MPC8610 HPCD workbook says that LBMAP=11 is the "normal" boot
- * bank and LBMAP=00 is the alternate bank. However, the pixis
- * altbank code can only set bits, not clear them, so we treat 00 as
- * the normal bank and 11 as the alternate.
- */
- switch (in_8(pixis_base + PIXIS_VBOOT) & 0xC0) {
- case 0:
- puts("vBank: Standard\n");
- break;
- case 0x40:
- puts("Promjet\n");
- break;
- case 0x80:
- puts("NAND\n");
- break;
- case 0xC0:
- puts("vBank: Alternate\n");
- break;
- }
-
- mcm->abcr |= 0x00010000; /* 0 */
- mcm->hpmr3 = 0x80000008; /* 4c */
- mcm->hpmr0 = 0;
- mcm->hpmr1 = 0;
- mcm->hpmr2 = 0;
- mcm->hpmr4 = 0;
- mcm->hpmr5 = 0;
-
- return 0;
-}
-
-
-int dram_init(void)
-{
- phys_size_t dram_size = 0;
-
-#if defined(CONFIG_SPD_EEPROM)
- dram_size = fsl_ddr_sdram();
-#else
- dram_size = fixed_sdram();
-#endif
-
- setup_ddr_bat(dram_size);
-
- debug(" DDR: ");
- gd->ram_size = dram_size;
-
- return 0;
-}
-
-
-#if !defined(CONFIG_SPD_EEPROM)
-/*
- * Fixed sdram init -- doesn't use serial presence detect.
- */
-
-phys_size_t fixed_sdram(void)
-{
-#if !defined(CONFIG_SYS_RAMBOOT)
- volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
- struct ccsr_ddr __iomem *ddr = &immap->im_ddr1;
- uint d_init;
-
- ddr->cs0_bnds = 0x0000001f;
- ddr->cs0_config = 0x80010202;
-
- ddr->timing_cfg_3 = 0x00000000;
- ddr->timing_cfg_0 = 0x00260802;
- ddr->timing_cfg_1 = 0x3935d322;
- ddr->timing_cfg_2 = 0x14904cc8;
- ddr->sdram_mode = 0x00480432;
- ddr->sdram_mode_2 = 0x00000000;
- ddr->sdram_interval = 0x06180fff; /* 0x06180100; */
- ddr->sdram_data_init = 0xDEADBEEF;
- ddr->sdram_clk_cntl = 0x03800000;
- ddr->sdram_cfg_2 = 0x04400010;
-
-#if defined(CONFIG_DDR_ECC)
- ddr->err_int_en = 0x0000000d;
- ddr->err_disable = 0x00000000;
- ddr->err_sbe = 0x00010000;
-#endif
- asm("sync;isync");
-
- udelay(500);
-
- ddr->sdram_cfg = 0xc3000000; /* 0xe3008000;*/
-
-
-#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
- d_init = 1;
- debug("DDR - 1st controller: memory initializing\n");
- /*
- * Poll until memory is initialized.
- * 512 Meg at 400 might hit this 200 times or so.
- */
- while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0)
- udelay(1000);
-
- debug("DDR: memory initialized\n\n");
- asm("sync; isync");
- udelay(500);
-#endif
-
- return 512 * 1024 * 1024;
-#endif
- return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
-}
-
-#endif
-
-#if defined(CONFIG_PCI)
-/*
- * Initialize PCI Devices, report devices found.
- */
-
-#ifndef CONFIG_PCI_PNP
-static struct pci_config_table pci_fsl86xxads_config_table[] = {
- {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
- PCI_IDSEL_NUMBER, PCI_ANY_ID,
- pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
- PCI_ENET0_MEMADDR,
- PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER} },
- {}
-};
-#endif
-
-
-static struct pci_controller pci1_hose;
-#endif /* CONFIG_PCI */
-
-void pci_init_board(void)
-{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR;
- volatile ccsr_gur_t *gur = &immap->im_gur;
- struct fsl_pci_info pci_info;
- u32 devdisr;
- int first_free_busno;
- int pci_agent;
-
- devdisr = in_be32(&gur->devdisr);
-
- first_free_busno = fsl_pcie_init_board(0);
-
-#ifdef CONFIG_PCI1
- if (!(devdisr & MPC86xx_DEVDISR_PCI1)) {
- SET_STD_PCI_INFO(pci_info, 1);
- set_next_law(pci_info.mem_phys,
- law_size_bits(pci_info.mem_size), pci_info.law);
- set_next_law(pci_info.io_phys,
- law_size_bits(pci_info.io_size), pci_info.law);
-
- pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs);
- printf("PCI: connected to PCI slots as %s" \
- " (base address %lx)\n",
- pci_agent ? "Agent" : "Host",
- pci_info.regs);
-#ifndef CONFIG_PCI_PNP
- pci1_hose.config_table = pci_mpc86xxcts_config_table;
-#endif
- first_free_busno = fsl_pci_init_port(&pci_info,
- &pci1_hose, first_free_busno);
- } else {
- printf("PCI: disabled\n");
- }
-
- puts("\n");
-#else
- setbits_be32(&gur->devdisr, MPC86xx_DEVDISR_PCI1); /* disable */
-#endif
-
- fsl_pcie_init_board(first_free_busno);
-}
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-int ft_board_setup(void *blob, struct bd_info *bd)
-{
- ft_cpu_setup(blob, bd);
-
- FT_FSL_PCI_SETUP;
-
- return 0;
-}
-#endif
-
-/*
- * get_board_sys_clk
- * Reads the FPGA on board for CONFIG_SYS_CLK_FREQ
- */
-
-unsigned long
-get_board_sys_clk(ulong dummy)
-{
- u8 i;
- ulong val = 0;
- u8 *pixis_base = (u8 *)PIXIS_BASE;
-
- i = in_8(pixis_base + PIXIS_SPD);
- i &= 0x07;
-
- switch (i) {
- case 0:
- val = 33333000;
- break;
- case 1:
- val = 39999600;
- break;
- case 2:
- val = 49999500;
- break;
- case 3:
- val = 66666000;
- break;
- case 4:
- val = 83332500;
- break;
- case 5:
- val = 99999000;
- break;
- case 6:
- val = 133332000;
- break;
- case 7:
- val = 166665000;
- break;
- }
-
- return val;
-}
-
-int board_eth_init(struct bd_info *bis)
-{
- return pci_eth_init(bis);
-}
-
-void board_reset(void)
-{
- u8 *pixis_base = (u8 *)PIXIS_BASE;
-
- out_8(pixis_base + PIXIS_RST, 0);
-
- while (1)
- ;
-}
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2007-2011 Freescale Semiconductor, Inc.
- * Authors: York Sun <yorksun@freescale.com>
- * Timur Tabi <timur@freescale.com>
- *
- * FSL DIU Framebuffer driver
- */
-
-#include <common.h>
-#include <clock_legacy.h>
-#include <command.h>
-#include <log.h>
-#include <asm/io.h>
-#include <fsl_diu_fb.h>
-#include "../common/pixis.h"
-
-#define PX_BRDCFG0_DLINK 0x10
-#define PX_BRDCFG0_DVISEL 0x08
-
-void diu_set_pixel_clock(unsigned int pixclock)
-{
- volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
- volatile ccsr_gur_t *gur = &immap->im_gur;
- volatile unsigned int *guts_clkdvdr = &gur->clkdvdr;
- unsigned long speed_ccb, temp, pixval;
-
- speed_ccb = get_bus_freq(0);
- temp = 1000000000/pixclock;
- temp *= 1000;
- pixval = speed_ccb / temp;
- debug("DIU pixval = %lu\n", pixval);
-
- /* Modify PXCLK in GUTS CLKDVDR */
- debug("DIU: Current value of CLKDVDR = 0x%08x\n", *guts_clkdvdr);
- temp = *guts_clkdvdr & 0x2000FFFF;
- *guts_clkdvdr = temp; /* turn off clock */
- *guts_clkdvdr = temp | 0x80000000 | ((pixval & 0x1F) << 16);
- debug("DIU: Modified value of CLKDVDR = 0x%08x\n", *guts_clkdvdr);
-}
-
-int platform_diu_init(unsigned int xres, unsigned int yres, const char *port)
-{
- const char *name;
- int gamma_fix = 0;
- u32 pixel_format = 0x88883316;
- u8 temp;
-
- temp = in_8(&pixis->brdcfg0);
-
- if (strncmp(port, "dlvds", 5) == 0) {
- /* Dual link LVDS */
- gamma_fix = 1;
- temp &= ~(PX_BRDCFG0_DLINK | PX_BRDCFG0_DVISEL);
- name = "Dual-Link LVDS";
- } else if (strncmp(port, "lvds", 4) == 0) {
- /* Single link LVDS */
- temp = (temp & ~PX_BRDCFG0_DVISEL) | PX_BRDCFG0_DLINK;
- name = "Single-Link LVDS";
- } else {
- /* DVI */
- if (in_8(&pixis->ver) == 1) /* Board version */
- pixel_format = 0x88882317;
- temp |= PX_BRDCFG0_DVISEL;
- name = "DVI";
- }
-
- printf("DIU: Switching to %s monitor @ %ux%u\n", name, xres, yres);
- out_8(&pixis->brdcfg0, temp);
-
- return fsl_diu_init(xres, yres, pixel_format, gamma_fix);
-}
+++ /dev/null
-if TARGET_MPC8641HPCN
-
-config SYS_BOARD
- default "mpc8641hpcn"
-
-config SYS_VENDOR
- default "freescale"
-
-config SYS_CONFIG_NAME
- default "MPC8641HPCN"
-
-endif
+++ /dev/null
-MPC8641HPCN BOARD
-M: Priyanka Jain <priyanka.jain@nxp.com>
-S: Maintained
-F: board/freescale/mpc8641hpcn/
-F: include/configs/MPC8641HPCN.h
-F: configs/MPC8641HPCN_defconfig
-F: configs/MPC8641HPCN_36BIT_defconfig
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2001
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-
-obj-y += mpc8641hpcn.o
-obj-y += law.o
-obj-$(CONFIG_SYS_FSL_DDR2) += ddr.o
+++ /dev/null
-Freescale MPC8641HPCN board
-===========================
-
-Created 05/24/2006 Haiying Wang
--------------------------------
-
-1. Building U-Boot
-------------------
-The 86xx HPCN code base is known to compile using:
- Binutils 2.15, Gcc 3.4.3, Glibc 2.3.3
-
- $ make MPC8641HPCN_config
- Configuring for MPC8641HPCN board...
-
- $ make
-
-
-2. Switch and Jumper Setting
-----------------------------
-Jumpers:
- J14 Pins 1-2 (near plcc32 socket)
-
-Switches:
- SW1(1-5) = 01100 CONFIG_SYS_COREPLL = 01000 :: CORE = 2:1
- 01100 :: CORE = 2.5:1
- 10000 :: CORE = 3:1
- 11100 :: CORE = 3.5:1
- 10100 :: CORE = 4:1
- 01110 :: CORE = 4.5:1
- SW1(6-8) = 001 CONFIG_SYS_SYSCLK = 000 :: SYSCLK = 33MHz
- 001 :: SYSCLK = 40MHz
-
- SW2(1-4) = 1100 CONFIG_SYS_CCBPLL = 0010 :: 2X
- 0100 :: 4X
- 0110 :: 6X
- 1000 :: 8X
- 1010 :: 10X
- 1100 :: 12X
- 1110 :: 14X
- 0000 :: 16X
- SW2(5-8) = 1110 CONFIG_SYS_BOOTLOC = 1110 :: boot 16-bit localbus
-
- SW3(1-7) = 0011000 CONFIG_SYS_VID = 0011000 :: VCORE = 1.2V
- 0100000 :: VCORE = 1.11V
- SW3(8) = 0 VCC_PLAT = 0 :: VCC_PLAT = 1.2V
- 1 :: VCC_PLAT = 1.0V
-
- SW4(1-2) = 11 CONFIG_SYS_HOSTMODE = 11 :: both prots host/root
- SW4(3-4) = 11 CONFIG_SYS_BOOTSEQ = 11 :: no boot seq
- SW4(5-8) = 0011 CONFIG_SYS_IOPORT = 0011 :: both PEX
-
- SW5(1) = 1 CONFIG_SYS_FLASHMAP = 1 :: boot from flash
- 0 :: boot from PromJet
- SW5(2) = 1 CONFIG_SYS_FLASHBANK = 1 :: swap upper/lower
- halves (virtual banks)
- 0 :: normal
- SW5(3) = 0 CONFIG_SYS_FLASHWP = 0 :: not protected
- SW5(4) = 0 CONFIG_SYS_PORTDIV = 1 :: 2:1 for PD4
- 1:1 for PD6
- SW5(5-6) = 11 CONFIG_SYS_PIXISOPT = 11 :: s/w determined
- SW5(7-8) = 11 CONFIG_SYS_LADOPT = 11 :: s/w determined
-
- SW6(1) = 1 CONFIG_SYS_CPUBOOT = 1 :: no boot holdoff
- SW6(2) = 1 CONFIG_SYS_BOOTADDR = 1 :: no traslation
- SW6(3-5) = 000 CONFIG_SYS_REFCLKSEL = 000 :: 100MHZ
- SW6(6) = 1 CONFIG_SYS_SERROM_ADDR= 1 ::
- SW6(7) = 1 CONFIG_SYS_MEMDEBUG = 1 ::
- SW6(8) = 1 CONFIG_SYS_DDRDEBUG = 1 ::
-
- SW8(1) = 1 ACZ_SYNC = 1 :: 48MHz on TP49
- SW8(2) = 1 ACB_SYNC = 1 :: THRMTRIP disabled
- SW8(3) = 1 ACZ_SDOUT = 1 :: p4 mode
- SW8(4) = 1 ACB_SDOUT = 1 :: PATA freq. = 133MHz
- SW8(5) = 0 SUSLED = 0 :: SouthBridge Mode
- SW8(6) = 0 SPREAD = 0 :: REFCLK SSCG Disabled
- SW8(7) = 1 ACPWR = 1 :: non-battery
- SW8(8) = 0 CONFIG_SYS_IDWP = 0 :: write enable
-
-
-3. Flash U-Boot
----------------
-The flash range 0xEF800000 to 0xEFFFFFFF can be divided into 2 halves.
-It is possible to use either half to boot using U-Boot. Switch 5 bit 2
-is used for this purpose.
-
-0xEF800000 to 0xEFBFFFFF - 4MB
-0xEFC00000 to 0xEFFFFFFF - 4MB
-When this bit is 0, U-Boot is at 0xEFF00000.
-When this bit is 1, U-Boot is at 0xEFB00000.
-
-Use the above mentioned flash commands to program the other half, and
-use switch 5, bit 2 to alternate between the halves. Note: The booting
-version of U-Boot will always be at 0xEFF00000.
-
-To Flash U-Boot into the booting bank (0xEFC00000 - 0xEFFFFFFF):
-
- tftp 1000000 u-boot.bin
- protect off all
- erase eff00000 +$filesize
- cp.b 1000000 eff00000 $filesize
-
-or use tftpflash command:
- run tftpflash
-
-To Flash U-Boot into the alternative bank (0xEF800000 - 0xEFBFFFFF):
-
- tftp 1000000 u-boot.bin
- erase efb00000 +$filesize
- cp.b 1000000 efb00000 $filesize
-
-
-4. Memory Map
--------------
-NOTE: RIO and PCI are mutually exclusive, so they share an address
-
-For 32-bit U-Boot, devices are mapped so that the virtual address ==
-the physical address, and the map looks liks this:
-
- Memory Range Device Size
- ------------ ------ ----
- 0x0000_0000 0x7fff_ffff DDR 2G
- 0x8000_0000 0x9fff_ffff RIO MEM 512M
- 0x8000_0000 0x9fff_ffff PCI1/PEX1 MEM 512M
- 0xa000_0000 0xbfff_ffff PCI2/PEX2 MEM 512M
- 0xffe0_0000 0xffef_ffff CCSR 1M
- 0xffdf_0000 0xffdf_7fff PIXIS 8K
- 0xffdf_8000 0xffdf_ffff CF 8K
- 0xf840_0000 0xf840_3fff Stack space 32K
- 0xffc0_0000 0xffc0_ffff PCI1/PEX1 IO 64K
- 0xffc1_0000 0xffc1_ffff PCI2/PEX2 IO 64K
- 0xef80_0000 0xefff_ffff Flash 8M
-
-For 36-bit-enabled U-Boot, the virtual map is the same as for 32-bit.
-However, the physical map is altered to reside in 36-bit space, as follows.
-Addresses are no longer mapped with VA == PA. All accesses from
-software use the VA; the PA is only used for setting up windows
-and mappings. Note that with the exception of PCI MEM and RIO, the low
- 32 bits are the same as the VA above; only the top 4 bits vary:
-
- Memory Range Device Size
- ------------ ------ ----
- 0x0_0000_0000 0x0_7fff_ffff DDR 2G
- 0xc_0000_0000 0xc_1fff_ffff RIO MEM 512M
- 0xc_0000_0000 0xc_1fff_ffff PCI1/PEX1 MEM 512M
- 0xc_2000_0000 0xc_3fff_ffff PCI2/PEX2 MEM 512M
- 0xf_ffe0_0000 0xf_ffef_ffff CCSR 1M
- 0xf_ffdf_0000 0xf_ffdf_7fff PIXIS 8K
- 0xf_ffdf_8000 0xf_ffdf_ffff CF 8K
- 0x0_f840_0000 0xf_f840_3fff Stack space 32K
- 0xf_ffc0_0000 0xf_ffc0_ffff PCI1/PEX1 IO 64K
- 0xf_ffc1_0000 0xf_ffc1_ffff PCI2/PEX2 IO 64K
- 0xf_ef80_0000 0xf_efff_ffff Flash 8M
-
-5. pixis_reset command
---------------------
-A new command, "pixis_reset", is introduced to reset mpc8641hpcn board
-using the FPGA sequencer. When the board restarts, it has the option
-of using either the current or alternate flash bank as the boot
-image, with or without the watchdog timer enabled, and finally with
-or without frequency changes.
-
-Usage is;
-
- pixis_reset
- pixis_reset altbank
- pixis_reset altbank wd
- pixis_reset altbank cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
- pixis_reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
-
-Examples;
-
- /* reset to current bank, like "reset" command */
- pixis_reset
-
- /* reset board but use the to alternate flash bank */
- pixis_reset altbank
-
- /* reset board, use alternate flash bank with watchdog timer enabled*/
- pixis_reset altbank wd
-
- /* reset board to alternate bank with frequency changed.
- * 40 is SYSCLK, 2.5 is COREPLL ratio, 10 is MPXPLL ratio
- */
- pixis-reset altbank cf 40 2.5 10
-
-Valid clock choices are in the 8641 Reference Manuals.
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright 2008,2011 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-
-struct board_specific_parameters {
- u32 n_ranks;
- u32 datarate_mhz_high;
- u32 clk_adjust;
- u32 cpo;
- u32 write_data_delay;
-};
-
-/*
- * This table contains all valid speeds we want to override with board
- * specific parameters. datarate_mhz_high values need to be in ascending order
- * for each n_ranks group.
- */
-const struct board_specific_parameters dimm0[] = {
- /*
- * memory controller 0
- * num| hi| clk| cpo|wrdata|2T
- * ranks| mhz|adjst| | delay|
- */
- {4, 333, 7, 7, 3},
- {4, 549, 7, 9, 3},
- {4, 650, 7, 10, 4},
- {2, 333, 7, 7, 3},
- {2, 549, 7, 9, 3},
- {2, 650, 7, 10, 4},
- {1, 333, 7, 7, 3},
- {1, 549, 7, 9, 3},
- {1, 650, 7, 10, 4},
- {}
-};
-
-/*
- * The two slots have slightly different timing. The center values are good
- * for both slots. We use identical speed tables for them. In future use, if
- * DIMMs have fewer center values that require two separated tables, copy the
- * udimm0 table to udimm1 and make changes to clk_adjust and wrlvl_start.
- */
-const struct board_specific_parameters *dimms[] = {
- dimm0,
- dimm0,
-};
-
-void fsl_ddr_board_options(memctl_options_t *popts,
- dimm_params_t *pdimm,
- unsigned int ctrl_num)
-{
- const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
- unsigned int i;
- ulong ddr_freq;
-
- if (ctrl_num > 1) {
- printf("Wrong parameter for controller number %d", ctrl_num);
- return;
- }
- for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
- if (pdimm[i].n_ranks)
- break;
- }
- if (i >= CONFIG_DIMM_SLOTS_PER_CTLR) /* no DIMM */
- return;
-
- pbsp = dimms[ctrl_num];
-
- /* Get clk_adjust, cpo, write_data_delay, according to the board ddr
- * freqency and n_banks specified in board_specific_parameters table.
- */
- ddr_freq = get_ddr_freq(0) / 1000000;
- while (pbsp->datarate_mhz_high) {
- if (pbsp->n_ranks == pdimm[i].n_ranks) {
- if (ddr_freq <= pbsp->datarate_mhz_high) {
- popts->clk_adjust = pbsp->clk_adjust;
- popts->cpo_override = pbsp->cpo;
- popts->write_data_delay =
- pbsp->write_data_delay;
- goto found;
- }
- pbsp_highest = pbsp;
- }
- pbsp++;
- }
-
- if (pbsp_highest) {
- printf("Error: board specific timing not found "
- "for data rate %lu MT/s!\n"
- "Trying to use the highest speed (%u) parameters\n",
- ddr_freq, pbsp_highest->datarate_mhz_high);
- popts->clk_adjust = pbsp_highest->clk_adjust;
- popts->cpo_override = pbsp_highest->cpo;
- popts->write_data_delay = pbsp_highest->write_data_delay;
- } else {
- panic("DIMM is not supported by this board");
- }
-
-found:
- /* 2T timing enable */
- popts->twot_en = 1;
-}
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2008,2010-2011 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- */
-
-#include <common.h>
-#include <asm/fsl_law.h>
-#include <asm/mmu.h>
-
-/*
- * LAW(Local Access Window) configuration:
- *
- * 0x0000_0000 0x7fff_ffff DDR 2G
- * if PCI (prepend 0xc_0000_0000 if CONFIG_PHYS_64BIT)
- * 0x8000_0000 0x9fff_ffff PCIE1 MEM 512M
- * 0xa000_0000 0xbfff_ffff PCIE2 MEM 512M
- * else if RIO (prepend 0xc_0000_0000 if CONFIG_PHYS_64BIT)
- * 0x8000_0000 0x9fff_ffff RapidIO 512M
- * endif
- * (prepend 0xf_0000_0000 if CONFIG_PHYS_64BIT)
- * 0xffc0_0000 0xffc0_ffff PCIE1 IO 64K
- * 0xffc1_0000 0xffc1_ffff PCIE2 IO 64K
- * 0xffe0_0000 0xffef_ffff CCSRBAR 1M
- * 0xffdf_0000 0xffe0_0000 PIXIS, CF 64K
- * 0xef80_0000 0xefff_ffff FLASH (boot bank) 8M
- *
- * Notes:
- * CCSRBAR doesn't need a configured Local Access Window.
- * If flash is 8M at default position (last 8M), no LAW needed.
- */
-
-struct law_entry law_table[] = {
-#if !defined(CONFIG_SPD_EEPROM)
- SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR_1),
-#endif
- SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_LBC),
- SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_LBC),
-};
-
-int num_law_entries = ARRAY_SIZE(law_table);
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2006, 2007, 2010-2011 Freescale Semiconductor.
- */
-
-#include <common.h>
-#include <init.h>
-#include <log.h>
-#include <net.h>
-#include <pci.h>
-#include <asm/processor.h>
-#include <asm/immap_86xx.h>
-#include <asm/fsl_pci.h>
-#include <fsl_ddr_sdram.h>
-#include <asm/fsl_serdes.h>
-#include <asm/io.h>
-#include <linux/delay.h>
-#include <linux/libfdt.h>
-#include <fdt_support.h>
-#include <netdev.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-phys_size_t fixed_sdram(void);
-
-int checkboard(void)
-{
- u8 vboot;
- u8 *pixis_base = (u8 *)PIXIS_BASE;
-
- printf ("Board: MPC8641HPCN, Sys ID: 0x%02x, "
- "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
- in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
- in_8(pixis_base + PIXIS_PVER));
-
- vboot = in_8(pixis_base + PIXIS_VBOOT);
- if (vboot & PIXIS_VBOOT_FMAP)
- printf ("vBank: %d\n", ((vboot & PIXIS_VBOOT_FBANK) >> 6));
- else
- puts ("Promjet\n");
-
- return 0;
-}
-
-int dram_init(void)
-{
- phys_size_t dram_size = 0;
-
-#if defined(CONFIG_SPD_EEPROM)
- dram_size = fsl_ddr_sdram();
-#else
- dram_size = fixed_sdram();
-#endif
-
- setup_ddr_bat(dram_size);
-
- debug(" DDR: ");
- gd->ram_size = dram_size;
-
- return 0;
-}
-
-
-#if !defined(CONFIG_SPD_EEPROM)
-/*
- * Fixed sdram init -- doesn't use serial presence detect.
- */
-phys_size_t
-fixed_sdram(void)
-{
-#if !defined(CONFIG_SYS_RAMBOOT)
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- struct ccsr_ddr __iomem *ddr = &immap->im_ddr1;
-
- ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
- ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
- ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
- ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
- ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
- ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
- ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
- ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
- ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
- ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
- ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
- ddr->sdram_ocd_cntl = CONFIG_SYS_DDR_OCD_CTRL;
- ddr->sdram_ocd_status = CONFIG_SYS_DDR_OCD_STATUS;
-
-#if defined (CONFIG_DDR_ECC)
- ddr->err_disable = 0x0000008D;
- ddr->err_sbe = 0x00ff0000;
-#endif
- asm("sync;isync");
-
- udelay(500);
-
-#if defined (CONFIG_DDR_ECC)
- /* Enable ECC checking */
- ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000);
-#else
- ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
- ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
-#endif
- asm("sync; isync");
-
- udelay(500);
-#endif
- return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
-}
-#endif /* !defined(CONFIG_SPD_EEPROM) */
-
-void pci_init_board(void)
-{
- fsl_pcie_init_board(0);
-
-#ifdef CONFIG_PCIE1
- /*
- * Activate ULI1575 legacy chip by performing a fake
- * memory access. Needed to make ULI RTC work.
- */
- in_be32((unsigned *) ((char *)(CONFIG_SYS_PCIE1_MEM_VIRT
- + CONFIG_SYS_PCIE1_MEM_SIZE - 0x1000000)));
-#endif /* CONFIG_PCIE1 */
-}
-
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-int ft_board_setup(void *blob, struct bd_info *bd)
-{
- int off;
- u64 *tmp;
- int addrcells;
-
- ft_cpu_setup(blob, bd);
-
- FT_FSL_PCI_SETUP;
-
- /*
- * Warn if it looks like the device tree doesn't match u-boot.
- * This is just an estimation, based on the location of CCSR,
- * which is defined by the "reg" property in the soc node.
- */
- off = fdt_path_offset(blob, "/soc8641");
- addrcells = fdt_address_cells(blob, 0);
- tmp = (u64 *)fdt_getprop(blob, off, "reg", NULL);
-
- if (tmp) {
- u64 addr;
-
- if (addrcells == 1)
- addr = *(u32 *)tmp;
- else
- addr = *tmp;
-
- if (addr != CONFIG_SYS_CCSRBAR_PHYS)
- printf("WARNING: The CCSRBAR address in your .dts "
- "does not match the address of the CCSR "
- "in u-boot. This means your .dts might "
- "be old.\n");
- }
-
- return 0;
-}
-#endif
-
-
-/*
- * get_board_sys_clk
- * Reads the FPGA on board for CONFIG_SYS_CLK_FREQ
- */
-
-unsigned long
-get_board_sys_clk(ulong dummy)
-{
- u8 i, go_bit, rd_clks;
- ulong val = 0;
- u8 *pixis_base = (u8 *)PIXIS_BASE;
-
- go_bit = in_8(pixis_base + PIXIS_VCTL);
- go_bit &= 0x01;
-
- rd_clks = in_8(pixis_base + PIXIS_VCFGEN0);
- rd_clks &= 0x1C;
-
- /*
- * Only if both go bit and the SCLK bit in VCFGEN0 are set
- * should we be using the AUX register. Remember, we also set the
- * GO bit to boot from the alternate bank on the on-board flash
- */
-
- if (go_bit) {
- if (rd_clks == 0x1c)
- i = in_8(pixis_base + PIXIS_AUX);
- else
- i = in_8(pixis_base + PIXIS_SPD);
- } else {
- i = in_8(pixis_base + PIXIS_SPD);
- }
-
- i &= 0x07;
-
- switch (i) {
- case 0:
- val = 33000000;
- break;
- case 1:
- val = 40000000;
- break;
- case 2:
- val = 50000000;
- break;
- case 3:
- val = 66000000;
- break;
- case 4:
- val = 83000000;
- break;
- case 5:
- val = 100000000;
- break;
- case 6:
- val = 134000000;
- break;
- case 7:
- val = 166000000;
- break;
- }
-
- return val;
-}
-
-int board_eth_init(struct bd_info *bis)
-{
- /* Initialize TSECs */
- cpu_eth_init(bis);
- return pci_eth_init(bis);
-}
-
-void board_reset(void)
-{
- u8 *pixis_base = (u8 *)PIXIS_BASE;
-
- out_8(pixis_base + PIXIS_RST, 0);
-
- while (1)
- ;
-}
+++ /dev/null
-if TARGET_MX35PDK
-
-config SYS_BOARD
- default "mx35pdk"
-
-config SYS_VENDOR
- default "freescale"
-
-config SYS_SOC
- default "mx35"
-
-config SYS_CONFIG_NAME
- default "mx35pdk"
-
-endif
+++ /dev/null
-MX35PDK BOARD
-M: Stefano Babic <sbabic@denx.de>
-S: Maintained
-F: board/freescale/mx35pdk/
-F: include/configs/mx35pdk.h
-F: configs/mx35pdk_defconfig
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
-#
-# (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
-
-obj-y := mx35pdk.o
-obj-y += lowlevel_init.o
+++ /dev/null
-Overview
---------------
-
-mx35pdk (known als as mx35_3stack) is a development board by Freescale.
-It consists of three pluggable board:
- - CPU module, with CPU, RAM, flash
- - Personality board, with most interfaces (USB, Network,..)
- - Debug board with JTAG header.
-
-The board is usually delivered with redboot. This howto explains how to boot
-a linux kernel and how to replace the original bootloader with U-Boot.
-
-The board is delivered with Redboot on the NAND flash. It is possible to
-switch the boot device with the switches SW1-SW2 on the Personality board,
-and with SW5-SW10 on the Debug board.
-
-Delivered Redboot script to start the kernel
----------------------------------------------------
-
-In redboot the following script is stored:
-
-fis load kernel
-exec -c "noinitrd console=ttymxc0,115200 root=/dev/mtdblock8 rw rootfstype=jffs2 ip=dhcp fec_mac=00:04:9F:00:E7:76"
-
-Kernel is taken from flash. The image is in zImage format.
-
-Booting from NET, rootfs on NFS:
------------------------------------
-
-To change the script in redboot:
-
-load -r -b 0x100000 <path_to_zImage>
-exec -c "noinitrd console=ttymxc0,115200 root=/dev/nfsroot rootfstype=nfsroot nfsroot=192.168.1.1:/opt/eldk-4.2-arm/armVFP rw ip=dhcp"
-
-If the ip address is not set, you can set it with :
-
-ip_address -l <board_ip/netmask> -h <server_ip>
-
-Linux partitions:
----------------------------
-
-As default, the board is shipped with these partition tables for NAND
-and for NOR:
-
-Creating 5 MTD partitions on "NAND 2GiB 3,3V 8-bit":
-0x00000000-0x00100000 : "nand.bootloader"
-0x00100000-0x00600000 : "nand.kernel"
-0x00600000-0x06600000 : "nand.rootfs"
-0x06600000-0x06e00000 : "nand.configure"
-0x06e00000-0x80000000 : "nand.userfs"
-
-Creating 6 MTD partitions on "mxc_nor_flash.0":
-0x00000000-0x00080000 : "Bootloader"
-0x00080000-0x00480000 : "nor.Kernel"
-0x00480000-0x02280000 : "nor.userfs"
-0x02280000-0x03e80000 : "nor.rootfs"
-0x01fe0000-0x01fe3000 : "FIS directory"
-0x01fff000-0x04000000 : "Redboot config"
-
-NAND partitions can be recognized enabling in kernel CONFIG_MTD_REDBOOT_PARTS.
-For this board, CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK should be set to 2.
-
-However, the setup in redboot is not correct and does not use the whole flash.
-
-Better solution is to use the kernel parameter mtdparts.
-Here the resulting script to be defined in RedBoot with fconfig:
-
-load -r -b 0x100000 sbabic/mx35pdk/zImage.2.6.37
-exec -c "noinitrd console=ttymxc0,115200 root=/dev/nfsroot rootfstype=nfsroot nfsroot=192.168.1.1:/opt/eldk-4.2-arm/arm rw ip=dhcp mtdparts=mxc_nand:1m(boot),5m(linux),96m(root),8m(cfg),1938m(user);physmap-flash.0:512k(b),4m(k),30m(u),28m(r)"
-
-Flashing U-Boot
---------------------------------
-
-U-Boot should be stored on the NOR flash.
-
-The boot storage can be select using the switches on the personality board
-(SW1-SW2) and on the DEBUG board (SW4-SW10).
-
-If something goes wrong flashing the bootloader, it is always possible to
-recover the board booting from the other device.
-
-Saving U-Boot in the NOR flash
----------------------------------
-
-Check the partition for boot in the NOR flash. Setting the mtdparts as reported,
-the boot partition should be /dev/mtd0.
-
-Creating 6 MTD partitions on "mxc_nor_flash.0":
-0x00000000-0x00080000 : "Bootloader"
-0x00080000-0x00480000 : "nor.Kernel"
-0x00480000-0x02280000 : "nor.userfs"
-0x02280000-0x03e80000 : "nor.rootfs"
-0x01fe0000-0x01fe3000 : "FIS directory"
-0x01fff000-0x04000000 : "Redboot config"
-
-To erase the whole partition:
-$ flash_eraseall /dev/mtd0
-
-Writing U-Boot:
-dd if=u-boot.bin of=/dev/mtd0
-
-To boot from NOR, you have to select the switches as follows:
-
-Personality board
- SW2 all off
- SW1 all off
-
-Debug Board:
- SW5 0
- SW6 0
- SW7 0
- SW8 1
- SW9 1
- SW10 0
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
- *
- * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
- */
-
-#include <config.h>
-#include <asm/arch/imx-regs.h>
-#include <generated/asm-offsets.h>
-#include "mx35pdk.h"
-#include <asm/arch/lowlevel_macro.S>
-
-/*
- * return soc version
- * 0x10: TO1
- * 0x20: TO2
- * 0x30: TO3
- */
-.macro check_soc_version ret, tmp
- ldr \tmp, =IIM_BASE_ADDR
- ldr \ret, [\tmp, #IIM_SREV]
- cmp \ret, #0x00
- moveq \tmp, #ROMPATCH_REV
- ldreq \ret, [\tmp]
- moveq \ret, \ret, lsl #4
- addne \ret, \ret, #0x10
-.endm
-
-/* CPLD on CS5 setup */
-.macro init_debug_board
- ldr r0, =DBG_BASE_ADDR
- ldr r1, =DBG_CSCR_U_CONFIG
- str r1, [r0, #0x00]
- ldr r1, =DBG_CSCR_L_CONFIG
- str r1, [r0, #0x04]
- ldr r1, =DBG_CSCR_A_CONFIG
- str r1, [r0, #0x08]
-.endm
-
-/* clock setup */
-.macro init_clock
- ldr r0, =CCM_BASE_ADDR
-
- /* default CLKO to 1/32 of the ARM core*/
- ldr r1, [r0, #CLKCTL_COSR]
- bic r1, r1, #0x00000FF00
- bic r1, r1, #0x0000000FF
- mov r2, #0x00006C00
- add r2, r2, #0x67
- orr r1, r1, r2
- str r1, [r0, #CLKCTL_COSR]
-
- ldr r2, =CCM_CCMR_CONFIG
- str r2, [r0, #CLKCTL_CCMR]
-
- check_soc_version r1, r2
- cmp r1, #CHIP_REV_2_0
- ldrhs r3, =CCM_MPLL_532_HZ
- bhs 1f
- ldr r2, [r0, #CLKCTL_PDR0]
- tst r2, #CLKMODE_CONSUMER
- ldrne r3, =CCM_MPLL_532_HZ /* consumer path*/
- ldreq r3, =CCM_MPLL_399_HZ /* auto path*/
-1:
- str r3, [r0, #CLKCTL_MPCTL]
-
- ldr r1, =CCM_PPLL_300_HZ
- str r1, [r0, #CLKCTL_PPCTL]
-
- ldr r1, =CCM_PDR0_CONFIG
- bic r1, r1, #0x800000
- str r1, [r0, #CLKCTL_PDR0]
-
- ldr r1, [r0, #CLKCTL_CGR0]
- orr r1, r1, #0x0C300000
- str r1, [r0, #CLKCTL_CGR0]
-
- ldr r1, [r0, #CLKCTL_CGR1]
- orr r1, r1, #0x00000C00
- orr r1, r1, #0x00000003
- str r1, [r0, #CLKCTL_CGR1]
-
- ldr r1, [r0, #CLKCTL_CGR2]
- orr r1, r1, #0x00C00000
- str r1, [r0, #CLKCTL_CGR2]
-.endm
-
-.macro setup_sdram
- ldr r0, =ESDCTL_BASE_ADDR
- mov r3, #0x2000
- str r3, [r0, #0x0]
- str r3, [r0, #0x8]
-
- /*ip(r12) has used to save lr register in upper calling*/
- mov fp, lr
-
- mov r5, #0x00
- mov r2, #0x00
- mov r1, #CSD0_BASE_ADDR
- bl setup_sdram_bank
-
- mov r5, #0x00
- mov r2, #0x00
- mov r1, #CSD1_BASE_ADDR
- bl setup_sdram_bank
-
- mov lr, fp
-
-1:
- ldr r3, =ESDCTL_DELAY_LINE5
- str r3, [r0, #0x30]
-.endm
-
-.globl lowlevel_init
-lowlevel_init:
- mov r10, lr
-
- core_init
-
- init_aips
-
- init_max
-
- init_m3if
-
- init_clock
- init_debug_board
-
- cmp pc, #PHYS_SDRAM_1
- blo init_sdram_start
- cmp pc, #(PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)
- blo skip_sdram_setup
-
-init_sdram_start:
- /*init_sdram*/
- setup_sdram
-
-skip_sdram_setup:
- mov lr, r10
- mov pc, lr
-
-
-/*
- * r0: ESDCTL control base, r1: sdram slot base
- * r2: DDR type(0:DDR2, 1:MDDR) r3, r4:working base
- */
-setup_sdram_bank:
- mov r3, #0xE
- tst r2, #0x1
- orreq r3, r3, #0x300 /*DDR2*/
- str r3, [r0, #0x10]
- bic r3, r3, #0x00A
- str r3, [r0, #0x10]
- beq 2f
-
- mov r3, #0x20000
-1: subs r3, r3, #1
- bne 1b
-
-2: tst r2, #0x1
- ldreq r3, =ESDCTL_DDR2_CONFIG
- ldrne r3, =ESDCTL_MDDR_CONFIG
- cmp r1, #CSD1_BASE_ADDR
- strlo r3, [r0, #0x4]
- strhs r3, [r0, #0xC]
-
- ldr r3, =ESDCTL_0x92220000
- strlo r3, [r0, #0x0]
- strhs r3, [r0, #0x8]
- mov r3, #0xDA
- ldr r4, =ESDCTL_PRECHARGE
- strb r3, [r1, r4]
-
- tst r2, #0x1
- bne skip_set_mode
-
- cmp r1, #CSD1_BASE_ADDR
- ldr r3, =ESDCTL_0xB2220000
- strlo r3, [r0, #0x0]
- strhs r3, [r0, #0x8]
- mov r3, #0xDA
- ldr r4, =ESDCTL_DDR2_EMR2
- strb r3, [r1, r4]
- ldr r4, =ESDCTL_DDR2_EMR3
- strb r3, [r1, r4]
- ldr r4, =ESDCTL_DDR2_EN_DLL
- strb r3, [r1, r4]
- ldr r4, =ESDCTL_DDR2_RESET_DLL
- strb r3, [r1, r4]
-
- ldr r3, =ESDCTL_0x92220000
- strlo r3, [r0, #0x0]
- strhs r3, [r0, #0x8]
- mov r3, #0xDA
- ldr r4, =ESDCTL_PRECHARGE
- strb r3, [r1, r4]
-
-skip_set_mode:
- cmp r1, #CSD1_BASE_ADDR
- ldr r3, =ESDCTL_0xA2220000
- strlo r3, [r0, #0x0]
- strhs r3, [r0, #0x8]
- mov r3, #0xDA
- strb r3, [r1]
- strb r3, [r1]
-
- ldr r3, =ESDCTL_0xB2220000
- strlo r3, [r0, #0x0]
- strhs r3, [r0, #0x8]
- tst r2, #0x1
- ldreq r4, =ESDCTL_DDR2_MR
- ldrne r4, =ESDCTL_MDDR_MR
- mov r3, #0xDA
- strb r3, [r1, r4]
- ldreq r4, =ESDCTL_DDR2_OCD_DEFAULT
- streqb r3, [r1, r4]
- ldreq r4, =ESDCTL_DDR2_EN_DLL
- ldrne r4, =ESDCTL_MDDR_EMR
- strb r3, [r1, r4]
-
- cmp r1, #CSD1_BASE_ADDR
- ldr r3, =ESDCTL_0x82228080
- strlo r3, [r0, #0x0]
- strhs r3, [r0, #0x8]
-
- tst r2, #0x1
- moveq r4, #0x20000
- movne r4, #0x200
-1: subs r4, r4, #1
- bne 1b
-
- str r3, [r1, #0x100]
- ldr r4, [r1, #0x100]
- cmp r3, r4
- movne r3, #1
- moveq r3, #0
-
- mov pc, lr
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
- *
- * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <init.h>
-#include <net.h>
-#include <asm/io.h>
-#include <linux/delay.h>
-#include <linux/errno.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/crm_regs.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/iomux-mx35.h>
-#include <i2c.h>
-#include <power/pmic.h>
-#include <fsl_pmic.h>
-#include <mmc.h>
-#include <fsl_esdhc_imx.h>
-#include <mc9sdz60.h>
-#include <mc13892.h>
-#include <linux/types.h>
-#include <asm/gpio.h>
-#include <asm/arch/sys_proto.h>
-#include <netdev.h>
-#include <asm/mach-types.h>
-
-#ifndef CONFIG_BOARD_LATE_INIT
-#error "CONFIG_BOARD_LATE_INIT must be set for this board"
-#endif
-
-#ifndef CONFIG_BOARD_EARLY_INIT_F
-#error "CONFIG_BOARD_EARLY_INIT_F must be set for this board"
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int dram_init(void)
-{
- u32 size1, size2;
-
- size1 = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
- size2 = get_ram_size((void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
-
- gd->ram_size = size1 + size2;
-
- return 0;
-}
-
-int dram_init_banksize(void)
-{
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-
- gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
- gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
-
- return 0;
-}
-
-#define I2C_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_ODE)
-
-static void setup_iomux_i2c(void)
-{
- static const iomux_v3_cfg_t i2c1_pads[] = {
- NEW_PAD_CTRL(MX35_PAD_I2C1_CLK__I2C1_SCL, I2C_PAD_CTRL),
- NEW_PAD_CTRL(MX35_PAD_I2C1_DAT__I2C1_SDA, I2C_PAD_CTRL),
- };
-
- /* setup pins for I2C1 */
- imx_iomux_v3_setup_multiple_pads(i2c1_pads, ARRAY_SIZE(i2c1_pads));
-}
-
-
-static void setup_iomux_spi(void)
-{
- static const iomux_v3_cfg_t spi_pads[] = {
- MX35_PAD_CSPI1_MOSI__CSPI1_MOSI,
- MX35_PAD_CSPI1_MISO__CSPI1_MISO,
- MX35_PAD_CSPI1_SS0__CSPI1_SS0,
- MX35_PAD_CSPI1_SS1__CSPI1_SS1,
- MX35_PAD_CSPI1_SCLK__CSPI1_SCLK,
- };
-
- imx_iomux_v3_setup_multiple_pads(spi_pads, ARRAY_SIZE(spi_pads));
-}
-
-#define USBOTG_IN_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | \
- PAD_CTL_DSE_LOW | PAD_CTL_SRE_SLOW)
-#define USBOTG_OUT_PAD_CTRL (PAD_CTL_DSE_LOW | PAD_CTL_SRE_SLOW)
-
-static void setup_iomux_usbotg(void)
-{
- static const iomux_v3_cfg_t usbotg_pads[] = {
- NEW_PAD_CTRL(MX35_PAD_USBOTG_PWR__USB_TOP_USBOTG_PWR,
- USBOTG_OUT_PAD_CTRL),
- NEW_PAD_CTRL(MX35_PAD_USBOTG_OC__USB_TOP_USBOTG_OC,
- USBOTG_IN_PAD_CTRL),
- };
-
- /* Set up pins for USBOTG. */
- imx_iomux_v3_setup_multiple_pads(usbotg_pads, ARRAY_SIZE(usbotg_pads));
-}
-
-#define FEC_PAD_CTRL (PAD_CTL_DSE_LOW | PAD_CTL_SRE_SLOW)
-
-static void setup_iomux_fec(void)
-{
- static const iomux_v3_cfg_t fec_pads[] = {
- NEW_PAD_CTRL(MX35_PAD_FEC_TX_CLK__FEC_TX_CLK, FEC_PAD_CTRL |
- PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
- NEW_PAD_CTRL(MX35_PAD_FEC_RX_CLK__FEC_RX_CLK, FEC_PAD_CTRL |
- PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
- NEW_PAD_CTRL(MX35_PAD_FEC_RX_DV__FEC_RX_DV, FEC_PAD_CTRL |
- PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
- NEW_PAD_CTRL(MX35_PAD_FEC_COL__FEC_COL, FEC_PAD_CTRL |
- PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
- NEW_PAD_CTRL(MX35_PAD_FEC_RDATA0__FEC_RDATA_0, FEC_PAD_CTRL |
- PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
- NEW_PAD_CTRL(MX35_PAD_FEC_TDATA0__FEC_TDATA_0, FEC_PAD_CTRL),
- NEW_PAD_CTRL(MX35_PAD_FEC_TX_EN__FEC_TX_EN, FEC_PAD_CTRL),
- NEW_PAD_CTRL(MX35_PAD_FEC_MDC__FEC_MDC, FEC_PAD_CTRL),
- NEW_PAD_CTRL(MX35_PAD_FEC_MDIO__FEC_MDIO, FEC_PAD_CTRL |
- PAD_CTL_HYS | PAD_CTL_PUS_22K_UP),
- NEW_PAD_CTRL(MX35_PAD_FEC_TX_ERR__FEC_TX_ERR, FEC_PAD_CTRL),
- NEW_PAD_CTRL(MX35_PAD_FEC_RX_ERR__FEC_RX_ERR, FEC_PAD_CTRL |
- PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
- NEW_PAD_CTRL(MX35_PAD_FEC_CRS__FEC_CRS, FEC_PAD_CTRL |
- PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
- NEW_PAD_CTRL(MX35_PAD_FEC_RDATA1__FEC_RDATA_1, FEC_PAD_CTRL |
- PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
- NEW_PAD_CTRL(MX35_PAD_FEC_TDATA1__FEC_TDATA_1, FEC_PAD_CTRL),
- NEW_PAD_CTRL(MX35_PAD_FEC_RDATA2__FEC_RDATA_2, FEC_PAD_CTRL |
- PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
- NEW_PAD_CTRL(MX35_PAD_FEC_TDATA2__FEC_TDATA_2, FEC_PAD_CTRL),
- NEW_PAD_CTRL(MX35_PAD_FEC_RDATA3__FEC_RDATA_3, FEC_PAD_CTRL |
- PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
- NEW_PAD_CTRL(MX35_PAD_FEC_TDATA3__FEC_TDATA_3, FEC_PAD_CTRL),
- };
-
- /* setup pins for FEC */
- imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
-}
-
-int board_early_init_f(void)
-{
- struct ccm_regs *ccm =
- (struct ccm_regs *)IMX_CCM_BASE;
-
- /* enable clocks */
- writel(readl(&ccm->cgr0) |
- MXC_CCM_CGR0_EMI_MASK |
- MXC_CCM_CGR0_EDIO_MASK |
- MXC_CCM_CGR0_EPIT1_MASK,
- &ccm->cgr0);
-
- writel(readl(&ccm->cgr1) |
- MXC_CCM_CGR1_FEC_MASK |
- MXC_CCM_CGR1_GPIO1_MASK |
- MXC_CCM_CGR1_GPIO2_MASK |
- MXC_CCM_CGR1_GPIO3_MASK |
- MXC_CCM_CGR1_I2C1_MASK |
- MXC_CCM_CGR1_I2C2_MASK |
- MXC_CCM_CGR1_IPU_MASK,
- &ccm->cgr1);
-
- /* Setup NAND */
- __raw_writel(readl(&ccm->rcsr) | MXC_CCM_RCSR_NFC_FMS, &ccm->rcsr);
-
- setup_iomux_i2c();
- setup_iomux_usbotg();
- setup_iomux_fec();
- setup_iomux_spi();
-
- return 0;
-}
-
-int board_init(void)
-{
- gd->bd->bi_arch_number = MACH_TYPE_MX35_3DS; /* board id for linux */
- /* address of boot parameters */
- gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
-
- return 0;
-}
-
-static inline int pmic_detect(void)
-{
- unsigned int id;
- struct pmic *p = pmic_get("FSL_PMIC");
- if (!p)
- return -ENODEV;
-
- pmic_reg_read(p, REG_IDENTIFICATION, &id);
-
- id = (id >> 6) & 0x7;
- if (id == 0x7)
- return 1;
- return 0;
-}
-
-u32 get_board_rev(void)
-{
- int rev;
-
- rev = pmic_detect();
-
- return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
-}
-
-int board_late_init(void)
-{
- u8 val;
- u32 pmic_val;
- struct pmic *p;
- int ret;
-
- ret = pmic_init(I2C_0);
- if (ret)
- return ret;
-
- if (pmic_detect()) {
- p = pmic_get("FSL_PMIC");
- imx_iomux_v3_setup_pad(MX35_PAD_WDOG_RST__WDOG_WDOG_B);
-
- pmic_reg_read(p, REG_SETTING_0, &pmic_val);
- pmic_reg_write(p, REG_SETTING_0,
- pmic_val | VO_1_30V | VO_1_50V);
- pmic_reg_read(p, REG_MODE_0, &pmic_val);
- pmic_reg_write(p, REG_MODE_0, pmic_val | VGEN3EN);
-
- imx_iomux_v3_setup_pad(MX35_PAD_COMPARE__GPIO1_5);
-
- gpio_direction_output(IMX_GPIO_NR(1, 5), 1);
- }
-
- val = mc9sdz60_reg_read(MC9SDZ60_REG_GPIO_1) | 0x04;
- mc9sdz60_reg_write(MC9SDZ60_REG_GPIO_1, val);
- mdelay(200);
-
- val = mc9sdz60_reg_read(MC9SDZ60_REG_RESET_1) & 0x7F;
- mc9sdz60_reg_write(MC9SDZ60_REG_RESET_1, val);
- mdelay(200);
-
- val |= 0x80;
- mc9sdz60_reg_write(MC9SDZ60_REG_RESET_1, val);
-
- /* Print board revision */
- printf("Board: MX35 PDK %d.0\n", ((get_board_rev() >> 8) + 1) & 0x0F);
-
- return 0;
-}
-
-int board_eth_init(struct bd_info *bis)
-{
-#if defined(CONFIG_SMC911X)
- int rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
- if (rc)
- return rc;
-#endif
- return cpu_eth_init(bis);
-}
-
-#if defined(CONFIG_FSL_ESDHC_IMX)
-
-struct fsl_esdhc_cfg esdhc_cfg = {MMC_SDHC1_BASE_ADDR};
-
-int board_mmc_init(struct bd_info *bis)
-{
- static const iomux_v3_cfg_t sdhc1_pads[] = {
- MX35_PAD_SD1_CMD__ESDHC1_CMD,
- MX35_PAD_SD1_CLK__ESDHC1_CLK,
- MX35_PAD_SD1_DATA0__ESDHC1_DAT0,
- MX35_PAD_SD1_DATA1__ESDHC1_DAT1,
- MX35_PAD_SD1_DATA2__ESDHC1_DAT2,
- MX35_PAD_SD1_DATA3__ESDHC1_DAT3,
- };
-
- /* configure pins for SDHC1 only */
- imx_iomux_v3_setup_multiple_pads(sdhc1_pads, ARRAY_SIZE(sdhc1_pads));
-
- esdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK);
- return fsl_esdhc_initialize(bis, &esdhc_cfg);
-}
-
-int board_mmc_getcd(struct mmc *mmc)
-{
- return !(mc9sdz60_reg_read(MC9SDZ60_REG_DES_FLAG) & 0x4);
-}
-#endif
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- *
- * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
- *
- * (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
- */
-
-#ifndef __BOARD_MX35_3STACK_H
-#define __BOARD_MX35_3STACK_H
-
-#define DBG_BASE_ADDR WEIM_CTRL_CS5
-#define DBG_CSCR_U_CONFIG 0x0000D843
-#define DBG_CSCR_L_CONFIG 0x22252521
-#define DBG_CSCR_A_CONFIG 0x22220A00
-
-#define CCM_CCMR_CONFIG 0x003F4208
-#define CCM_PDR0_CONFIG 0x00801000
-
-/* MEMORY SETTING */
-#define ESDCTL_0x92220000 0x92220000
-#define ESDCTL_0xA2220000 0xA2220000
-#define ESDCTL_0xB2220000 0xB2220000
-#define ESDCTL_0x82228080 0x82228080
-
-#define ESDCTL_PRECHARGE 0x00000400
-
-#define ESDCTL_MDDR_CONFIG 0x007FFC3F
-#define ESDCTL_MDDR_MR 0x00000033
-#define ESDCTL_MDDR_EMR 0x02000000
-
-#define ESDCTL_DDR2_CONFIG 0x007FFC3F
-#define ESDCTL_DDR2_EMR2 0x04000000
-#define ESDCTL_DDR2_EMR3 0x06000000
-#define ESDCTL_DDR2_EN_DLL 0x02000400
-#define ESDCTL_DDR2_RESET_DLL 0x00000333
-#define ESDCTL_DDR2_MR 0x00000233
-#define ESDCTL_DDR2_OCD_DEFAULT 0x02000780
-
-#define ESDCTL_DELAY_LINE5 0x00F49F00
-#endif /* __BOARD_MX35_3STACK_H */
+++ /dev/null
-if TARGET_MIGOR
-
-config SYS_BOARD
- default "MigoR"
-
-config SYS_VENDOR
- default "renesas"
-
-config SYS_CONFIG_NAME
- default "MigoR"
-
-endif
+++ /dev/null
-MIGOR BOARD
-#M: -
-S: Maintained
-F: board/renesas/MigoR/
-F: include/configs/MigoR.h
-F: configs/MigoR_defconfig
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (C) 2007
-# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
-#
-# Copyright (C) 2007
-# Kenati Technologies, Inc.
-#
-# board/MigoR/Makefile
-#
-
-obj-y := migo_r.o
-extra-y += lowlevel_init.o
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2007-2008
- * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
- *
- * Copyright (C) 2007
- * Kenati Technologies, Inc.
- *
- * board/MigoR/lowlevel_init.S
- */
-
-#include <config.h>
-
-#include <asm/processor.h>
-#include <asm/macro.h>
-
-/*
- * Board specific low level init code, called _very_ early in the
- * startup sequence. Relocation to SDRAM has not happened yet, no
- * stack is available, bss section has not been initialised, etc.
- *
- * (Note: As no stack is available, no subroutines can be called...).
- */
-
- .global lowlevel_init
-
- .text
- .align 2
-
-lowlevel_init:
- write32 CCR_A, CCR_D ! Address of Cache Control Register
- ! Instruction Cache Invalidate
-
- write32 MMUCR_A, MMUCR_D ! Address of MMU Control Register
- ! TI == TLB Invalidate bit
-
- write32 MSTPCR0_A, MSTPCR0_D ! Address of Power Control Register 0
-
- write32 MSTPCR2_A, MSTPCR2_D ! Address of Power Control Register 2
-
- write16 PFC_PULCR_A, PFC_PULCR_D
-
- write16 PFC_DRVCR_A, PFC_DRVCR_D
-
- write16 SBSCR_A, SBSCR_D
-
- write16 PSCR_A, PSCR_D
-
- write16 RWTCSR_A, RWTCSR_D_1 ! 0xA4520004 (Watchdog Control / Status Register)
- ! 0xA507 -> timer_STOP / WDT_CLK = max
-
- write16 RWTCNT_A, RWTCNT_D ! 0xA4520000 (Watchdog Count Register)
- ! 0x5A00 -> Clear
-
- write16 RWTCSR_A, RWTCSR_D_2 ! 0xA4520004 (Watchdog Control / Status Register)
- ! 0xA504 -> timer_STOP / CLK = 500ms
-
- write32 DLLFRQ_A, DLLFRQ_D ! 20080115
- ! 20080115
-
- write32 FRQCR_A, FRQCR_D ! 0xA4150000 Frequency control register
- ! 20080115
-
- write32 CCR_A, CCR_D_2 ! Address of Cache Control Register
- ! ??
-
-bsc_init:
- write32 CMNCR_A, CMNCR_D
-
- write32 CS0BCR_A, CS0BCR_D
-
- write32 CS4BCR_A, CS4BCR_D
-
- write32 CS5ABCR_A, CS5ABCR_D
-
- write32 CS5BBCR_A, CS5BBCR_D
-
- write32 CS6ABCR_A, CS6ABCR_D
-
- write32 CS0WCR_A, CS0WCR_D
-
- write32 CS4WCR_A, CS4WCR_D
-
- write32 CS5AWCR_A, CS5AWCR_D
-
- write32 CS5BWCR_A, CS5BWCR_D
-
- write32 CS6AWCR_A, CS6AWCR_D
-
- ! SDRAM initialization
- write32 SDCR_A, SDCR_D
-
- write32 SDWCR_A, SDWCR_D
-
- write32 SDPCR_A, SDPCR_D
-
- write32 RTCOR_A, RTCOR_D
-
- write32 RTCNT_A, RTCNT_D
-
- write32 RTCSR_A, RTCSR_D
-
- write32 RFCR_A, RFCR_D
-
- write8 SDMR3_A, SDMR3_D
-
- ! BL bit off (init = ON) (?!?)
-
- stc sr, r0 ! BL bit off(init=ON)
- mov.l SR_MASK_D, r1
- and r1, r0
- ldc r0, sr
-
- rts
- mov #0, r0
-
- .align 4
-
-CCR_A: .long CCR
-MMUCR_A: .long MMUCR
-MSTPCR0_A: .long MSTPCR0
-MSTPCR2_A: .long MSTPCR2
-PFC_PULCR_A: .long PULCR
-PFC_DRVCR_A: .long DRVCR
-SBSCR_A: .long SBSCR
-PSCR_A: .long PSCR
-RWTCSR_A: .long RWTCSR
-RWTCNT_A: .long RWTCNT
-FRQCR_A: .long FRQCR
-PLLCR_A: .long PLLCR
-DLLFRQ_A: .long DLLFRQ
-
-CCR_D: .long 0x00000800
-CCR_D_2: .long 0x00000103
-MMUCR_D: .long 0x00000004
-MSTPCR0_D: .long 0x00001001
-MSTPCR2_D: .long 0xffffffff
-PFC_PULCR_D: .long 0x6000
-PFC_DRVCR_D: .long 0x0464
-FRQCR_D: .long 0x07033639
-PLLCR_D: .long 0x00005000
-DLLFRQ_D: .long 0x000004F6
-
-CMNCR_A: .long CMNCR
-CMNCR_D: .long 0x0000001B
-CS0BCR_A: .long CS0BCR
-CS0BCR_D: .long 0x24920400
-CS4BCR_A: .long CS4BCR
-CS4BCR_D: .long 0x00003400
-CS5ABCR_A: .long CS5ABCR
-CS5ABCR_D: .long 0x24920400
-CS5BBCR_A: .long CS5BBCR
-CS5BBCR_D: .long 0x24920400
-CS6ABCR_A: .long CS6ABCR
-CS6ABCR_D: .long 0x24920400
-
-CS0WCR_A: .long CS0WCR
-CS0WCR_D: .long 0x00000380
-CS4WCR_A: .long CS4WCR
-CS4WCR_D: .long 0x00110080
-CS5AWCR_A: .long CS5AWCR
-CS5AWCR_D: .long 0x00000300
-CS5BWCR_A: .long CS5BWCR
-CS5BWCR_D: .long 0x00000300
-CS6AWCR_A: .long CS6AWCR
-CS6AWCR_D: .long 0x00000300
-
-SDCR_A: .long SBSC_SDCR
-SDCR_D: .long 0x80160809
-SDWCR_A: .long SBSC_SDWCR
-SDWCR_D: .long 0x0014450C
-SDPCR_A: .long SBSC_SDPCR
-SDPCR_D: .long 0x00000087
-RTCOR_A: .long SBSC_RTCOR
-RTCNT_A: .long SBSC_RTCNT
-RTCNT_D: .long 0xA55A0012
-RTCOR_D: .long 0xA55A001C
-RTCSR_A: .long SBSC_RTCSR
-RFCR_A: .long SBSC_RFCR
-RFCR_D: .long 0xA55A0221
-RTCSR_D: .long 0xA55A009a
-SDMR3_A: .long 0xFE581180
-SDMR3_D: .long 0x0
-
-SR_MASK_D: .long 0xEFFFFF0F
-
- .align 2
-
-SBSCR_D: .word 0x0044
-PSCR_D: .word 0x0000
-RWTCSR_D_1: .word 0xA507
-RWTCSR_D_2: .word 0xA504
-RWTCNT_D: .word 0x5A00
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2007
- * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
- *
- * Copyright (C) 2007
- * Kenati Technologies, Inc.
- *
- * board/MigoR/migo_r.c
- */
-
-#include <common.h>
-#include <init.h>
-#include <net.h>
-#include <netdev.h>
-#include <asm/io.h>
-#include <asm/processor.h>
-
-int checkboard(void)
-{
- puts("BOARD: Renesas MigoR\n");
- return 0;
-}
-
-int board_init(void)
-{
- return 0;
-}
-
-void led_set_state (unsigned short value)
-{
-}
-
-#ifdef CONFIG_CMD_NET
-int board_eth_init(struct bd_info *bis)
-{
- int rc = 0;
-#ifdef CONFIG_SMC91111
- rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
-#endif
- return rc;
-}
-#endif
+++ /dev/null
-if TARGET_R7780MP
-
-config SYS_BOARD
- default "r7780mp"
-
-config SYS_VENDOR
- default "renesas"
-
-config SYS_CONFIG_NAME
- default "r7780mp"
-
-endif
+++ /dev/null
-R7780MP BOARD
-M: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
-M: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
-S: Maintained
-F: board/renesas/r7780mp/
-F: include/configs/r7780mp.h
-F: configs/r7780mp_defconfig
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (C) 2007,2008 Nobuhiro Iwamatsu
-#
-# board/r7780mp/Makefile
-#
-
-obj-y := r7780mp.o
-extra-y += lowlevel_init.o
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2007,2008 Nobuhiro Iwamatsu
- *
- * u-boot/board/r7780mp/lowlevel_init.S
- */
-
-#include <config.h>
-#include <asm/processor.h>
-#include <asm/macro.h>
-
-/*
- * Board specific low level init code, called _very_ early in the
- * startup sequence. Relocation to SDRAM has not happened yet, no
- * stack is available, bss section has not been initialised, etc.
- *
- * (Note: As no stack is available, no subroutines can be called...).
- */
-
- .global lowlevel_init
-
- .text
- .align 2
-
-lowlevel_init:
-
- write32 CCR_A, CCR_D /* Address of Cache Control Register */
- /* Instruction Cache Invalidate */
-
- write32 FRQCR_A, FRQCR_D /* Frequency control register */
-
- /* pin_multi_setting */
- write32 BBG_PMMR_A, BBG_PMMR_D_PMSR1
-
- write32 BBG_PMSR1_A, BBG_PMSR1_D
-
- write32 BBG_PMMR_A, BBG_PMMR_D_PMSR2
-
- write32 BBG_PMSR2_A, BBG_PMSR2_D
-
- write32 BBG_PMMR_A, BBG_PMMR_D_PMSR3
-
- write32 BBG_PMSR3_A, BBG_PMSR3_D
-
- write32 BBG_PMMR_A, BBG_PMMR_D_PMSR4
-
- write32 BBG_PMSR4_A, BBG_PMSR4_D
-
- write32 BBG_PMMR_A, BBG_PMMR_D_PMSRG
-
- write32 BBG_PMSRG_A, BBG_PMSRG_D
-
- /* cpg_setting */
- write32 FRQCR_A, FRQCR_D
-
- write32 DLLCSR_A, DLLCSR_D
-
- nop
- nop
- nop
- nop
- nop
- nop
- nop
- nop
- nop
- nop
-
- /* wait 200us */
- mov.l REPEAT0_R3, r3
- mov #0, r2
-repeat0:
- add #1, r2
- cmp/hs r3, r2
- bf repeat0
- nop
-
- /* bsc_setting */
- write32 MMSELR_A, MMSELR_D
-
- write32 BCR_A, BCR_D
-
- write32 CS0BCR_A, CS0BCR_D
-
- write32 CS1BCR_A, CS1BCR_D
-
- write32 CS2BCR_A, CS2BCR_D
-
- write32 CS4BCR_A, CS4BCR_D
-
- write32 CS5BCR_A, CS5BCR_D
-
- write32 CS6BCR_A, CS6BCR_D
-
- write32 CS0WCR_A, CS0WCR_D
-
- write32 CS1WCR_A, CS1WCR_D
-
- write32 CS2WCR_A, CS2WCR_D
-
- write32 CS4WCR_A, CS4WCR_D
-
- write32 CS5WCR_A, CS5WCR_D
-
- write32 CS6WCR_A, CS6WCR_D
-
- write32 CS5PCR_A, CS5PCR_D
-
- write32 CS6PCR_A, CS6PCR_D
-
- /* ddr_setting */
- /* wait 200us */
- mov.l REPEAT0_R3, r3
- mov #0, r2
-repeat1:
- add #1, r2
- cmp/hs r3, r2
- bf repeat1
- nop
-
- mov.l MIM_U_A, r0
- mov.l MIM_U_D, r1
- synco
- mov.l r1, @r0
- synco
-
- mov.l MIM_L_A, r0
- mov.l MIM_L_D0, r1
- synco
- mov.l r1, @r0
- synco
-
- mov.l STR_L_A, r0
- mov.l STR_L_D, r1
- synco
- mov.l r1, @r0
- synco
-
- mov.l SDR_L_A, r0
- mov.l SDR_L_D, r1
- synco
- mov.l r1, @r0
- synco
-
- nop
- nop
- nop
- nop
-
- mov.l SCR_L_A, r0
- mov.l SCR_L_D0, r1
- synco
- mov.l r1, @r0
- synco
-
- mov.l SCR_L_A, r0
- mov.l SCR_L_D1, r1
- synco
- mov.l r1, @r0
- synco
-
- nop
- nop
- nop
-
- mov.l EMRS_A, r0
- mov.l EMRS_D, r1
- synco
- mov.l r1, @r0
- synco
-
- nop
- nop
- nop
-
- mov.l MRS1_A, r0
- mov.l MRS1_D, r1
- synco
- mov.l r1, @r0
- synco
-
- nop
- nop
- nop
-
- mov.l SCR_L_A, r0
- mov.l SCR_L_D2, r1
- synco
- mov.l r1, @r0
- synco
-
- nop
- nop
- nop
-
- mov.l SCR_L_A, r0
- mov.l SCR_L_D3, r1
- synco
- mov.l r1, @r0
- synco
-
- nop
- nop
- nop
-
- mov.l SCR_L_A, r0
- mov.l SCR_L_D4, r1
- synco
- mov.l r1, @r0
- synco
-
- nop
- nop
- nop
-
- mov.l MRS2_A, r0
- mov.l MRS2_D, r1
- synco
- mov.l r1, @r0
- synco
-
- nop
- nop
- nop
-
- mov.l SCR_L_A, r0
- mov.l SCR_L_D5, r1
- synco
- mov.l r1, @r0
- synco
-
- /* wait 200us */
- mov.l REPEAT0_R1, r3
- mov #0, r2
-repeat2:
- add #1, r2
- cmp/hs r3, r2
- bf repeat2
-
- synco
-
- mov.l MIM_L_A, r0
- mov.l MIM_L_D1, r1
- synco
- mov.l r1, @r0
- synco
-
- rts
- nop
- .align 4
-
-RWTCSR_D_1: .word 0xA507
-RWTCSR_D_2: .word 0xA507
-RWTCNT_D: .word 0x5A00
- .align 2
-
-BBG_PMMR_A: .long 0xFF800010
-BBG_PMSR1_A: .long 0xFF800014
-BBG_PMSR2_A: .long 0xFF800018
-BBG_PMSR3_A: .long 0xFF80001C
-BBG_PMSR4_A: .long 0xFF800020
-BBG_PMSRG_A: .long 0xFF800024
-
-BBG_PMMR_D_PMSR1: .long 0xffffbffd
-BBG_PMSR1_D: .long 0x00004002
-BBG_PMMR_D_PMSR2: .long 0xfc21a7ff
-BBG_PMSR2_D: .long 0x03de5800
-BBG_PMMR_D_PMSR3: .long 0xfffffff8
-BBG_PMSR3_D: .long 0x00000007
-BBG_PMMR_D_PMSR4: .long 0xdffdfff9
-BBG_PMSR4_D: .long 0x20020006
-BBG_PMMR_D_PMSRG: .long 0xffffffff
-BBG_PMSRG_D: .long 0x00000000
-
-FRQCR_A: .long FRQCR
-DLLCSR_A: .long 0xffc40010
-FRQCR_D: .long 0x40233035
-DLLCSR_D: .long 0x00000000
-
-/* for DDR-SDRAM */
-MIM_U_A: .long MIM_1
-MIM_L_A: .long MIM_2
-SCR_U_A: .long SCR_1
-SCR_L_A: .long SCR_2
-STR_U_A: .long STR_1
-STR_L_A: .long STR_2
-SDR_U_A: .long SDR_1
-SDR_L_A: .long SDR_2
-
-EMRS_A: .long 0xFEC02000
-MRS1_A: .long 0xFEC00B08
-MRS2_A: .long 0xFEC00308
-
-MIM_U_D: .long 0x00004000
-MIM_L_D0: .long 0x03e80009
-MIM_L_D1: .long 0x03e80209
-SCR_L_D0: .long 0x3
-SCR_L_D1: .long 0x2
-SCR_L_D2: .long 0x2
-SCR_L_D3: .long 0x4
-SCR_L_D4: .long 0x4
-SCR_L_D5: .long 0x0
-STR_L_D: .long 0x000f0000
-SDR_L_D: .long 0x00000400
-EMRS_D: .long 0x0
-MRS1_D: .long 0x0
-MRS2_D: .long 0x0
-
-/* Cache Controller */
-CCR_A: .long CCR
-MMUCR_A: .long MMUCR
-RWTCNT_A: .long WTCNT
-
-CCR_D: .long 0x0000090b
-CCR_D_2: .long 0x00000103
-MMUCR_D: .long 0x00000004
-MSTPCR0_D: .long 0x00001001
-MSTPCR2_D: .long 0xffffffff
-
-/* local Bus State Controller */
-MMSELR_A: .long MMSELR
-BCR_A: .long BCR
-CS0BCR_A: .long CS0BCR
-CS1BCR_A: .long CS1BCR
-CS2BCR_A: .long CS2BCR
-CS4BCR_A: .long CS4BCR
-CS5BCR_A: .long CS5BCR
-CS6BCR_A: .long CS6BCR
-CS0WCR_A: .long CS0WCR
-CS1WCR_A: .long CS1WCR
-CS2WCR_A: .long CS2WCR
-CS4WCR_A: .long CS4WCR
-CS5WCR_A: .long CS5WCR
-CS6WCR_A: .long CS6WCR
-CS5PCR_A: .long CS5PCR
-CS6PCR_A: .long CS6PCR
-
-MMSELR_D: .long 0xA5A50003
-BCR_D: .long 0x00000000
-CS0BCR_D: .long 0x77777770
-CS1BCR_D: .long 0x77777670
-CS2BCR_D: .long 0x77777770
-CS4BCR_D: .long 0x77777770
-CS5BCR_D: .long 0x77777670
-CS6BCR_D: .long 0x77777770
-CS0WCR_D: .long 0x00020006
-CS1WCR_D: .long 0x00232304
-CS2WCR_D: .long 0x7777770F
-CS4WCR_D: .long 0x7777770F
-CS5WCR_D: .long 0x00101006
-CS6WCR_D: .long 0x77777703
-CS5PCR_D: .long 0x77000000
-CS6PCR_D: .long 0x77000000
-
-REPEAT0_R3: .long 0x00002000
-REPEAT0_R1: .long 0x0000200
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
- * Copyright (C) 2008 Yusuke Goda <goda.yusuke@renesas.com>
- */
-
-#include <common.h>
-#include <ide.h>
-#include <init.h>
-#include <net.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <asm/pci.h>
-#include <netdev.h>
-#include "r7780mp.h"
-
-int checkboard(void)
-{
-#if defined(CONFIG_R7780MP)
- puts("BOARD: Renesas Solutions R7780MP\n");
-#else
- puts("BOARD: Renesas Solutions R7780RP\n");
-#endif
- return 0;
-}
-
-int board_init(void)
-{
- /* SCIF Enable */
- writew(0x0, PHCR);
-
- return 0;
-}
-
-void led_set_state(unsigned short value)
-{
-
-}
-
-void ide_set_reset(int idereset)
-{
- /* if reset = 1 IDE reset will be asserted */
- if (idereset) {
- writew(0x432, FPGA_CFCTL);
-#if defined(CONFIG_R7780MP)
- writew(inw(FPGA_CFPOW)|0x01, FPGA_CFPOW);
-#else
- writew(inw(FPGA_CFPOW)|0x02, FPGA_CFPOW);
-#endif
- writew(0x01, FPGA_CFCDINTCLR);
- }
-}
-
-static struct pci_controller hose;
-void pci_init_board(void)
-{
- pci_sh7780_init(&hose);
-}
-
-int board_eth_init(struct bd_info *bis)
-{
- /* return >= 0 if a chip is found, the board's AX88796L is n2k-based */
- return ne2k_register() + pci_eth_init(bis);
-}
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2007 Nobuhiro Iwamatsu
- * Copyright (C) 2008 Yusuke Goda <goda.yusuke@renesas.com>
- *
- * u-boot/board/r7780mp/r7780mp.h
- */
-
-#ifndef _BOARD_R7780MP_R7780MP_H_
-#define _BOARD_R7780MP_R7780MP_H_
-
-/* R7780MP's FPGA register map */
-#define FPGA_BASE 0xa4000000
-#define FPGA_IRLMSK (FPGA_BASE + 0x00)
-#define FPGA_IRLMON (FPGA_BASE + 0x02)
-#define FPGA_IRLPRI1 (FPGA_BASE + 0x04)
-#define FPGA_IRLPRI2 (FPGA_BASE + 0x06)
-#define FPGA_IRLPRI3 (FPGA_BASE + 0x08)
-#define FPGA_IRLPRI4 (FPGA_BASE + 0x0A)
-#define FPGA_RSTCTL (FPGA_BASE + 0x0C)
-#define FPGA_PCIBD (FPGA_BASE + 0x0E)
-#define FPGA_PCICD (FPGA_BASE + 0x10)
-#define FPGA_EXTGIO (FPGA_BASE + 0x16)
-#define FPGA_IVDRMON (FPGA_BASE + 0x18)
-#define FPGA_IVDRCR (FPGA_BASE + 0x1A)
-#define FPGA_OBLED (FPGA_BASE + 0x1C)
-#define FPGA_OBSW (FPGA_BASE + 0x1E)
-#define FPGA_TPCTL (FPGA_BASE + 0x100)
-#define FPGA_TPDCKCTL (FPGA_BASE + 0x102)
-#define FPGA_TPCLR (FPGA_BASE + 0x104)
-#define FPGA_TPXPOS (FPGA_BASE + 0x106)
-#define FPGA_TPYPOS (FPGA_BASE + 0x108)
-#define FPGA_DBSW (FPGA_BASE + 0x200)
-#define FPGA_VERSION (FPGA_BASE + 0x700)
-#define FPGA_CFCTL (FPGA_BASE + 0x300)
-#define FPGA_CFPOW (FPGA_BASE + 0x302)
-#define FPGA_CFCDINTCLR (FPGA_BASE + 0x304)
-#define FPGA_PMR (FPGA_BASE + 0x900)
-
-#endif /* _BOARD_R7780RP_R7780RP_H_ */
+++ /dev/null
-if TARGET_SH7752EVB
-
-config SYS_BOARD
- default "sh7752evb"
-
-config SYS_VENDOR
- default "renesas"
-
-config SYS_CONFIG_NAME
- default "sh7752evb"
-
-endif
+++ /dev/null
-SH7752EVB BOARD
-#M: -
-S: Maintained
-F: board/renesas/sh7752evb/
-F: include/configs/sh7752evb.h
-F: configs/sh7752evb_defconfig
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (C) 2012 Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
-#
-
-obj-y := sh7752evb.o spi-boot.o
-extra-y += lowlevel_init.o
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2012 Renesas Solutions Corp.
- */
-
-#include <config.h>
-#include <asm/processor.h>
-#include <asm/macro.h>
-
-.macro or32, addr, data
- mov.l \addr, r1
- mov.l \data, r0
- mov.l @r1, r2
- or r2, r0
- mov.l r0, @r1
-.endm
-
-.macro wait_DBCMD
- mov.l DBWAIT_A, r0
- mov.l @r0, r1
-.endm
-
- .global lowlevel_init
- .section .spiboot1.text
- .align 2
-
-lowlevel_init:
- /*------- GPIO -------*/
- write16 PDCR_A, PDCR_D ! SPI0
- write16 PGCR_A, PGCR_D ! SPI0, GETHER MDIO gate(PTG1)
- write16 PJCR_A, PJCR_D ! SCIF4
- write16 PTCR_A, PTCR_D ! STATUS
- write16 PSEL1_A, PSEL1_D ! SPI0
- write16 PSEL2_A, PSEL2_D ! SPI0
- write16 PSEL5_A, PSEL5_D ! STATUS
-
- bra exit_gpio
- nop
-
- .align 2
-
-/*------- GPIO -------*/
-PDCR_A: .long 0xffec0006
-PGCR_A: .long 0xffec000c
-PJCR_A: .long 0xffec0012
-PTCR_A: .long 0xffec0026
-PSEL1_A: .long 0xffec0072
-PSEL2_A: .long 0xffec0074
-PSEL5_A: .long 0xffec007a
-
-PDCR_D: .long 0x0000
-PGCR_D: .long 0x0004
-PJCR_D: .long 0x0000
-PTCR_D: .long 0x0000
-PSEL1_D: .long 0x0000
-PSEL2_D: .long 0x3000
-PSEL5_D: .long 0x0ffc
-
- .align 2
-
-exit_gpio:
- mov #0, r14
- mova 2f, r0
- mov.l PC_MASK, r1
- tst r0, r1
- bf 2f
-
- bra exit_pmb
- nop
-
- .align 2
-
-/* If CPU runs on SDRAM (PC=0x5???????) or not. */
-PC_MASK: .long 0x20000000
-
-2:
- mov #1, r14
-
- mov.l EXPEVT_A, r0
- mov.l @r0, r0
- mov.l EXPEVT_POWER_ON_RESET, r1
- cmp/eq r0, r1
- bt 1f
-
- /*
- * If EXPEVT value is manual reset or tlb multipul-hit,
- * initialization of DDR3IF is not necessary.
- */
- bra exit_ddr
- nop
-
-1:
- /*------- Reset -------*/
- write32 MRSTCR0_A, MRSTCR0_D
- write32 MRSTCR1_A, MRSTCR1_D
-
- /* For Core Reset */
- mov.l DBACEN_A, r0
- mov.l @r0, r0
- cmp/eq #0, r0
- bt 3f
-
- /*
- * If DBACEN == 1(DBSC was already enabled), we have to avoid the
- * initialization of DDR3-SDRAM.
- */
- bra exit_ddr
- nop
-
-3:
- /*------- DDR3IF -------*/
- /* oscillation stabilization time */
- wait_timer WAIT_OSC_TIME
-
- /* step 3 */
- write32 DBCMD_A, DBCMD_RSTL_VAL
- wait_timer WAIT_30US
-
- /* step 4 */
- write32 DBCMD_A, DBCMD_PDEN_VAL
-
- /* step 5 */
- write32 DBKIND_A, DBKIND_D
-
- /* step 6 */
- write32 DBCONF_A, DBCONF_D
- write32 DBTR0_A, DBTR0_D
- write32 DBTR1_A, DBTR1_D
- write32 DBTR2_A, DBTR2_D
- write32 DBTR3_A, DBTR3_D
- write32 DBTR4_A, DBTR4_D
- write32 DBTR5_A, DBTR5_D
- write32 DBTR6_A, DBTR6_D
- write32 DBTR7_A, DBTR7_D
- write32 DBTR8_A, DBTR8_D
- write32 DBTR9_A, DBTR9_D
- write32 DBTR10_A, DBTR10_D
- write32 DBTR11_A, DBTR11_D
- write32 DBTR12_A, DBTR12_D
- write32 DBTR13_A, DBTR13_D
- write32 DBTR14_A, DBTR14_D
- write32 DBTR15_A, DBTR15_D
- write32 DBTR16_A, DBTR16_D
- write32 DBTR17_A, DBTR17_D
- write32 DBTR18_A, DBTR18_D
- write32 DBTR19_A, DBTR19_D
- write32 DBRNK0_A, DBRNK0_D
-
- /* step 7 */
- write32 DBPDCNT3_A, DBPDCNT3_D
-
- /* step 8 */
- write32 DBPDCNT1_A, DBPDCNT1_D
- write32 DBPDCNT2_A, DBPDCNT2_D
- write32 DBPDLCK_A, DBPDLCK_D
- write32 DBPDRGA_A, DBPDRGA_D
- write32 DBPDRGD_A, DBPDRGD_D
-
- /* step 9 */
- wait_timer WAIT_30US
-
- /* step 10 */
- write32 DBPDCNT0_A, DBPDCNT0_D
-
- /* step 11 */
- wait_timer WAIT_30US
- wait_timer WAIT_30US
-
- /* step 12 */
- write32 DBCMD_A, DBCMD_WAIT_VAL
- wait_DBCMD
-
- /* step 13 */
- write32 DBCMD_A, DBCMD_RSTH_VAL
- wait_DBCMD
-
- /* step 14 */
- write32 DBCMD_A, DBCMD_WAIT_VAL
- write32 DBCMD_A, DBCMD_WAIT_VAL
- write32 DBCMD_A, DBCMD_WAIT_VAL
- write32 DBCMD_A, DBCMD_WAIT_VAL
-
- /* step 15 */
- write32 DBCMD_A, DBCMD_PDXT_VAL
-
- /* step 16 */
- write32 DBCMD_A, DBCMD_MRS2_VAL
-
- /* step 17 */
- write32 DBCMD_A, DBCMD_MRS3_VAL
-
- /* step 18 */
- write32 DBCMD_A, DBCMD_MRS1_VAL
-
- /* step 19 */
- write32 DBCMD_A, DBCMD_MRS0_VAL
-
- /* step 20 */
- write32 DBCMD_A, DBCMD_ZQCL_VAL
-
- write32 DBCMD_A, DBCMD_REF_VAL
- write32 DBCMD_A, DBCMD_REF_VAL
- wait_DBCMD
-
- /* step 21 */
- write32 DBADJ0_A, DBADJ0_D
- write32 DBADJ1_A, DBADJ1_D
- write32 DBADJ2_A, DBADJ2_D
-
- /* step 22 */
- write32 DBRFCNF0_A, DBRFCNF0_D
- write32 DBRFCNF1_A, DBRFCNF1_D
- write32 DBRFCNF2_A, DBRFCNF2_D
-
- /* step 23 */
- write32 DBCALCNF_A, DBCALCNF_D
-
- /* step 24 */
- write32 DBRFEN_A, DBRFEN_D
- write32 DBCMD_A, DBCMD_SRXT_VAL
-
- /* step 25 */
- write32 DBACEN_A, DBACEN_D
-
- /* step 26 */
- wait_DBCMD
-
- bra exit_ddr
- nop
-
- .align 2
-
-EXPEVT_A: .long 0xff000024
-EXPEVT_POWER_ON_RESET: .long 0x00000000
-
-/*------- Reset -------*/
-MRSTCR0_A: .long 0xffd50030
-MRSTCR0_D: .long 0xfe1ffe7f
-MRSTCR1_A: .long 0xffd50034
-MRSTCR1_D: .long 0xfff3ffff
-
-/*------- DDR3IF -------*/
-DBCMD_A: .long 0xfe800018
-DBKIND_A: .long 0xfe800020
-DBCONF_A: .long 0xfe800024
-DBTR0_A: .long 0xfe800040
-DBTR1_A: .long 0xfe800044
-DBTR2_A: .long 0xfe800048
-DBTR3_A: .long 0xfe800050
-DBTR4_A: .long 0xfe800054
-DBTR5_A: .long 0xfe800058
-DBTR6_A: .long 0xfe80005c
-DBTR7_A: .long 0xfe800060
-DBTR8_A: .long 0xfe800064
-DBTR9_A: .long 0xfe800068
-DBTR10_A: .long 0xfe80006c
-DBTR11_A: .long 0xfe800070
-DBTR12_A: .long 0xfe800074
-DBTR13_A: .long 0xfe800078
-DBTR14_A: .long 0xfe80007c
-DBTR15_A: .long 0xfe800080
-DBTR16_A: .long 0xfe800084
-DBTR17_A: .long 0xfe800088
-DBTR18_A: .long 0xfe80008c
-DBTR19_A: .long 0xfe800090
-DBRNK0_A: .long 0xfe800100
-DBPDCNT0_A: .long 0xfe800200
-DBPDCNT1_A: .long 0xfe800204
-DBPDCNT2_A: .long 0xfe800208
-DBPDCNT3_A: .long 0xfe80020c
-DBPDLCK_A: .long 0xfe800280
-DBPDRGA_A: .long 0xfe800290
-DBPDRGD_A: .long 0xfe8002a0
-DBADJ0_A: .long 0xfe8000c0
-DBADJ1_A: .long 0xfe8000c4
-DBADJ2_A: .long 0xfe8000c8
-DBRFCNF0_A: .long 0xfe8000e0
-DBRFCNF1_A: .long 0xfe8000e4
-DBRFCNF2_A: .long 0xfe8000e8
-DBCALCNF_A: .long 0xfe8000f4
-DBRFEN_A: .long 0xfe800014
-DBACEN_A: .long 0xfe800010
-DBWAIT_A: .long 0xfe80001c
-
-WAIT_OSC_TIME: .long 6000
-WAIT_30US: .long 13333
-
-DBCMD_RSTL_VAL: .long 0x20000000
-DBCMD_PDEN_VAL: .long 0x1000d73c
-DBCMD_WAIT_VAL: .long 0x0000d73c
-DBCMD_RSTH_VAL: .long 0x2100d73c
-DBCMD_PDXT_VAL: .long 0x110000c8
-DBCMD_MRS0_VAL: .long 0x28000930
-DBCMD_MRS1_VAL: .long 0x29000004
-DBCMD_MRS2_VAL: .long 0x2a000008
-DBCMD_MRS3_VAL: .long 0x2b000000
-DBCMD_ZQCL_VAL: .long 0x03000200
-DBCMD_REF_VAL: .long 0x0c000000
-DBCMD_SRXT_VAL: .long 0x19000000
-DBKIND_D: .long 0x00000007
-DBCONF_D: .long 0x0f030a01
-DBTR0_D: .long 0x00000007
-DBTR1_D: .long 0x00000006
-DBTR2_D: .long 0x00000000
-DBTR3_D: .long 0x00000007
-DBTR4_D: .long 0x00070007
-DBTR5_D: .long 0x0000001b
-DBTR6_D: .long 0x00000014
-DBTR7_D: .long 0x00000005
-DBTR8_D: .long 0x00000015
-DBTR9_D: .long 0x00000006
-DBTR10_D: .long 0x00000008
-DBTR11_D: .long 0x00000007
-DBTR12_D: .long 0x0000000e
-DBTR13_D: .long 0x00000056
-DBTR14_D: .long 0x00000006
-DBTR15_D: .long 0x00000004
-DBTR16_D: .long 0x00150002
-DBTR17_D: .long 0x000c0017
-DBTR18_D: .long 0x00000200
-DBTR19_D: .long 0x00000040
-DBRNK0_D: .long 0x00000001
-DBPDCNT0_D: .long 0x00000001
-DBPDCNT1_D: .long 0x00000001
-DBPDCNT2_D: .long 0x00000000
-DBPDCNT3_D: .long 0x00004010
-DBPDLCK_D: .long 0x0000a55a
-DBPDRGA_D: .long 0x00000028
-DBPDRGD_D: .long 0x00017100
-
-DBADJ0_D: .long 0x00000000
-DBADJ1_D: .long 0x00000000
-DBADJ2_D: .long 0x18061806
-DBRFCNF0_D: .long 0x000001ff
-DBRFCNF1_D: .long 0x08001000
-DBRFCNF2_D: .long 0x00000000
-DBCALCNF_D: .long 0x0000ffff
-DBRFEN_D: .long 0x00000001
-DBACEN_D: .long 0x00000001
-
- .align 2
-exit_ddr:
-#if defined(CONFIG_SH_32BIT)
- /*------- set PMB -------*/
- write32 PASCR_A, PASCR_29BIT_D
- write32 MMUCR_A, MMUCR_D
-
- /*****************************************************************
- * ent virt phys v sz c wt
- * 0 0xa0000000 0x00000000 1 128M 0 1
- * 1 0xa8000000 0x48000000 1 128M 0 1
- * 5 0x88000000 0x48000000 1 128M 1 1
- */
- write32 PMB_ADDR_SPIBOOT_A, PMB_ADDR_SPIBOOT_D
- write32 PMB_DATA_SPIBOOT_A, PMB_DATA_SPIBOOT_D
- write32 PMB_ADDR_DDR_C1_A, PMB_ADDR_DDR_C1_D
- write32 PMB_DATA_DDR_C1_A, PMB_DATA_DDR_C1_D
- write32 PMB_ADDR_DDR_N1_A, PMB_ADDR_DDR_N1_D
- write32 PMB_DATA_DDR_N1_A, PMB_DATA_DDR_N1_D
-
- write32 PMB_ADDR_ENTRY2, PMB_ADDR_NOT_USE_D
- write32 PMB_ADDR_ENTRY3, PMB_ADDR_NOT_USE_D
- write32 PMB_ADDR_ENTRY4, PMB_ADDR_NOT_USE_D
- write32 PMB_ADDR_ENTRY6, PMB_ADDR_NOT_USE_D
- write32 PMB_ADDR_ENTRY7, PMB_ADDR_NOT_USE_D
- write32 PMB_ADDR_ENTRY8, PMB_ADDR_NOT_USE_D
- write32 PMB_ADDR_ENTRY9, PMB_ADDR_NOT_USE_D
- write32 PMB_ADDR_ENTRY10, PMB_ADDR_NOT_USE_D
- write32 PMB_ADDR_ENTRY11, PMB_ADDR_NOT_USE_D
- write32 PMB_ADDR_ENTRY12, PMB_ADDR_NOT_USE_D
- write32 PMB_ADDR_ENTRY13, PMB_ADDR_NOT_USE_D
- write32 PMB_ADDR_ENTRY14, PMB_ADDR_NOT_USE_D
- write32 PMB_ADDR_ENTRY15, PMB_ADDR_NOT_USE_D
-
- write32 PASCR_A, PASCR_INIT
- mov.l DUMMY_ADDR, r0
- icbi @r0
-#endif /* if defined(CONFIG_SH_32BIT) */
-
-exit_pmb:
- /* CPU is running on ILRAM? */
- mov r14, r0
- tst #1, r0
- bt 1f
-
- mov.l _stack_ilram, r15
- mov.l _spiboot_main, r0
-100: bsrf r0
- nop
-
- .align 2
-_spiboot_main: .long (spiboot_main - (100b + 4))
-_stack_ilram: .long 0xe5204000
-
-1:
- write32 CCR_A, CCR_D
-
- rts
- nop
-
- .align 2
-
-#if defined(CONFIG_SH_32BIT)
-/*------- set PMB -------*/
-PMB_ADDR_SPIBOOT_A: .long PMB_ADDR_BASE(0)
-PMB_ADDR_DDR_N1_A: .long PMB_ADDR_BASE(1)
-PMB_ADDR_DDR_C1_A: .long PMB_ADDR_BASE(5)
-PMB_ADDR_ENTRY2: .long PMB_ADDR_BASE(2)
-PMB_ADDR_ENTRY3: .long PMB_ADDR_BASE(3)
-PMB_ADDR_ENTRY4: .long PMB_ADDR_BASE(4)
-PMB_ADDR_ENTRY6: .long PMB_ADDR_BASE(6)
-PMB_ADDR_ENTRY7: .long PMB_ADDR_BASE(7)
-PMB_ADDR_ENTRY8: .long PMB_ADDR_BASE(8)
-PMB_ADDR_ENTRY9: .long PMB_ADDR_BASE(9)
-PMB_ADDR_ENTRY10: .long PMB_ADDR_BASE(10)
-PMB_ADDR_ENTRY11: .long PMB_ADDR_BASE(11)
-PMB_ADDR_ENTRY12: .long PMB_ADDR_BASE(12)
-PMB_ADDR_ENTRY13: .long PMB_ADDR_BASE(13)
-PMB_ADDR_ENTRY14: .long PMB_ADDR_BASE(14)
-PMB_ADDR_ENTRY15: .long PMB_ADDR_BASE(15)
-
-PMB_ADDR_SPIBOOT_D: .long mk_pmb_addr_val(0xa0)
-PMB_ADDR_DDR_C1_D: .long mk_pmb_addr_val(0x88)
-PMB_ADDR_DDR_N1_D: .long mk_pmb_addr_val(0xa8)
-PMB_ADDR_NOT_USE_D: .long 0x00000000
-
-PMB_DATA_SPIBOOT_A: .long PMB_DATA_BASE(0)
-PMB_DATA_DDR_N1_A: .long PMB_DATA_BASE(1)
-PMB_DATA_DDR_C1_A: .long PMB_DATA_BASE(5)
-
-/* ppn ub v s1 s0 c wt */
-PMB_DATA_SPIBOOT_D: .long mk_pmb_data_val(0x00, 0, 1, 1, 0, 0, 1)
-PMB_DATA_DDR_C1_D: .long mk_pmb_data_val(0x48, 0, 1, 1, 0, 1, 1)
-PMB_DATA_DDR_N1_D: .long mk_pmb_data_val(0x48, 1, 1, 1, 0, 0, 1)
-
-PASCR_A: .long 0xff000070
-DUMMY_ADDR: .long 0xa0000000
-PASCR_29BIT_D: .long 0x00000000
-PASCR_INIT: .long 0x80000080
-MMUCR_A: .long 0xff000010
-MMUCR_D: .long 0x00000004 /* clear ITLB */
-#endif /* CONFIG_SH_32BIT */
-
-CCR_A: .long CCR
-CCR_D: .long CCR_CACHE_INIT
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2012 Renesas Solutions Corp.
- */
-
-#include <common.h>
-#include <command.h>
-#include <env.h>
-#include <flash.h>
-#include <init.h>
-#include <malloc.h>
-#include <net.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <asm/mmc.h>
-#include <spi.h>
-#include <spi_flash.h>
-#include <linux/delay.h>
-
-int checkboard(void)
-{
- puts("BOARD: SH7752 evaluation board (R0P7752C00000RZ)\n");
-
- return 0;
-}
-
-static void init_gpio(void)
-{
- struct gpio_regs *gpio = GPIO_BASE;
- struct sermux_regs *sermux = SERMUX_BASE;
-
- /* GPIO */
- writew(0x0000, &gpio->pacr); /* GETHER */
- writew(0x0001, &gpio->pbcr); /* INTC */
- writew(0x0000, &gpio->pccr); /* PWMU, INTC */
- writew(0xeaff, &gpio->pecr); /* GPIO */
- writew(0x0000, &gpio->pfcr); /* WDT */
- writew(0x0000, &gpio->phcr); /* SPI1 */
- writew(0x0000, &gpio->picr); /* SDHI */
- writew(0x0003, &gpio->pkcr); /* SerMux */
- writew(0x0000, &gpio->plcr); /* SerMux */
- writew(0x0000, &gpio->pmcr); /* RIIC */
- writew(0x0000, &gpio->pncr); /* USB, SGPIO */
- writew(0x0000, &gpio->pocr); /* SGPIO */
- writew(0xd555, &gpio->pqcr); /* GPIO */
- writew(0x0000, &gpio->prcr); /* RIIC */
- writew(0x0000, &gpio->pscr); /* RIIC */
- writeb(0x00, &gpio->pudr);
- writew(0x5555, &gpio->pucr); /* Debug LED */
- writew(0x0000, &gpio->pvcr); /* RSPI */
- writew(0x0000, &gpio->pwcr); /* EVC */
- writew(0x0000, &gpio->pxcr); /* LBSC */
- writew(0x0000, &gpio->pycr); /* LBSC */
- writew(0x0000, &gpio->pzcr); /* eMMC */
- writew(0xfe00, &gpio->psel0);
- writew(0xff00, &gpio->psel3);
- writew(0x771f, &gpio->psel4);
- writew(0x00ff, &gpio->psel6);
- writew(0xfc00, &gpio->psel7);
-
- writeb(0x10, &sermux->smr0); /* SMR0: SerMux mode 0 */
-}
-
-static void init_usb_phy(void)
-{
- struct usb_common_regs *common0 = USB0_COMMON_BASE;
- struct usb_common_regs *common1 = USB1_COMMON_BASE;
- struct usb0_phy_regs *phy = USB0_PHY_BASE;
- struct usb1_port_regs *port = USB1_PORT_BASE;
- struct usb1_alignment_regs *align = USB1_ALIGNMENT_BASE;
-
- writew(0x0100, &phy->reset); /* set reset */
- /* port0 = USB0, port1 = USB1 */
- writew(0x0002, &phy->portsel);
- writel(0x0001, &port->port1sel); /* port1 = Host */
- writew(0x0111, &phy->reset); /* clear reset */
-
- writew(0x4000, &common0->suspmode);
- writew(0x4000, &common1->suspmode);
-
-#if defined(__LITTLE_ENDIAN)
- writel(0x00000000, &align->ehcidatac);
- writel(0x00000000, &align->ohcidatac);
-#endif
-}
-
-static void init_gether_mdio(void)
-{
- struct gpio_regs *gpio = GPIO_BASE;
-
- writew(readw(&gpio->pgcr) | 0x0004, &gpio->pgcr);
- writeb(readb(&gpio->pgdr) | 0x02, &gpio->pgdr); /* Use ET0-MDIO */
-}
-
-static void set_mac_to_sh_giga_eth_register(int channel, char *mac_string)
-{
- struct ether_mac_regs *ether;
- unsigned char mac[6];
- unsigned long val;
-
- string_to_enetaddr(mac_string, mac);
-
- if (!channel)
- ether = GETHER0_MAC_BASE;
- else
- ether = GETHER1_MAC_BASE;
-
- val = (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3];
- writel(val, ðer->mahr);
- val = (mac[4] << 8) | mac[5];
- writel(val, ðer->malr);
-}
-
-/*****************************************************************
- * This PMB must be set on this timing. The lowlevel_init is run on
- * Area 0(phys 0x00000000), so we have to map it.
- *
- * The new PMB table is following:
- * ent virt phys v sz c wt
- * 0 0xa0000000 0x40000000 1 128M 0 1
- * 1 0xa8000000 0x48000000 1 128M 0 1
- * 2 0xb0000000 0x50000000 1 128M 0 1
- * 3 0xb8000000 0x58000000 1 128M 0 1
- * 4 0x80000000 0x40000000 1 128M 1 1
- * 5 0x88000000 0x48000000 1 128M 1 1
- * 6 0x90000000 0x50000000 1 128M 1 1
- * 7 0x98000000 0x58000000 1 128M 1 1
- */
-static void set_pmb_on_board_init(void)
-{
- struct mmu_regs *mmu = MMU_BASE;
-
- /* clear ITLB */
- writel(0x00000004, &mmu->mmucr);
-
- /* delete PMB for SPIBOOT */
- writel(0, PMB_ADDR_BASE(0));
- writel(0, PMB_DATA_BASE(0));
-
- /* add PMB for SDRAM(0x40000000 - 0x47ffffff) */
- /* ppn ub v s1 s0 c wt */
- writel(mk_pmb_addr_val(0xa0), PMB_ADDR_BASE(0));
- writel(mk_pmb_data_val(0x40, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(0));
- writel(mk_pmb_addr_val(0xb0), PMB_ADDR_BASE(2));
- writel(mk_pmb_data_val(0x50, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(2));
- writel(mk_pmb_addr_val(0xb8), PMB_ADDR_BASE(3));
- writel(mk_pmb_data_val(0x58, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(3));
- writel(mk_pmb_addr_val(0x80), PMB_ADDR_BASE(4));
- writel(mk_pmb_data_val(0x40, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(4));
- writel(mk_pmb_addr_val(0x90), PMB_ADDR_BASE(6));
- writel(mk_pmb_data_val(0x50, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(6));
- writel(mk_pmb_addr_val(0x98), PMB_ADDR_BASE(7));
- writel(mk_pmb_data_val(0x58, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(7));
-}
-
-int board_init(void)
-{
- init_gpio();
- set_pmb_on_board_init();
-
- init_usb_phy();
- init_gether_mdio();
-
- return 0;
-}
-
-int board_mmc_init(struct bd_info *bis)
-{
- struct gpio_regs *gpio = GPIO_BASE;
-
- writew(readw(&gpio->pgcr) | 0x0040, &gpio->pgcr);
- writeb(readb(&gpio->pgdr) & ~0x08, &gpio->pgdr); /* Reset */
- udelay(1);
- writeb(readb(&gpio->pgdr) | 0x08, &gpio->pgdr); /* Release reset */
- udelay(200);
-
- return mmcif_mmc_init();
-}
-
-static int get_sh_eth_mac_raw(unsigned char *buf, int size)
-{
-#ifdef CONFIG_DEPRECATED
- struct spi_flash *spi;
- int ret;
-
- spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
- if (spi == NULL) {
- printf("%s: spi_flash probe failed.\n", __func__);
- return 1;
- }
-
- ret = spi_flash_read(spi, SH7752EVB_ETHERNET_MAC_BASE, size, buf);
- if (ret) {
- printf("%s: spi_flash read failed.\n", __func__);
- spi_flash_free(spi);
- return 1;
- }
- spi_flash_free(spi);
-#endif
-
- return 0;
-}
-
-static int get_sh_eth_mac(int channel, char *mac_string, unsigned char *buf)
-{
- memcpy(mac_string, &buf[channel * (SH7752EVB_ETHERNET_MAC_SIZE + 1)],
- SH7752EVB_ETHERNET_MAC_SIZE);
- mac_string[SH7752EVB_ETHERNET_MAC_SIZE] = 0x00; /* terminate */
-
- return 0;
-}
-
-static void init_ethernet_mac(void)
-{
- char mac_string[64];
- char env_string[64];
- int i;
- unsigned char *buf;
-
- buf = malloc(256);
- if (!buf) {
- printf("%s: malloc failed.\n", __func__);
- return;
- }
- get_sh_eth_mac_raw(buf, 256);
-
- /* Gigabit Ethernet */
- for (i = 0; i < SH7752EVB_ETHERNET_NUM_CH; i++) {
- get_sh_eth_mac(i, mac_string, buf);
- if (i == 0)
- env_set("ethaddr", mac_string);
- else {
- sprintf(env_string, "eth%daddr", i);
- env_set(env_string, mac_string);
- }
- set_mac_to_sh_giga_eth_register(i, mac_string);
- }
-
- free(buf);
-}
-
-int board_late_init(void)
-{
- init_ethernet_mac();
-
- return 0;
-}
-
-#ifdef CONFIG_DEPRECATED
-int do_write_mac(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
-{
- int i, ret;
- char mac_string[256];
- struct spi_flash *spi;
- unsigned char *buf;
-
- if (argc != 3) {
- buf = malloc(256);
- if (!buf) {
- printf("%s: malloc failed.\n", __func__);
- return 1;
- }
-
- get_sh_eth_mac_raw(buf, 256);
-
- /* print current MAC address */
- for (i = 0; i < SH7752EVB_ETHERNET_NUM_CH; i++) {
- get_sh_eth_mac(i, mac_string, buf);
- printf("GETHERC ch%d = %s\n", i, mac_string);
- }
- free(buf);
- return 0;
- }
-
- /* new setting */
- memset(mac_string, 0xff, sizeof(mac_string));
- sprintf(mac_string, "%s\t%s",
- argv[1], argv[2]);
-
- /* write MAC data to SPI rom */
- spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
- if (!spi) {
- printf("%s: spi_flash probe failed.\n", __func__);
- return 1;
- }
-
- ret = spi_flash_erase(spi, SH7752EVB_ETHERNET_MAC_BASE_SPI,
- SH7752EVB_SPI_SECTOR_SIZE);
- if (ret) {
- printf("%s: spi_flash erase failed.\n", __func__);
- return 1;
- }
-
- ret = spi_flash_write(spi, SH7752EVB_ETHERNET_MAC_BASE_SPI,
- sizeof(mac_string), mac_string);
- if (ret) {
- printf("%s: spi_flash write failed.\n", __func__);
- spi_flash_free(spi);
- return 1;
- }
- spi_flash_free(spi);
-
- puts("The writing of the MAC address to SPI ROM was completed.\n");
-
- return 0;
-}
-
-U_BOOT_CMD(
- write_mac, 3, 1, do_write_mac,
- "write MAC address for GETHERC",
- "[GETHERC ch0] [GETHERC ch1]\n"
-);
-#endif
+++ /dev/null
-/*
- * Copyright (C) 2012 Renesas Solutions Corp.
- *
- * This file is subject to the terms and conditions of the GNU Lesser
- * General Public License. See the file "COPYING.LIB" in the main
- * directory of this archive for more details.
- */
-
-#include <common.h>
-
-#define CONFIG_RAM_BOOT_PHYS CONFIG_SYS_TEXT_BASE
-#define CONFIG_SPI_ADDR 0x00000000
-#define CONFIG_SPI_LENGTH CONFIG_SYS_MONITOR_LEN
-#define CONFIG_RAM_BOOT CONFIG_SYS_TEXT_BASE
-
-#define SPIWDMADR 0xFE001018
-#define SPIWDMCNTR 0xFE001020
-#define SPIDMCOR 0xFE001028
-#define SPIDMINTSR 0xFE001188
-#define SPIDMINTMR 0xFE001190
-
-#define SPIDMINTSR_DMEND 0x00000004
-
-#define TBR 0xFE002000
-#define RBR 0xFE002000
-
-#define CR1 0xFE002008
-#define CR2 0xFE002010
-#define CR3 0xFE002018
-#define CR4 0xFE002020
-
-/* CR1 */
-#define SPI_TBE 0x80
-#define SPI_TBF 0x40
-#define SPI_RBE 0x20
-#define SPI_RBF 0x10
-#define SPI_PFONRD 0x08
-#define SPI_SSDB 0x04
-#define SPI_SSD 0x02
-#define SPI_SSA 0x01
-
-/* CR2 */
-#define SPI_RSTF 0x80
-#define SPI_LOOPBK 0x40
-#define SPI_CPOL 0x20
-#define SPI_CPHA 0x10
-#define SPI_L1M0 0x08
-
-/* CR4 */
-#define SPI_TBEI 0x80
-#define SPI_TBFI 0x40
-#define SPI_RBEI 0x20
-#define SPI_RBFI 0x10
-#define SPI_SpiS0 0x02
-#define SPI_SSS 0x01
-
-#define spi_write(val, addr) (*(volatile unsigned long *)(addr)) = val
-#define spi_read(addr) (*(volatile unsigned long *)(addr))
-
-/* M25P80 */
-#define M25_READ 0x03
-
-#define __uses_spiboot2 __attribute__((section(".spiboot2.text")))
-static void __uses_spiboot2 spi_reset(void)
-{
- int timeout = 0x00100000;
-
- /* Make sure the last transaction is finalized */
- spi_write(0x00, CR3);
- spi_write(0x02, CR1);
- while (!(spi_read(CR4) & SPI_SpiS0)) {
- if (timeout-- < 0)
- break;
- }
- spi_write(0x00, CR1);
-
- spi_write(spi_read(CR2) | SPI_RSTF, CR2); /* fifo reset */
- spi_write(spi_read(CR2) & ~SPI_RSTF, CR2);
-
- spi_write(0, SPIDMCOR);
-}
-
-static void __uses_spiboot2 spi_read_flash(void *buf, unsigned long addr,
- unsigned long len)
-{
- spi_write(M25_READ, TBR);
- spi_write((addr >> 16) & 0xFF, TBR);
- spi_write((addr >> 8) & 0xFF, TBR);
- spi_write(addr & 0xFF, TBR);
-
- spi_write(SPIDMINTSR_DMEND, SPIDMINTSR);
- spi_write((unsigned long)buf, SPIWDMADR);
- spi_write(len & 0xFFFFFFE0, SPIWDMCNTR);
- spi_write(1, SPIDMCOR);
-
- spi_write(0xff, CR3);
- spi_write(spi_read(CR1) | SPI_SSDB, CR1);
- spi_write(spi_read(CR1) | SPI_SSA, CR1);
-
- while (!(spi_read(SPIDMINTSR) & SPIDMINTSR_DMEND))
- ;
-
- /* Nagate SP0-SS0 */
- spi_write(0, CR1);
-}
-
-void __uses_spiboot2 spiboot_main(void)
-{
- void (*_start)(void) = (void *)CONFIG_SYS_TEXT_BASE;
-
- spi_reset();
- spi_read_flash((void *)CONFIG_RAM_BOOT_PHYS, CONFIG_SPI_ADDR,
- CONFIG_SPI_LENGTH);
-
- _start();
-}
+++ /dev/null
-if TARGET_SH7753EVB
-
-config SYS_BOARD
- default "sh7753evb"
-
-config SYS_VENDOR
- default "renesas"
-
-config SYS_CONFIG_NAME
- default "sh7753evb"
-
-endif
+++ /dev/null
-SH7753EVB BOARD
-#M: -
-S: Maintained
-F: board/renesas/sh7753evb/
-F: include/configs/sh7753evb.h
-F: configs/sh7753evb_defconfig
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (C) 2012 Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
-#
-
-obj-y := sh7753evb.o spi-boot.o
-extra-y += lowlevel_init.o
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2013 Renesas Solutions Corp.
- */
-
-#include <config.h>
-#include <asm/processor.h>
-#include <asm/macro.h>
-
-.macro or32, addr, data
- mov.l \addr, r1
- mov.l \data, r0
- mov.l @r1, r2
- or r2, r0
- mov.l r0, @r1
-.endm
-
-.macro wait_DBCMD
- mov.l DBWAIT_A, r0
- mov.l @r0, r1
-.endm
-
- .global lowlevel_init
- .section .spiboot1.text
- .align 2
-
-lowlevel_init:
- mov #0, r14
- mova 2f, r0
- mov.l PC_MASK, r1
- tst r0, r1
- bf 2f
-
- bra exit_pmb
- nop
-
- .align 2
-
-/* If CPU runs on SDRAM (PC=0x5???????) or not. */
-PC_MASK: .long 0x20000000
-
-2:
- mov #1, r14
-
- mov.l EXPEVT_A, r0
- mov.l @r0, r0
- mov.l EXPEVT_POWER_ON_RESET, r1
- cmp/eq r0, r1
- bt 1f
-
- /*
- * If EXPEVT value is manual reset or tlb multipul-hit,
- * initialization of DBSC3 is not necessary.
- */
- bra exit_ddr
- nop
-
-1:
- /*------- Reset -------*/
- write32 MRSTCR0_A, MRSTCR0_D
- write32 MRSTCR1_A, MRSTCR1_D
-
- /* For Core Reset */
- mov.l DBACEN_A, r0
- mov.l @r0, r0
- cmp/eq #0, r0
- bt 3f
-
- /*
- * If DBACEN == 1(DBSC was already enabled), we have to avoid the
- * initialization of DDR3-SDRAM.
- */
- bra exit_ddr
- nop
-
-3:
- /*------- DBSC3 -------*/
- /* oscillation stabilization time */
- wait_timer WAIT_OSC_TIME
-
- /* step 3 */
- write32 DBKIND_A, DBKIND_D
-
- /* step 4 */
- write32 DBCONF_A, DBCONF_D
- write32 DBTR0_A, DBTR0_D
- write32 DBTR1_A, DBTR1_D
- write32 DBTR2_A, DBTR2_D
- write32 DBTR3_A, DBTR3_D
- write32 DBTR4_A, DBTR4_D
- write32 DBTR5_A, DBTR5_D
- write32 DBTR6_A, DBTR6_D
- write32 DBTR7_A, DBTR7_D
- write32 DBTR8_A, DBTR8_D
- write32 DBTR9_A, DBTR9_D
- write32 DBTR10_A, DBTR10_D
- write32 DBTR11_A, DBTR11_D
- write32 DBTR12_A, DBTR12_D
- write32 DBTR13_A, DBTR13_D
- write32 DBTR14_A, DBTR14_D
- write32 DBTR15_A, DBTR15_D
- write32 DBTR16_A, DBTR16_D
- write32 DBTR17_A, DBTR17_D
- write32 DBTR18_A, DBTR18_D
- write32 DBTR19_A, DBTR19_D
- write32 DBRNK0_A, DBRNK0_D
- write32 DBADJ0_A, DBADJ0_D
- write32 DBADJ2_A, DBADJ2_D
-
- /* step 5 */
- write32 DBCMD_A, DBCMD_RSTL_VAL
- wait_timer WAIT_30US
-
- /* step 6 */
- write32 DBCMD_A, DBCMD_PDEN_VAL
-
- /* step 7 */
- write32 DBPDCNT3_A, DBPDCNT3_D
-
- /* step 8 */
- write32 DBPDCNT1_A, DBPDCNT1_D
- write32 DBPDCNT2_A, DBPDCNT2_D
- write32 DBPDLCK_A, DBPDLCK_D
- write32 DBPDRGA_A, DBPDRGA_D
- write32 DBPDRGD_A, DBPDRGD_D
-
- /* step 9 */
- wait_timer WAIT_30US
-
- /* step 10 */
- write32 DBPDCNT0_A, DBPDCNT0_D
-
- /* step 11 */
- wait_timer WAIT_30US
- wait_timer WAIT_30US
-
- /* step 12 */
- write32 DBCMD_A, DBCMD_WAIT_VAL
- wait_DBCMD
-
- /* step 13 */
- write32 DBCMD_A, DBCMD_RSTH_VAL
- wait_DBCMD
-
- /* step 14 */
- write32 DBCMD_A, DBCMD_WAIT_VAL
- write32 DBCMD_A, DBCMD_WAIT_VAL
- write32 DBCMD_A, DBCMD_WAIT_VAL
- write32 DBCMD_A, DBCMD_WAIT_VAL
-
- /* step 15 */
- write32 DBCMD_A, DBCMD_PDXT_VAL
-
- /* step 16 */
- write32 DBCMD_A, DBCMD_MRS2_VAL
-
- /* step 17 */
- write32 DBCMD_A, DBCMD_MRS3_VAL
-
- /* step 18 */
- write32 DBCMD_A, DBCMD_MRS1_VAL
-
- /* step 19 */
- write32 DBCMD_A, DBCMD_MRS0_VAL
- write32 DBPDNCNF_A, DBPDNCNF_D
-
- /* step 20 */
- write32 DBCMD_A, DBCMD_ZQCL_VAL
-
- write32 DBCMD_A, DBCMD_REF_VAL
- write32 DBCMD_A, DBCMD_REF_VAL
- wait_DBCMD
-
- /* step 21 */
- write32 DBCALTR_A, DBCALTR_D
-
- /* step 22 */
- write32 DBRFCNF0_A, DBRFCNF0_D
- write32 DBRFCNF1_A, DBRFCNF1_D
- write32 DBRFCNF2_A, DBRFCNF2_D
-
- /* step 23 */
- write32 DBCALCNF_A, DBCALCNF_D
-
- /* step 24 */
- write32 DBRFEN_A, DBRFEN_D
- write32 DBCMD_A, DBCMD_SRXT_VAL
-
- /* step 25 */
- write32 DBACEN_A, DBACEN_D
-
- /* step 26 */
- wait_DBCMD
-
- bra exit_ddr
- nop
-
- .align 2
-
-EXPEVT_A: .long 0xff000024
-EXPEVT_POWER_ON_RESET: .long 0x00000000
-
-/*------- Reset -------*/
-MRSTCR0_A: .long 0xffd50030
-MRSTCR0_D: .long 0xfe1ffe7f
-MRSTCR1_A: .long 0xffd50034
-MRSTCR1_D: .long 0xfff3ffff
-
-/*------- DBSC3 -------*/
-DBCMD_A: .long 0xfe800018
-DBKIND_A: .long 0xfe800020
-DBCONF_A: .long 0xfe800024
-DBTR0_A: .long 0xfe800040
-DBTR1_A: .long 0xfe800044
-DBTR2_A: .long 0xfe800048
-DBTR3_A: .long 0xfe800050
-DBTR4_A: .long 0xfe800054
-DBTR5_A: .long 0xfe800058
-DBTR6_A: .long 0xfe80005c
-DBTR7_A: .long 0xfe800060
-DBTR8_A: .long 0xfe800064
-DBTR9_A: .long 0xfe800068
-DBTR10_A: .long 0xfe80006c
-DBTR11_A: .long 0xfe800070
-DBTR12_A: .long 0xfe800074
-DBTR13_A: .long 0xfe800078
-DBTR14_A: .long 0xfe80007c
-DBTR15_A: .long 0xfe800080
-DBTR16_A: .long 0xfe800084
-DBTR17_A: .long 0xfe800088
-DBTR18_A: .long 0xfe80008c
-DBTR19_A: .long 0xfe800090
-DBRNK0_A: .long 0xfe800100
-DBPDCNT0_A: .long 0xfe800200
-DBPDCNT1_A: .long 0xfe800204
-DBPDCNT2_A: .long 0xfe800208
-DBPDCNT3_A: .long 0xfe80020c
-DBPDLCK_A: .long 0xfe800280
-DBPDRGA_A: .long 0xfe800290
-DBPDRGD_A: .long 0xfe8002a0
-DBADJ0_A: .long 0xfe8000c0
-DBADJ2_A: .long 0xfe8000c8
-DBRFCNF0_A: .long 0xfe8000e0
-DBRFCNF1_A: .long 0xfe8000e4
-DBRFCNF2_A: .long 0xfe8000e8
-DBCALCNF_A: .long 0xfe8000f4
-DBRFEN_A: .long 0xfe800014
-DBACEN_A: .long 0xfe800010
-DBWAIT_A: .long 0xfe80001c
-DBCALTR_A: .long 0xfe8000f8
-DBPDNCNF_A: .long 0xfe800180
-
-WAIT_OSC_TIME: .long 6000
-WAIT_30US: .long 13333
-
-DBCMD_RSTL_VAL: .long 0x20000000
-DBCMD_PDEN_VAL: .long 0x1000d73c
-DBCMD_WAIT_VAL: .long 0x0000d73c
-DBCMD_RSTH_VAL: .long 0x2100d73c
-DBCMD_PDXT_VAL: .long 0x110000c8
-DBCMD_MRS0_VAL: .long 0x28000930
-DBCMD_MRS1_VAL: .long 0x29000004
-DBCMD_MRS2_VAL: .long 0x2a000008
-DBCMD_MRS3_VAL: .long 0x2b000000
-DBCMD_ZQCL_VAL: .long 0x03000200
-DBCMD_REF_VAL: .long 0x0c000000
-DBCMD_SRXT_VAL: .long 0x19000000
-DBKIND_D: .long 0x00000007
-DBCONF_D: .long 0x0f030a01
-DBTR0_D: .long 0x00000007
-DBTR1_D: .long 0x00000006
-DBTR2_D: .long 0x00000000
-DBTR3_D: .long 0x00000007
-DBTR4_D: .long 0x00070007
-DBTR5_D: .long 0x0000001b
-DBTR6_D: .long 0x00000014
-DBTR7_D: .long 0x00000004
-DBTR8_D: .long 0x00000014
-DBTR9_D: .long 0x00000004
-DBTR10_D: .long 0x00000008
-DBTR11_D: .long 0x00000007
-DBTR12_D: .long 0x0000000e
-DBTR13_D: .long 0x000000a0
-DBTR14_D: .long 0x00060006
-DBTR15_D: .long 0x00000003
-DBTR16_D: .long 0x00160002
-DBTR17_D: .long 0x000c0000
-DBTR18_D: .long 0x00000200
-DBTR19_D: .long 0x00000040
-DBRNK0_D: .long 0x00000001
-DBPDCNT0_D: .long 0x00000001
-DBPDCNT1_D: .long 0x00000001
-DBPDCNT2_D: .long 0x00000000
-DBPDCNT3_D: .long 0x00004010
-DBPDLCK_D: .long 0x0000a55a
-DBPDRGA_D: .long 0x00000028
-DBPDRGD_D: .long 0x00017100
-
-DBADJ0_D: .long 0x00010000
-DBADJ2_D: .long 0x18061806
-DBRFCNF0_D: .long 0x000001ff
-DBRFCNF1_D: .long 0x00081040
-DBRFCNF2_D: .long 0x00000000
-DBCALCNF_D: .long 0x0000ffff
-DBRFEN_D: .long 0x00000001
-DBACEN_D: .long 0x00000001
-DBCALTR_D: .long 0x08200820
-DBPDNCNF_D: .long 0x00000001
-
- .align 2
-exit_ddr:
-#if defined(CONFIG_SH_32BIT)
- /*------- set PMB -------*/
- write32 PASCR_A, PASCR_29BIT_D
- write32 MMUCR_A, MMUCR_D
-
- /*****************************************************************
- * ent virt phys v sz c wt
- * 0 0xa0000000 0x00000000 1 128M 0 1
- * 1 0xa8000000 0x48000000 1 128M 0 1
- * 5 0x88000000 0x48000000 1 128M 1 1
- */
- write32 PMB_ADDR_SPIBOOT_A, PMB_ADDR_SPIBOOT_D
- write32 PMB_DATA_SPIBOOT_A, PMB_DATA_SPIBOOT_D
- write32 PMB_ADDR_DDR_C1_A, PMB_ADDR_DDR_C1_D
- write32 PMB_DATA_DDR_C1_A, PMB_DATA_DDR_C1_D
- write32 PMB_ADDR_DDR_N1_A, PMB_ADDR_DDR_N1_D
- write32 PMB_DATA_DDR_N1_A, PMB_DATA_DDR_N1_D
-
- write32 PMB_ADDR_ENTRY2, PMB_ADDR_NOT_USE_D
- write32 PMB_ADDR_ENTRY3, PMB_ADDR_NOT_USE_D
- write32 PMB_ADDR_ENTRY4, PMB_ADDR_NOT_USE_D
- write32 PMB_ADDR_ENTRY6, PMB_ADDR_NOT_USE_D
- write32 PMB_ADDR_ENTRY7, PMB_ADDR_NOT_USE_D
- write32 PMB_ADDR_ENTRY8, PMB_ADDR_NOT_USE_D
- write32 PMB_ADDR_ENTRY9, PMB_ADDR_NOT_USE_D
- write32 PMB_ADDR_ENTRY10, PMB_ADDR_NOT_USE_D
- write32 PMB_ADDR_ENTRY11, PMB_ADDR_NOT_USE_D
- write32 PMB_ADDR_ENTRY12, PMB_ADDR_NOT_USE_D
- write32 PMB_ADDR_ENTRY13, PMB_ADDR_NOT_USE_D
- write32 PMB_ADDR_ENTRY14, PMB_ADDR_NOT_USE_D
- write32 PMB_ADDR_ENTRY15, PMB_ADDR_NOT_USE_D
-
- write32 PASCR_A, PASCR_INIT
- mov.l DUMMY_ADDR, r0
- icbi @r0
-#endif /* if defined(CONFIG_SH_32BIT) */
-
-exit_pmb:
- /* CPU is running on ILRAM? */
- mov r14, r0
- tst #1, r0
- bt 1f
-
- mov.l _stack_ilram, r15
- mov.l _spiboot_main, r0
-100: bsrf r0
- nop
-
- .align 2
-_spiboot_main: .long (spiboot_main - (100b + 4))
-_stack_ilram: .long 0xe5204000
-
-1:
- write32 CCR_A, CCR_D
-
- rts
- nop
-
- .align 2
-
-#if defined(CONFIG_SH_32BIT)
-/*------- set PMB -------*/
-PMB_ADDR_SPIBOOT_A: .long PMB_ADDR_BASE(0)
-PMB_ADDR_DDR_N1_A: .long PMB_ADDR_BASE(1)
-PMB_ADDR_DDR_C1_A: .long PMB_ADDR_BASE(5)
-PMB_ADDR_ENTRY2: .long PMB_ADDR_BASE(2)
-PMB_ADDR_ENTRY3: .long PMB_ADDR_BASE(3)
-PMB_ADDR_ENTRY4: .long PMB_ADDR_BASE(4)
-PMB_ADDR_ENTRY6: .long PMB_ADDR_BASE(6)
-PMB_ADDR_ENTRY7: .long PMB_ADDR_BASE(7)
-PMB_ADDR_ENTRY8: .long PMB_ADDR_BASE(8)
-PMB_ADDR_ENTRY9: .long PMB_ADDR_BASE(9)
-PMB_ADDR_ENTRY10: .long PMB_ADDR_BASE(10)
-PMB_ADDR_ENTRY11: .long PMB_ADDR_BASE(11)
-PMB_ADDR_ENTRY12: .long PMB_ADDR_BASE(12)
-PMB_ADDR_ENTRY13: .long PMB_ADDR_BASE(13)
-PMB_ADDR_ENTRY14: .long PMB_ADDR_BASE(14)
-PMB_ADDR_ENTRY15: .long PMB_ADDR_BASE(15)
-
-PMB_ADDR_SPIBOOT_D: .long mk_pmb_addr_val(0xa0)
-PMB_ADDR_DDR_C1_D: .long mk_pmb_addr_val(0x88)
-PMB_ADDR_DDR_N1_D: .long mk_pmb_addr_val(0xa8)
-PMB_ADDR_NOT_USE_D: .long 0x00000000
-
-PMB_DATA_SPIBOOT_A: .long PMB_DATA_BASE(0)
-PMB_DATA_DDR_N1_A: .long PMB_DATA_BASE(1)
-PMB_DATA_DDR_C1_A: .long PMB_DATA_BASE(5)
-
-/* ppn ub v s1 s0 c wt */
-PMB_DATA_SPIBOOT_D: .long mk_pmb_data_val(0x00, 0, 1, 1, 0, 0, 1)
-PMB_DATA_DDR_C1_D: .long mk_pmb_data_val(0x48, 0, 1, 1, 0, 1, 1)
-PMB_DATA_DDR_N1_D: .long mk_pmb_data_val(0x48, 1, 1, 1, 0, 0, 1)
-
-PASCR_A: .long 0xff000070
-DUMMY_ADDR: .long 0xa0000000
-PASCR_29BIT_D: .long 0x00000000
-PASCR_INIT: .long 0x80000080
-MMUCR_A: .long 0xff000010
-MMUCR_D: .long 0x00000004 /* clear ITLB */
-#endif /* CONFIG_SH_32BIT */
-
-CCR_A: .long CCR
-CCR_D: .long CCR_CACHE_INIT
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2012 Renesas Solutions Corp.
- */
-
-#include <common.h>
-#include <command.h>
-#include <env.h>
-#include <flash.h>
-#include <init.h>
-#include <malloc.h>
-#include <net.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <asm/mmc.h>
-#include <spi.h>
-#include <spi_flash.h>
-#include <linux/delay.h>
-
-int checkboard(void)
-{
- puts("BOARD: SH7753 EVB\n");
-
- return 0;
-}
-
-static void init_gpio(void)
-{
- struct gpio_regs *gpio = GPIO_BASE;
- struct sermux_regs *sermux = SERMUX_BASE;
-
- /* GPIO */
- writew(0x0000, &gpio->pacr); /* GETHER */
- writew(0x0001, &gpio->pbcr); /* INTC */
- writew(0x0000, &gpio->pccr); /* PWMU, INTC */
- writew(0x0000, &gpio->pdcr); /* SPI0 */
- writew(0xeaff, &gpio->pecr); /* GPIO */
- writew(0x0000, &gpio->pfcr); /* WDT */
- writew(0x0004, &gpio->pgcr); /* SPI0, GETHER MDIO gate(PTG1) */
- writew(0x0000, &gpio->phcr); /* SPI1 */
- writew(0x0000, &gpio->picr); /* SDHI */
- writew(0x0000, &gpio->pjcr); /* SCIF4 */
- writew(0x0003, &gpio->pkcr); /* SerMux */
- writew(0x0000, &gpio->plcr); /* SerMux */
- writew(0x0000, &gpio->pmcr); /* RIIC */
- writew(0x0000, &gpio->pncr); /* USB, SGPIO */
- writew(0x0000, &gpio->pocr); /* SGPIO */
- writew(0xd555, &gpio->pqcr); /* GPIO */
- writew(0x0000, &gpio->prcr); /* RIIC */
- writew(0x0000, &gpio->pscr); /* RIIC */
- writew(0x0000, &gpio->ptcr); /* STATUS */
- writeb(0x00, &gpio->pudr);
- writew(0x5555, &gpio->pucr); /* Debug LED */
- writew(0x0000, &gpio->pvcr); /* RSPI */
- writew(0x0000, &gpio->pwcr); /* EVC */
- writew(0x0000, &gpio->pxcr); /* LBSC */
- writew(0x0000, &gpio->pycr); /* LBSC */
- writew(0x0000, &gpio->pzcr); /* eMMC */
- writew(0xfe00, &gpio->psel0);
- writew(0x0000, &gpio->psel1);
- writew(0x3000, &gpio->psel2);
- writew(0xff00, &gpio->psel3);
- writew(0x771f, &gpio->psel4);
- writew(0x0ffc, &gpio->psel5);
- writew(0x00ff, &gpio->psel6);
- writew(0xfc00, &gpio->psel7);
-
- writeb(0x10, &sermux->smr0); /* SMR0: SerMux mode 0 */
-}
-
-static void init_usb_phy(void)
-{
- struct usb_common_regs *common0 = USB0_COMMON_BASE;
- struct usb_common_regs *common1 = USB1_COMMON_BASE;
- struct usb0_phy_regs *phy = USB0_PHY_BASE;
- struct usb1_port_regs *port = USB1_PORT_BASE;
- struct usb1_alignment_regs *align = USB1_ALIGNMENT_BASE;
-
- writew(0x0100, &phy->reset); /* set reset */
- /* port0 = USB0, port1 = USB1 */
- writew(0x0002, &phy->portsel);
- writel(0x0001, &port->port1sel); /* port1 = Host */
- writew(0x0111, &phy->reset); /* clear reset */
-
- writew(0x4000, &common0->suspmode);
- writew(0x4000, &common1->suspmode);
-
-#if defined(__LITTLE_ENDIAN)
- writel(0x00000000, &align->ehcidatac);
- writel(0x00000000, &align->ohcidatac);
-#endif
-}
-
-static void init_gether_mdio(void)
-{
- struct gpio_regs *gpio = GPIO_BASE;
-
- writew(readw(&gpio->pgcr) | 0x0004, &gpio->pgcr);
- writeb(readb(&gpio->pgdr) | 0x02, &gpio->pgdr); /* Use ET0-MDIO */
-}
-
-static void set_mac_to_sh_giga_eth_register(int channel, char *mac_string)
-{
- struct ether_mac_regs *ether;
- unsigned char mac[6];
- unsigned long val;
-
- string_to_enetaddr(mac_string, mac);
-
- if (!channel)
- ether = GETHER0_MAC_BASE;
- else
- ether = GETHER1_MAC_BASE;
-
- val = (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3];
- writel(val, ðer->mahr);
- val = (mac[4] << 8) | mac[5];
- writel(val, ðer->malr);
-}
-
-#if defined(CONFIG_SH_32BIT)
-/*****************************************************************
- * This PMB must be set on this timing. The lowlevel_init is run on
- * Area 0(phys 0x00000000), so we have to map it.
- *
- * The new PMB table is following:
- * ent virt phys v sz c wt
- * 0 0xa0000000 0x40000000 1 128M 0 1
- * 1 0xa8000000 0x48000000 1 128M 0 1
- * 2 0xb0000000 0x50000000 1 128M 0 1
- * 3 0xb8000000 0x58000000 1 128M 0 1
- * 4 0x80000000 0x40000000 1 128M 1 1
- * 5 0x88000000 0x48000000 1 128M 1 1
- * 6 0x90000000 0x50000000 1 128M 1 1
- * 7 0x98000000 0x58000000 1 128M 1 1
- */
-static void set_pmb_on_board_init(void)
-{
- struct mmu_regs *mmu = MMU_BASE;
-
- /* clear ITLB */
- writel(0x00000004, &mmu->mmucr);
-
- /* delete PMB for SPIBOOT */
- writel(0, PMB_ADDR_BASE(0));
- writel(0, PMB_DATA_BASE(0));
-
- /* add PMB for SDRAM(0x40000000 - 0x47ffffff) */
- /* ppn ub v s1 s0 c wt */
- writel(mk_pmb_addr_val(0xa0), PMB_ADDR_BASE(0));
- writel(mk_pmb_data_val(0x40, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(0));
- writel(mk_pmb_addr_val(0xb0), PMB_ADDR_BASE(2));
- writel(mk_pmb_data_val(0x50, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(2));
- writel(mk_pmb_addr_val(0xb8), PMB_ADDR_BASE(3));
- writel(mk_pmb_data_val(0x58, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(3));
- writel(mk_pmb_addr_val(0x80), PMB_ADDR_BASE(4));
- writel(mk_pmb_data_val(0x40, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(4));
- writel(mk_pmb_addr_val(0x90), PMB_ADDR_BASE(6));
- writel(mk_pmb_data_val(0x50, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(6));
- writel(mk_pmb_addr_val(0x98), PMB_ADDR_BASE(7));
- writel(mk_pmb_data_val(0x58, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(7));
-}
-#endif
-
-int board_init(void)
-{
- struct gether_control_regs *gether = GETHER_CONTROL_BASE;
-
- init_gpio();
-#if defined(CONFIG_SH_32BIT)
- set_pmb_on_board_init();
-#endif
-
- /* Sets TXnDLY to B'010 */
- writel(0x00000202, &gether->gbecont);
-
- init_usb_phy();
- init_gether_mdio();
-
- return 0;
-}
-
-int board_mmc_init(struct bd_info *bis)
-{
- struct gpio_regs *gpio = GPIO_BASE;
-
- writew(readw(&gpio->pgcr) | 0x0040, &gpio->pgcr);
- writeb(readb(&gpio->pgdr) & ~0x08, &gpio->pgdr); /* Reset */
- udelay(1);
- writeb(readb(&gpio->pgdr) | 0x08, &gpio->pgdr); /* Release reset */
- udelay(200);
-
- return mmcif_mmc_init();
-}
-
-static int get_sh_eth_mac_raw(unsigned char *buf, int size)
-{
-#ifdef CONFIG_DEPRECATED
- struct spi_flash *spi;
- int ret;
-
- spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
- if (spi == NULL) {
- printf("%s: spi_flash probe failed.\n", __func__);
- return 1;
- }
-
- ret = spi_flash_read(spi, SH7753EVB_ETHERNET_MAC_BASE, size, buf);
- if (ret) {
- printf("%s: spi_flash read failed.\n", __func__);
- spi_flash_free(spi);
- return 1;
- }
- spi_flash_free(spi);
-#endif
-
- return 0;
-}
-
-static int get_sh_eth_mac(int channel, char *mac_string, unsigned char *buf)
-{
- memcpy(mac_string, &buf[channel * (SH7753EVB_ETHERNET_MAC_SIZE + 1)],
- SH7753EVB_ETHERNET_MAC_SIZE);
- mac_string[SH7753EVB_ETHERNET_MAC_SIZE] = 0x00; /* terminate */
-
- return 0;
-}
-
-static void init_ethernet_mac(void)
-{
- char mac_string[64];
- char env_string[64];
- int i;
- unsigned char *buf;
-
- buf = malloc(256);
- if (!buf) {
- printf("%s: malloc failed.\n", __func__);
- return;
- }
- get_sh_eth_mac_raw(buf, 256);
-
- /* Gigabit Ethernet */
- for (i = 0; i < SH7753EVB_ETHERNET_NUM_CH; i++) {
- get_sh_eth_mac(i, mac_string, buf);
- if (i == 0)
- env_set("ethaddr", mac_string);
- else {
- sprintf(env_string, "eth%daddr", i);
- env_set(env_string, mac_string);
- }
- set_mac_to_sh_giga_eth_register(i, mac_string);
- }
-
- free(buf);
-}
-
-int board_late_init(void)
-{
- init_ethernet_mac();
-
- return 0;
-}
-
-#ifdef CONFIG_DEPRECATED
-int do_write_mac(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
-{
- int i, ret;
- char mac_string[256];
- struct spi_flash *spi;
- unsigned char *buf;
-
- if (argc != 3) {
- buf = malloc(256);
- if (!buf) {
- printf("%s: malloc failed.\n", __func__);
- return 1;
- }
-
- get_sh_eth_mac_raw(buf, 256);
-
- /* print current MAC address */
- for (i = 0; i < SH7753EVB_ETHERNET_NUM_CH; i++) {
- get_sh_eth_mac(i, mac_string, buf);
- printf("GETHERC ch%d = %s\n", i, mac_string);
- }
- free(buf);
- return 0;
- }
-
- /* new setting */
- memset(mac_string, 0xff, sizeof(mac_string));
- sprintf(mac_string, "%s\t%s",
- argv[1], argv[2]);
-
- /* write MAC data to SPI rom */
- spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
- if (!spi) {
- printf("%s: spi_flash probe failed.\n", __func__);
- return 1;
- }
-
- ret = spi_flash_erase(spi, SH7753EVB_ETHERNET_MAC_BASE_SPI,
- SH7753EVB_SPI_SECTOR_SIZE);
- if (ret) {
- printf("%s: spi_flash erase failed.\n", __func__);
- return 1;
- }
-
- ret = spi_flash_write(spi, SH7753EVB_ETHERNET_MAC_BASE_SPI,
- sizeof(mac_string), mac_string);
- if (ret) {
- printf("%s: spi_flash write failed.\n", __func__);
- spi_flash_free(spi);
- return 1;
- }
- spi_flash_free(spi);
-
- puts("The writing of the MAC address to SPI ROM was completed.\n");
-
- return 0;
-}
-
-U_BOOT_CMD(
- write_mac, 3, 1, do_write_mac,
- "write MAC address for GETHERC",
- "[GETHERC ch0] [GETHERC ch1]\n"
-);
-#endif
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2013 Renesas Solutions Corp.
- */
-
-#include <common.h>
-
-#define CONFIG_SPI_ADDR 0x00000000
-#define PHYADDR(_addr) ((_addr & 0x1fffffff) | 0x40000000)
-#define CONFIG_RAM_BOOT_PHYS PHYADDR(CONFIG_SYS_TEXT_BASE)
-
-#define SPIWDMADR 0xFE001018
-#define SPIWDMCNTR 0xFE001020
-#define SPIDMCOR 0xFE001028
-#define SPIDMINTSR 0xFE001188
-#define SPIDMINTMR 0xFE001190
-
-#define SPIDMINTSR_DMEND 0x00000004
-
-#define TBR 0xFE002000
-#define RBR 0xFE002000
-
-#define CR1 0xFE002008
-#define CR2 0xFE002010
-#define CR3 0xFE002018
-#define CR4 0xFE002020
-#define CR7 0xFE002038
-#define CR8 0xFE002040
-
-/* CR1 */
-#define SPI_TBE 0x80
-#define SPI_TBF 0x40
-#define SPI_RBE 0x20
-#define SPI_RBF 0x10
-#define SPI_PFONRD 0x08
-#define SPI_SSDB 0x04
-#define SPI_SSD 0x02
-#define SPI_SSA 0x01
-
-/* CR2 */
-#define SPI_RSTF 0x80
-#define SPI_LOOPBK 0x40
-#define SPI_CPOL 0x20
-#define SPI_CPHA 0x10
-#define SPI_L1M0 0x08
-
-/* CR4 */
-#define SPI_TBEI 0x80
-#define SPI_TBFI 0x40
-#define SPI_RBEI 0x20
-#define SPI_RBFI 0x10
-#define SPI_SpiS0 0x02
-#define SPI_SSS 0x01
-
-/* CR7 */
-#define CR7_IDX_OR12 0x12
-#define OR12_ADDR32 0x00000001
-
-#define spi_write(val, addr) (*(volatile unsigned long *)(addr)) = val
-#define spi_read(addr) (*(volatile unsigned long *)(addr))
-
-/* M25P80 */
-#define M25_READ 0x03
-#define M25_READ_4BYTE 0x13
-
-extern void bss_start(void);
-
-#define __uses_spiboot2 __attribute__((section(".spiboot2.text")))
-static void __uses_spiboot2 spi_reset(void)
-{
- int timeout = 0x00100000;
-
- /* Make sure the last transaction is finalized */
- spi_write(0x00, CR3);
- spi_write(0x02, CR1);
- while (!(spi_read(CR4) & SPI_SpiS0)) {
- if (timeout-- < 0)
- break;
- }
- spi_write(0x00, CR1);
-
- spi_write(spi_read(CR2) | SPI_RSTF, CR2); /* fifo reset */
- spi_write(spi_read(CR2) & ~SPI_RSTF, CR2);
-
- spi_write(0, SPIDMCOR);
-}
-
-static void __uses_spiboot2 spi_read_flash(void *buf, unsigned long addr,
- unsigned long len)
-{
- spi_write(CR7_IDX_OR12, CR7);
- if (spi_read(CR8) & OR12_ADDR32) {
- /* 4-bytes address mode */
- spi_write(M25_READ_4BYTE, TBR);
- spi_write((addr >> 24) & 0xFF, TBR); /* ADDR31-24 */
- } else {
- /* 3-bytes address mode */
- spi_write(M25_READ, TBR);
- }
- spi_write((addr >> 16) & 0xFF, TBR); /* ADDR23-16 */
- spi_write((addr >> 8) & 0xFF, TBR); /* ADDR15-8 */
- spi_write(addr & 0xFF, TBR); /* ADDR7-0 */
-
- spi_write(SPIDMINTSR_DMEND, SPIDMINTSR);
- spi_write((unsigned long)buf, SPIWDMADR);
- spi_write(len & 0xFFFFFFE0, SPIWDMCNTR);
- spi_write(1, SPIDMCOR);
-
- spi_write(0xff, CR3);
- spi_write(spi_read(CR1) | SPI_SSDB, CR1);
- spi_write(spi_read(CR1) | SPI_SSA, CR1);
-
- while (!(spi_read(SPIDMINTSR) & SPIDMINTSR_DMEND))
- ;
-
- /* Nagate SP0-SS0 */
- spi_write(0, CR1);
-}
-
-void __uses_spiboot2 spiboot_main(void)
-{
- /*
- * This code rounds len up for SPIWDMCNTR. We should set it to 0 in
- * lower 5-bits.
- */
- void (*_start)(void) = (void *)CONFIG_SYS_TEXT_BASE;
- volatile unsigned long len = (bss_start - _start + 31) & 0xffffffe0;
-
- spi_reset();
- spi_read_flash((void *)CONFIG_RAM_BOOT_PHYS, CONFIG_SPI_ADDR, len);
-
- _start();
-}
+++ /dev/null
-if TARGET_SH7757LCR
-
-config SYS_BOARD
- default "sh7757lcr"
-
-config SYS_VENDOR
- default "renesas"
-
-config SYS_CONFIG_NAME
- default "sh7757lcr"
-
-endif
+++ /dev/null
-SH7757LCR BOARD
-#M: -
-S: Maintained
-F: board/renesas/sh7757lcr/
-F: include/configs/sh7757lcr.h
-F: configs/sh7757lcr_defconfig
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (C) 2011 Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
-#
-
-obj-y := sh7757lcr.o spi-boot.o
-extra-y += lowlevel_init.o
+++ /dev/null
-========================================
-Renesas R0P7757LC0030RL board
-========================================
-
-This board specification:
-=========================
-
-The R0P7757LC0030RL(board config name:sh7757lcr) has the following device:
-
- - SH7757 (SH-4A)
- - DDR3-SDRAM 256MB (with ECC)
- - SPI ROM 8MB
- - 2D Graphic controller
- - Ethernet controller
- - eMMC 2GB
-
-
-configuration for This board:
-=============================
-
-You can select the configuration as follows:
-
- - make sh7757lcr_config
-
-
-This board specific command:
-============================
-
-This board has the following its specific command:
-
- - sh_g200
- - write_mac
-
-
-1. sh_g200
-
-If we run this command, SH4 can control the G200.
-The default setting is that SH4 cannot control the G200.
-
-
-2. write_mac
-
-You can write MAC address to SPI ROM.
-
- Usage 1) Write MAC address
-
- write_mac [ETHERC ch0] [ETHERC ch1] [GETHERC ch0] [GETHERC ch1]
-
- For example)
- => write_mac 00:00:87:6c:21:80 00:00:87:6c:21:81 00:00:87:6c:21:82 00:00:87:6c:21:83
- *) We have to input the command as a single line
- (without carriage return)
- *) We have to reset after input the command.
-
- Usage 2) Show current data
-
- write_mac
-
- For example)
- => write_mac
- ETHERC ch0 = 00:00:87:6c:21:80
- ETHERC ch1 = 00:00:87:6c:21:81
- GETHERC ch0 = 00:00:87:6c:21:82
- GETHERC ch1 = 00:00:87:6c:21:83
-
-
-Update SPI ROM:
-============================
-
-1. Copy u-boot image to RAM area.
-2. Probe SPI device.
- => sf probe 0
- 8192 KiB M25P64 at 0:0 is now current device
-3. Erase SPI ROM.
- => sf erase 0 80000
-4. Write u-boot image to SPI ROM.
- => sf write 0x89000000 0 80000
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2011 Renesas Solutions Corp.
- */
-
-#include <config.h>
-#include <asm/processor.h>
-#include <asm/macro.h>
-
-.macro or32, addr, data
- mov.l \addr, r1
- mov.l \data, r0
- mov.l @r1, r2
- or r2, r0
- mov.l r0, @r1
-.endm
-
-.macro wait_DBCMD
- mov.l DBWAIT_A, r0
- mov.l @r0, r1
-.endm
-
- .global lowlevel_init
- .section .spiboot1.text
- .align 2
-
-lowlevel_init:
-
- /*------- GPIO -------*/
- write8 PGDR_A, PGDR_D /* eMMC power off */
-
- write16 PACR_A, PACR_D
- write16 PBCR_A, PBCR_D
- write16 PCCR_A, PCCR_D
- write16 PDCR_A, PDCR_D
- write16 PECR_A, PECR_D
- write16 PFCR_A, PFCR_D
- write16 PGCR_A, PGCR_D
- write16 PHCR_A, PHCR_D
- write16 PICR_A, PICR_D
- write16 PJCR_A, PJCR_D
- write16 PKCR_A, PKCR_D
- write16 PLCR_A, PLCR_D
- write16 PMCR_A, PMCR_D
- write16 PNCR_A, PNCR_D
- write16 POCR_A, POCR_D
- write16 PQCR_A, PQCR_D
- write16 PRCR_A, PRCR_D
- write16 PSCR_A, PSCR_D
- write16 PTCR_A, PTCR_D
- write16 PUCR_A, PUCR_D
- write16 PVCR_A, PVCR_D
- write16 PWCR_A, PWCR_D
- write16 PXCR_A, PXCR_D
- write16 PYCR_A, PYCR_D
- write16 PZCR_A, PZCR_D
- write16 PSEL0_A, PSEL0_D
- write16 PSEL1_A, PSEL1_D
- write16 PSEL2_A, PSEL2_D
- write16 PSEL3_A, PSEL3_D
- write16 PSEL4_A, PSEL4_D
- write16 PSEL5_A, PSEL5_D
- write16 PSEL6_A, PSEL6_D
- write16 PSEL7_A, PSEL7_D
- write16 PSEL8_A, PSEL8_D
-
- bra exit_gpio
- nop
-
- .align 4
-
-/*------- GPIO -------*/
-PGDR_A: .long 0xffec0040
-PACR_A: .long 0xffec0000
-PBCR_A: .long 0xffec0002
-PCCR_A: .long 0xffec0004
-PDCR_A: .long 0xffec0006
-PECR_A: .long 0xffec0008
-PFCR_A: .long 0xffec000a
-PGCR_A: .long 0xffec000c
-PHCR_A: .long 0xffec000e
-PICR_A: .long 0xffec0010
-PJCR_A: .long 0xffec0012
-PKCR_A: .long 0xffec0014
-PLCR_A: .long 0xffec0016
-PMCR_A: .long 0xffec0018
-PNCR_A: .long 0xffec001a
-POCR_A: .long 0xffec001c
-PQCR_A: .long 0xffec0020
-PRCR_A: .long 0xffec0022
-PSCR_A: .long 0xffec0024
-PTCR_A: .long 0xffec0026
-PUCR_A: .long 0xffec0028
-PVCR_A: .long 0xffec002a
-PWCR_A: .long 0xffec002c
-PXCR_A: .long 0xffec002e
-PYCR_A: .long 0xffec0030
-PZCR_A: .long 0xffec0032
-PSEL0_A: .long 0xffec0070
-PSEL1_A: .long 0xffec0072
-PSEL2_A: .long 0xffec0074
-PSEL3_A: .long 0xffec0076
-PSEL4_A: .long 0xffec0078
-PSEL5_A: .long 0xffec007a
-PSEL6_A: .long 0xffec007c
-PSEL7_A: .long 0xffec0082
-PSEL8_A: .long 0xffec0084
-
-PGDR_D: .long 0x80
-PACR_D: .long 0x0000
-PBCR_D: .long 0x0001
-PCCR_D: .long 0x0000
-PDCR_D: .long 0x0000
-PECR_D: .long 0x0000
-PFCR_D: .long 0x0000
-PGCR_D: .long 0x0000
-PHCR_D: .long 0x0000
-PICR_D: .long 0x0000
-PJCR_D: .long 0x0000
-PKCR_D: .long 0x0003
-PLCR_D: .long 0x0000
-PMCR_D: .long 0x0000
-PNCR_D: .long 0x0000
-POCR_D: .long 0x0000
-PQCR_D: .long 0xc000
-PRCR_D: .long 0x0000
-PSCR_D: .long 0x0000
-PTCR_D: .long 0x0000
-#if defined(CONFIG_SH7757_OFFSET_SPI)
-PUCR_D: .long 0x0055
-#else
-PUCR_D: .long 0x0000
-#endif
-PVCR_D: .long 0x0000
-PWCR_D: .long 0x0000
-PXCR_D: .long 0x0000
-PYCR_D: .long 0x0000
-PZCR_D: .long 0x0000
-PSEL0_D: .long 0xfe00
-PSEL1_D: .long 0x0000
-PSEL2_D: .long 0x3000
-PSEL3_D: .long 0xff00
-PSEL4_D: .long 0x771f
-PSEL5_D: .long 0x0ffc
-PSEL6_D: .long 0x00ff
-PSEL7_D: .long 0xfc00
-PSEL8_D: .long 0x0000
-
- .align 2
-
-exit_gpio:
- mov #0, r14
- mova 2f, r0
- mov.l PC_MASK, r1
- tst r0, r1
- bf 2f
-
- bra exit_pmb
- nop
-
- .align 2
-
-/* If CPU runs on SDRAM, PC is 0x8???????. */
-PC_MASK: .long 0x20000000
-
-2:
- mov #1, r14
-
- mov.l EXPEVT_A, r0
- mov.l @r0, r0
- mov.l EXPEVT_POWER_ON_RESET, r1
- cmp/eq r0, r1
- bt 1f
-
- /*
- * If EXPEVT value is manual reset or tlb multipul-hit,
- * initialization of DDR3IF is not necessary.
- */
- bra exit_ddr
- nop
-
-1:
- /* For Core Reset */
- mov.l DBACEN_A, r0
- mov.l @r0, r0
- cmp/eq #0, r0
- bt 3f
-
- /*
- * If DBACEN == 1(DBSC was already enabled), we have to avoid the
- * initialization of DDR3-SDRAM.
- */
- bra exit_ddr
- nop
-
-3:
- /*------- DDR3IF -------*/
- /* oscillation stabilization time */
- wait_timer WAIT_OSC_TIME
-
- /* step 3 */
- write32 DBCMD_A, DBCMD_RSTL_VAL
- wait_timer WAIT_30US
-
- /* step 4 */
- write32 DBCMD_A, DBCMD_PDEN_VAL
-
- /* step 5 */
- write32 DBKIND_A, DBKIND_D
-
- /* step 6 */
- write32 DBCONF_A, DBCONF_D
- write32 DBTR0_A, DBTR0_D
- write32 DBTR1_A, DBTR1_D
- write32 DBTR2_A, DBTR2_D
- write32 DBTR3_A, DBTR3_D
- write32 DBTR4_A, DBTR4_D
- write32 DBTR5_A, DBTR5_D
- write32 DBTR6_A, DBTR6_D
- write32 DBTR7_A, DBTR7_D
- write32 DBTR8_A, DBTR8_D
- write32 DBTR9_A, DBTR9_D
- write32 DBTR10_A, DBTR10_D
- write32 DBTR11_A, DBTR11_D
- write32 DBTR12_A, DBTR12_D
- write32 DBTR13_A, DBTR13_D
- write32 DBTR14_A, DBTR14_D
- write32 DBTR15_A, DBTR15_D
- write32 DBTR16_A, DBTR16_D
- write32 DBTR17_A, DBTR17_D
- write32 DBTR18_A, DBTR18_D
- write32 DBTR19_A, DBTR19_D
- write32 DBRNK0_A, DBRNK0_D
-
- /* step 7 */
- write32 DBPDCNT3_A, DBPDCNT3_D
-
- /* step 8 */
- write32 DBPDCNT1_A, DBPDCNT1_D
- write32 DBPDCNT2_A, DBPDCNT2_D
- write32 DBPDLCK_A, DBPDLCK_D
- write32 DBPDRGA_A, DBPDRGA_D
- write32 DBPDRGD_A, DBPDRGD_D
-
- /* step 9 */
- wait_timer WAIT_30US
-
- /* step 10 */
- write32 DBPDCNT0_A, DBPDCNT0_D
-
- /* step 11 */
- wait_timer WAIT_30US
- wait_timer WAIT_30US
-
- /* step 12 */
- write32 DBCMD_A, DBCMD_WAIT_VAL
- wait_DBCMD
-
- /* step 13 */
- write32 DBCMD_A, DBCMD_RSTH_VAL
- wait_DBCMD
-
- /* step 14 */
- write32 DBCMD_A, DBCMD_WAIT_VAL
- write32 DBCMD_A, DBCMD_WAIT_VAL
- write32 DBCMD_A, DBCMD_WAIT_VAL
- write32 DBCMD_A, DBCMD_WAIT_VAL
-
- /* step 15 */
- write32 DBCMD_A, DBCMD_PDXT_VAL
-
- /* step 16 */
- write32 DBCMD_A, DBCMD_MRS2_VAL
-
- /* step 17 */
- write32 DBCMD_A, DBCMD_MRS3_VAL
-
- /* step 18 */
- write32 DBCMD_A, DBCMD_MRS1_VAL
-
- /* step 19 */
- write32 DBCMD_A, DBCMD_MRS0_VAL
-
- /* step 20 */
- write32 DBCMD_A, DBCMD_ZQCL_VAL
-
- write32 DBCMD_A, DBCMD_REF_VAL
- write32 DBCMD_A, DBCMD_REF_VAL
- wait_DBCMD
-
- /* step 21 */
- write32 DBADJ0_A, DBADJ0_D
- write32 DBADJ1_A, DBADJ1_D
- write32 DBADJ2_A, DBADJ2_D
-
- /* step 22 */
- write32 DBRFCNF0_A, DBRFCNF0_D
- write32 DBRFCNF1_A, DBRFCNF1_D
- write32 DBRFCNF2_A, DBRFCNF2_D
-
- /* step 23 */
- write32 DBCALCNF_A, DBCALCNF_D
-
- /* step 24 */
- write32 DBRFEN_A, DBRFEN_D
- write32 DBCMD_A, DBCMD_SRXT_VAL
-
- /* step 25 */
- write32 DBACEN_A, DBACEN_D
-
- /* step 26 */
- wait_DBCMD
-
-#if defined(CONFIG_SH7757LCR_DDR_ECC)
- /* enable DDR-ECC */
- write32 ECD_ECDEN_A, ECD_ECDEN_D
- write32 ECD_INTSR_A, ECD_INTSR_D
- write32 ECD_SPACER_A, ECD_SPACER_D
- write32 ECD_MCR_A, ECD_MCR_D
-#endif
- bra exit_ddr
- nop
-
- .align 4
-
-EXPEVT_A: .long 0xff000024
-EXPEVT_POWER_ON_RESET: .long 0x00000000
-
-/*------- DDR3IF -------*/
-DBCMD_A: .long 0xfe800018
-DBKIND_A: .long 0xfe800020
-DBCONF_A: .long 0xfe800024
-DBTR0_A: .long 0xfe800040
-DBTR1_A: .long 0xfe800044
-DBTR2_A: .long 0xfe800048
-DBTR3_A: .long 0xfe800050
-DBTR4_A: .long 0xfe800054
-DBTR5_A: .long 0xfe800058
-DBTR6_A: .long 0xfe80005c
-DBTR7_A: .long 0xfe800060
-DBTR8_A: .long 0xfe800064
-DBTR9_A: .long 0xfe800068
-DBTR10_A: .long 0xfe80006c
-DBTR11_A: .long 0xfe800070
-DBTR12_A: .long 0xfe800074
-DBTR13_A: .long 0xfe800078
-DBTR14_A: .long 0xfe80007c
-DBTR15_A: .long 0xfe800080
-DBTR16_A: .long 0xfe800084
-DBTR17_A: .long 0xfe800088
-DBTR18_A: .long 0xfe80008c
-DBTR19_A: .long 0xfe800090
-DBRNK0_A: .long 0xfe800100
-DBPDCNT0_A: .long 0xfe800200
-DBPDCNT1_A: .long 0xfe800204
-DBPDCNT2_A: .long 0xfe800208
-DBPDCNT3_A: .long 0xfe80020c
-DBPDLCK_A: .long 0xfe800280
-DBPDRGA_A: .long 0xfe800290
-DBPDRGD_A: .long 0xfe8002a0
-DBADJ0_A: .long 0xfe8000c0
-DBADJ1_A: .long 0xfe8000c4
-DBADJ2_A: .long 0xfe8000c8
-DBRFCNF0_A: .long 0xfe8000e0
-DBRFCNF1_A: .long 0xfe8000e4
-DBRFCNF2_A: .long 0xfe8000e8
-DBCALCNF_A: .long 0xfe8000f4
-DBRFEN_A: .long 0xfe800014
-DBACEN_A: .long 0xfe800010
-DBWAIT_A: .long 0xfe80001c
-
-WAIT_OSC_TIME: .long 6000
-WAIT_30US: .long 13333
-
-DBCMD_RSTL_VAL: .long 0x20000000
-DBCMD_PDEN_VAL: .long 0x1000d73c
-DBCMD_WAIT_VAL: .long 0x0000d73c
-DBCMD_RSTH_VAL: .long 0x2100d73c
-DBCMD_PDXT_VAL: .long 0x110000c8
-DBCMD_MRS0_VAL: .long 0x28000930
-DBCMD_MRS1_VAL: .long 0x29000004
-DBCMD_MRS2_VAL: .long 0x2a000008
-DBCMD_MRS3_VAL: .long 0x2b000000
-DBCMD_ZQCL_VAL: .long 0x03000200
-DBCMD_REF_VAL: .long 0x0c000000
-DBCMD_SRXT_VAL: .long 0x19000000
-DBKIND_D: .long 0x00000007
-DBCONF_D: .long 0x0f030a01
-DBTR0_D: .long 0x00000007
-DBTR1_D: .long 0x00000006
-DBTR2_D: .long 0x00000000
-DBTR3_D: .long 0x00000007
-DBTR4_D: .long 0x00070007
-DBTR5_D: .long 0x0000001b
-DBTR6_D: .long 0x00000014
-DBTR7_D: .long 0x00000005
-DBTR8_D: .long 0x00000015
-DBTR9_D: .long 0x00000006
-DBTR10_D: .long 0x00000008
-DBTR11_D: .long 0x00000007
-DBTR12_D: .long 0x0000000e
-DBTR13_D: .long 0x00000056
-DBTR14_D: .long 0x00000006
-DBTR15_D: .long 0x00000004
-DBTR16_D: .long 0x00150002
-DBTR17_D: .long 0x000c0017
-DBTR18_D: .long 0x00000200
-DBTR19_D: .long 0x00000040
-DBRNK0_D: .long 0x00000001
-DBPDCNT0_D: .long 0x00000001
-DBPDCNT1_D: .long 0x00000001
-DBPDCNT2_D: .long 0x00000000
-DBPDCNT3_D: .long 0x00004010
-DBPDLCK_D: .long 0x0000a55a
-DBPDRGA_D: .long 0x00000028
-DBPDRGD_D: .long 0x00017100
-
-DBADJ0_D: .long 0x00000000
-DBADJ1_D: .long 0x00000000
-DBADJ2_D: .long 0x18061806
-DBRFCNF0_D: .long 0x000001ff
-DBRFCNF1_D: .long 0x08001000
-DBRFCNF2_D: .long 0x00000000
-DBCALCNF_D: .long 0x0000ffff
-DBRFEN_D: .long 0x00000001
-DBACEN_D: .long 0x00000001
-
-/*------- DDR-ECC -------*/
-ECD_ECDEN_A: .long 0xffc1012c
-ECD_ECDEN_D: .long 0x00000001
-ECD_INTSR_A: .long 0xfe900024
-ECD_INTSR_D: .long 0xffffffff
-ECD_SPACER_A: .long 0xfe900018
-ECD_SPACER_D: .long SH7757LCR_SDRAM_ECC_SETTING
-ECD_MCR_A: .long 0xfe900010
-ECD_MCR_D: .long 0x00000001
-
- .align 2
-exit_ddr:
-
-#if defined(CONFIG_SH_32BIT)
- /*------- set PMB -------*/
- write32 PASCR_A, PASCR_29BIT_D
- write32 MMUCR_A, MMUCR_D
-
- /*****************************************************************
- * ent virt phys v sz c wt
- * 0 0xa0000000 0x00000000 1 128M 0 1
- * 1 0xa8000000 0x48000000 1 128M 0 1
- * 5 0x88000000 0x48000000 1 128M 1 1
- */
- write32 PMB_ADDR_SPIBOOT_A, PMB_ADDR_SPIBOOT_D
- write32 PMB_DATA_SPIBOOT_A, PMB_DATA_SPIBOOT_D
- write32 PMB_ADDR_DDR_C1_A, PMB_ADDR_DDR_C1_D
- write32 PMB_DATA_DDR_C1_A, PMB_DATA_DDR_C1_D
- write32 PMB_ADDR_DDR_N1_A, PMB_ADDR_DDR_N1_D
- write32 PMB_DATA_DDR_N1_A, PMB_DATA_DDR_N1_D
-
- write32 PMB_ADDR_ENTRY2, PMB_ADDR_NOT_USE_D
- write32 PMB_ADDR_ENTRY3, PMB_ADDR_NOT_USE_D
- write32 PMB_ADDR_ENTRY4, PMB_ADDR_NOT_USE_D
- write32 PMB_ADDR_ENTRY6, PMB_ADDR_NOT_USE_D
- write32 PMB_ADDR_ENTRY7, PMB_ADDR_NOT_USE_D
- write32 PMB_ADDR_ENTRY8, PMB_ADDR_NOT_USE_D
- write32 PMB_ADDR_ENTRY9, PMB_ADDR_NOT_USE_D
- write32 PMB_ADDR_ENTRY10, PMB_ADDR_NOT_USE_D
- write32 PMB_ADDR_ENTRY11, PMB_ADDR_NOT_USE_D
- write32 PMB_ADDR_ENTRY12, PMB_ADDR_NOT_USE_D
- write32 PMB_ADDR_ENTRY13, PMB_ADDR_NOT_USE_D
- write32 PMB_ADDR_ENTRY14, PMB_ADDR_NOT_USE_D
- write32 PMB_ADDR_ENTRY15, PMB_ADDR_NOT_USE_D
-
- write32 PASCR_A, PASCR_INIT
- mov.l DUMMY_ADDR, r0
- icbi @r0
-#endif /* if defined(CONFIG_SH_32BIT) */
-
-exit_pmb:
- /* CPU is running on ILRAM? */
- mov r14, r0
- tst #1, r0
- bt 1f
-
- mov.l _bss_start, r15
- mov.l _spiboot_main, r0
-100: bsrf r0
- nop
-
- .align 2
-_spiboot_main: .long (spiboot_main - (100b + 4))
-_bss_start: .long bss_start
-
-1:
-
- write32 CCR_A, CCR_D
-
- rts
- nop
-
- .align 4
-
-#if defined(CONFIG_SH_32BIT)
-/*------- set PMB -------*/
-PMB_ADDR_SPIBOOT_A: .long PMB_ADDR_BASE(0)
-PMB_ADDR_DDR_N1_A: .long PMB_ADDR_BASE(1)
-PMB_ADDR_DDR_C1_A: .long PMB_ADDR_BASE(5)
-PMB_ADDR_ENTRY2: .long PMB_ADDR_BASE(2)
-PMB_ADDR_ENTRY3: .long PMB_ADDR_BASE(3)
-PMB_ADDR_ENTRY4: .long PMB_ADDR_BASE(4)
-PMB_ADDR_ENTRY6: .long PMB_ADDR_BASE(6)
-PMB_ADDR_ENTRY7: .long PMB_ADDR_BASE(7)
-PMB_ADDR_ENTRY8: .long PMB_ADDR_BASE(8)
-PMB_ADDR_ENTRY9: .long PMB_ADDR_BASE(9)
-PMB_ADDR_ENTRY10: .long PMB_ADDR_BASE(10)
-PMB_ADDR_ENTRY11: .long PMB_ADDR_BASE(11)
-PMB_ADDR_ENTRY12: .long PMB_ADDR_BASE(12)
-PMB_ADDR_ENTRY13: .long PMB_ADDR_BASE(13)
-PMB_ADDR_ENTRY14: .long PMB_ADDR_BASE(14)
-PMB_ADDR_ENTRY15: .long PMB_ADDR_BASE(15)
-
-PMB_ADDR_SPIBOOT_D: .long mk_pmb_addr_val(0xa0)
-PMB_ADDR_DDR_C1_D: .long mk_pmb_addr_val(0x88)
-PMB_ADDR_DDR_N1_D: .long mk_pmb_addr_val(0xa8)
-PMB_ADDR_NOT_USE_D: .long 0x00000000
-
-PMB_DATA_SPIBOOT_A: .long PMB_DATA_BASE(0)
-PMB_DATA_DDR_N1_A: .long PMB_DATA_BASE(1)
-PMB_DATA_DDR_C1_A: .long PMB_DATA_BASE(5)
-
-/* ppn ub v s1 s0 c wt */
-PMB_DATA_SPIBOOT_D: .long mk_pmb_data_val(0x00, 0, 1, 1, 0, 0, 1)
-PMB_DATA_DDR_C1_D: .long mk_pmb_data_val(0x48, 0, 1, 1, 0, 1, 1)
-PMB_DATA_DDR_N1_D: .long mk_pmb_data_val(0x48, 1, 1, 1, 0, 0, 1)
-
-PASCR_A: .long 0xff000070
-DUMMY_ADDR: .long 0xa0000000
-PASCR_29BIT_D: .long 0x00000000
-PASCR_INIT: .long 0x80000080
-MMUCR_A: .long 0xff000010
-MMUCR_D: .long 0x00000004 /* clear ITLB */
-#endif /* CONFIG_SH_32BIT */
-
-CCR_A: .long CCR
-CCR_D: .long CCR_CACHE_INIT
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2011 Renesas Solutions Corp.
- */
-
-#include <common.h>
-#include <command.h>
-#include <env.h>
-#include <flash.h>
-#include <init.h>
-#include <malloc.h>
-#include <net.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <asm/mmc.h>
-#include <spi.h>
-#include <spi_flash.h>
-
-int checkboard(void)
-{
- puts("BOARD: R0P7757LC0030RL board\n");
-
- return 0;
-}
-
-static void init_gctrl(void)
-{
- struct gctrl_regs *gctrl = GCTRL_BASE;
- unsigned long graofst;
-
- graofst = (SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_GRA_OFFSET) >> 24;
- writel(graofst | 0x20000f00, &gctrl->gracr3);
-}
-
-static int init_pcie_bridge_from_spi(void *buf, size_t size)
-{
-#ifdef CONFIG_DEPRECATED
- struct spi_flash *spi;
- int ret;
- unsigned long pcie_addr;
-
- spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
- if (!spi) {
- printf("%s: spi_flash probe error.\n", __func__);
- return 1;
- }
-
- if (is_sh7757_b0())
- pcie_addr = SH7757LCR_PCIEBRG_ADDR_B0;
- else
- pcie_addr = SH7757LCR_PCIEBRG_ADDR;
-
- ret = spi_flash_read(spi, pcie_addr, size, buf);
- if (ret) {
- printf("%s: spi_flash read error.\n", __func__);
- spi_flash_free(spi);
- return 1;
- }
- spi_flash_free(spi);
-
- return 0;
-#else
- printf("No SPI support so no PCIe support\n");
- return 1;
-#endif
-}
-
-static void init_pcie_bridge(void)
-{
- struct pciebrg_regs *pciebrg = PCIEBRG_BASE;
- struct pcie_setup_regs *pcie_setup = PCIE_SETUP_BASE;
- int i;
- unsigned char *data;
- unsigned short tmp;
- unsigned long pcie_size;
-
- if (!(readw(&pciebrg->ctrl_h8s) & 0x0001))
- return;
-
- if (is_sh7757_b0())
- pcie_size = SH7757LCR_PCIEBRG_SIZE_B0;
- else
- pcie_size = SH7757LCR_PCIEBRG_SIZE;
-
- data = malloc(pcie_size);
- if (!data) {
- printf("%s: malloc error.\n", __func__);
- return;
- }
- if (init_pcie_bridge_from_spi(data, pcie_size)) {
- free(data);
- return;
- }
-
- if (data[0] == 0xff && data[1] == 0xff && data[2] == 0xff &&
- data[3] == 0xff) {
- free(data);
- printf("%s: skipped initialization\n", __func__);
- return;
- }
-
- writew(0xa501, &pciebrg->ctrl_h8s); /* reset */
- writew(0x0000, &pciebrg->cp_ctrl);
- writew(0x0000, &pciebrg->cp_addr);
-
- for (i = 0; i < pcie_size; i += 2) {
- tmp = (data[i] << 8) | data[i + 1];
- writew(tmp, &pciebrg->cp_data);
- }
-
- writew(0xa500, &pciebrg->ctrl_h8s); /* start */
- if (!is_sh7757_b0())
- writel(0x00000001, &pcie_setup->pbictl3);
-
- free(data);
-}
-
-static void init_usb_phy(void)
-{
- struct usb_common_regs *common0 = USB0_COMMON_BASE;
- struct usb_common_regs *common1 = USB1_COMMON_BASE;
- struct usb0_phy_regs *phy = USB0_PHY_BASE;
- struct usb1_port_regs *port = USB1_PORT_BASE;
- struct usb1_alignment_regs *align = USB1_ALIGNMENT_BASE;
-
- writew(0x0100, &phy->reset); /* set reset */
- /* port0 = USB0, port1 = USB1 */
- writew(0x0002, &phy->portsel);
- writel(0x0001, &port->port1sel); /* port1 = Host */
- writew(0x0111, &phy->reset); /* clear reset */
-
- writew(0x4000, &common0->suspmode);
- writew(0x4000, &common1->suspmode);
-
-#if defined(__LITTLE_ENDIAN)
- writel(0x00000000, &align->ehcidatac);
- writel(0x00000000, &align->ohcidatac);
-#endif
-}
-
-static void set_mac_to_sh_eth_register(int channel, char *mac_string)
-{
- struct ether_mac_regs *ether;
- unsigned char mac[6];
- unsigned long val;
-
- string_to_enetaddr(mac_string, mac);
-
- if (!channel)
- ether = ETHER0_MAC_BASE;
- else
- ether = ETHER1_MAC_BASE;
-
- val = (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3];
- writel(val, ðer->mahr);
- val = (mac[4] << 8) | mac[5];
- writel(val, ðer->malr);
-}
-
-static void set_mac_to_sh_giga_eth_register(int channel, char *mac_string)
-{
- struct ether_mac_regs *ether;
- unsigned char mac[6];
- unsigned long val;
-
- string_to_enetaddr(mac_string, mac);
-
- if (!channel)
- ether = GETHER0_MAC_BASE;
- else
- ether = GETHER1_MAC_BASE;
-
- val = (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3];
- writel(val, ðer->mahr);
- val = (mac[4] << 8) | mac[5];
- writel(val, ðer->malr);
-}
-
-/*****************************************************************
- * This PMB must be set on this timing. The lowlevel_init is run on
- * Area 0(phys 0x00000000), so we have to map it.
- *
- * The new PMB table is following:
- * ent virt phys v sz c wt
- * 0 0xa0000000 0x40000000 1 128M 0 1
- * 1 0xa8000000 0x48000000 1 128M 0 1
- * 2 0xb0000000 0x50000000 1 128M 0 1
- * 3 0xb8000000 0x58000000 1 128M 0 1
- * 4 0x80000000 0x40000000 1 128M 1 1
- * 5 0x88000000 0x48000000 1 128M 1 1
- * 6 0x90000000 0x50000000 1 128M 1 1
- * 7 0x98000000 0x58000000 1 128M 1 1
- */
-static void set_pmb_on_board_init(void)
-{
- struct mmu_regs *mmu = MMU_BASE;
-
- /* clear ITLB */
- writel(0x00000004, &mmu->mmucr);
-
- /* delete PMB for SPIBOOT */
- writel(0, PMB_ADDR_BASE(0));
- writel(0, PMB_DATA_BASE(0));
-
- /* add PMB for SDRAM(0x40000000 - 0x47ffffff) */
- /* ppn ub v s1 s0 c wt */
- writel(mk_pmb_addr_val(0xa0), PMB_ADDR_BASE(0));
- writel(mk_pmb_data_val(0x40, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(0));
- writel(mk_pmb_addr_val(0xb0), PMB_ADDR_BASE(2));
- writel(mk_pmb_data_val(0x50, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(2));
- writel(mk_pmb_addr_val(0xb8), PMB_ADDR_BASE(3));
- writel(mk_pmb_data_val(0x58, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(3));
- writel(mk_pmb_addr_val(0x80), PMB_ADDR_BASE(4));
- writel(mk_pmb_data_val(0x40, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(4));
- writel(mk_pmb_addr_val(0x90), PMB_ADDR_BASE(6));
- writel(mk_pmb_data_val(0x50, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(6));
- writel(mk_pmb_addr_val(0x98), PMB_ADDR_BASE(7));
- writel(mk_pmb_data_val(0x58, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(7));
-}
-
-int board_init(void)
-{
- struct gether_control_regs *gether = GETHER_CONTROL_BASE;
-
- set_pmb_on_board_init();
-
- /* enable RMII's MDIO (disable GRMII's MDIO) */
- writel(0x00030000, &gether->gbecont);
-
- init_gctrl();
- init_usb_phy();
-
- return 0;
-}
-
-int board_mmc_init(struct bd_info *bis)
-{
- return mmcif_mmc_init();
-}
-
-static int get_sh_eth_mac_raw(unsigned char *buf, int size)
-{
-#ifdef CONFIG_DEPRECATED
- struct spi_flash *spi;
- int ret;
-
- spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
- if (spi == NULL) {
- printf("%s: spi_flash probe error.\n", __func__);
- return 1;
- }
-
- ret = spi_flash_read(spi, SH7757LCR_ETHERNET_MAC_BASE, size, buf);
- if (ret) {
- printf("%s: spi_flash read error.\n", __func__);
- spi_flash_free(spi);
- return 1;
- }
- spi_flash_free(spi);
-#endif
-
- return 0;
-}
-
-static int get_sh_eth_mac(int channel, char *mac_string, unsigned char *buf)
-{
- memcpy(mac_string, &buf[channel * (SH7757LCR_ETHERNET_MAC_SIZE + 1)],
- SH7757LCR_ETHERNET_MAC_SIZE);
- mac_string[SH7757LCR_ETHERNET_MAC_SIZE] = 0x00; /* terminate */
-
- return 0;
-}
-
-static void init_ethernet_mac(void)
-{
- char mac_string[64];
- char env_string[64];
- int i;
- unsigned char *buf;
-
- buf = malloc(256);
- if (!buf) {
- printf("%s: malloc error.\n", __func__);
- return;
- }
- get_sh_eth_mac_raw(buf, 256);
-
- /* Fast Ethernet */
- for (i = 0; i < SH7757LCR_ETHERNET_NUM_CH; i++) {
- get_sh_eth_mac(i, mac_string, buf);
- if (i == 0)
- env_set("ethaddr", mac_string);
- else {
- sprintf(env_string, "eth%daddr", i);
- env_set(env_string, mac_string);
- }
-
- set_mac_to_sh_eth_register(i, mac_string);
- }
-
- /* Gigabit Ethernet */
- for (i = 0; i < SH7757LCR_GIGA_ETHERNET_NUM_CH; i++) {
- get_sh_eth_mac(i + SH7757LCR_ETHERNET_NUM_CH, mac_string, buf);
- sprintf(env_string, "eth%daddr", i + SH7757LCR_ETHERNET_NUM_CH);
- env_set(env_string, mac_string);
-
- set_mac_to_sh_giga_eth_register(i, mac_string);
- }
-
- free(buf);
-}
-
-static void init_pcie(void)
-{
- struct pcie_setup_regs *pcie_setup = PCIE_SETUP_BASE;
- struct pcie_system_bus_regs *pcie_sysbus = PCIE_SYSTEM_BUS_BASE;
-
- writel(0x00000ff2, &pcie_setup->ladmsk0);
- writel(0x00000001, &pcie_setup->barmap);
- writel(0xffcaa000, &pcie_setup->lad0);
- writel(0x00030000, &pcie_sysbus->endictl0);
- writel(0x00000003, &pcie_sysbus->endictl1);
- writel(0x00000004, &pcie_setup->pbictl2);
-}
-
-static void finish_spiboot(void)
-{
- struct gctrl_regs *gctrl = GCTRL_BASE;
- /*
- * SH7757 B0 does not use LBSC.
- * So if we set SPIBOOTCAN to 1, SH7757 can not access Area0.
- * This setting is not cleared by manual reset, So we have to set it
- * to 0.
- */
- writel(0x00000000, &gctrl->spibootcan);
-}
-
-int board_late_init(void)
-{
- init_ethernet_mac();
- init_pcie_bridge();
- init_pcie();
- finish_spiboot();
-
- return 0;
-}
-
-int do_sh_g200(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
-{
- struct gctrl_regs *gctrl = GCTRL_BASE;
- unsigned long graofst;
-
- writel(0xfedcba98, &gctrl->wprotect);
- graofst = (SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_GRA_OFFSET) >> 24;
- writel(graofst | 0xa0000f00, &gctrl->gracr3);
-
- return 0;
-}
-
-U_BOOT_CMD(
- sh_g200, 1, 1, do_sh_g200,
- "enable sh-g200",
- "enable SH-G200 bus (disable PCIe-G200)"
-);
-
-#ifdef CONFIG_DEPRECATED
-int do_write_mac(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
-{
- int i, ret;
- char mac_string[256];
- struct spi_flash *spi;
- unsigned char *buf;
-
- if (argc != 5) {
- buf = malloc(256);
- if (!buf) {
- printf("%s: malloc error.\n", __func__);
- return 1;
- }
-
- get_sh_eth_mac_raw(buf, 256);
-
- /* print current MAC address */
- for (i = 0; i < 4; i++) {
- get_sh_eth_mac(i, mac_string, buf);
- if (i < 2)
- printf(" ETHERC ch%d = %s\n", i, mac_string);
- else
- printf("GETHERC ch%d = %s\n", i-2, mac_string);
- }
- free(buf);
- return 0;
- }
-
- /* new setting */
- memset(mac_string, 0xff, sizeof(mac_string));
- sprintf(mac_string, "%s\t%s\t%s\t%s",
- argv[1], argv[2], argv[3], argv[4]);
-
- /* write MAC data to SPI rom */
- spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
- if (!spi) {
- printf("%s: spi_flash probe error.\n", __func__);
- return 1;
- }
-
- ret = spi_flash_erase(spi, SH7757LCR_ETHERNET_MAC_BASE_SPI,
- SH7757LCR_SPI_SECTOR_SIZE);
- if (ret) {
- printf("%s: spi_flash erase error.\n", __func__);
- return 1;
- }
-
- ret = spi_flash_write(spi, SH7757LCR_ETHERNET_MAC_BASE_SPI,
- sizeof(mac_string), mac_string);
- if (ret) {
- printf("%s: spi_flash write error.\n", __func__);
- spi_flash_free(spi);
- return 1;
- }
- spi_flash_free(spi);
-
- puts("The writing of the MAC address to SPI ROM was completed.\n");
-
- return 0;
-}
-
-U_BOOT_CMD(
- write_mac, 5, 1, do_write_mac,
- "write MAC address for ETHERC/GETHERC",
- "[ETHERC ch0] [ETHERC ch1] [GETHERC ch0] [GETHERC ch1]\n"
-);
-#endif
+++ /dev/null
-/*
- * Copyright (C) 2011 Renesas Solutions Corp.
- *
- * This file is subject to the terms and conditions of the GNU Lesser
- * General Public License. See the file "COPYING.LIB" in the main
- * directory of this archive for more details.
- */
-
-#include <common.h>
-
-#define CONFIG_RAM_BOOT_PHYS 0x4ef80000
-#if defined(CONFIG_SH7757_OFFSET_SPI)
-#define CONFIG_SPI_ADDR 0x00010000
-#else
-#define CONFIG_SPI_ADDR 0x00000000
-#endif
-#define CONFIG_SPI_LENGTH 0x00030000
-#define CONFIG_RAM_BOOT 0x8ef80000
-
-#define SPIWDMADR 0xFE001018
-#define SPIWDMCNTR 0xFE001020
-#define SPIDMCOR 0xFE001028
-#define SPIDMINTSR 0xFE001188
-#define SPIDMINTMR 0xFE001190
-
-#define SPIDMINTSR_DMEND 0x00000004
-
-#define TBR 0xFE002000
-#define RBR 0xFE002000
-
-#define CR1 0xFE002008
-#define CR2 0xFE002010
-#define CR3 0xFE002018
-#define CR4 0xFE002020
-
-/* CR1 */
-#define SPI_TBE 0x80
-#define SPI_TBF 0x40
-#define SPI_RBE 0x20
-#define SPI_RBF 0x10
-#define SPI_PFONRD 0x08
-#define SPI_SSDB 0x04
-#define SPI_SSD 0x02
-#define SPI_SSA 0x01
-
-/* CR2 */
-#define SPI_RSTF 0x80
-#define SPI_LOOPBK 0x40
-#define SPI_CPOL 0x20
-#define SPI_CPHA 0x10
-#define SPI_L1M0 0x08
-
-/* CR4 */
-#define SPI_TBEI 0x80
-#define SPI_TBFI 0x40
-#define SPI_RBEI 0x20
-#define SPI_RBFI 0x10
-#define SPI_SSS 0x01
-
-#define spi_write(val, addr) (*(volatile unsigned long *)(addr)) = val
-#define spi_read(addr) (*(volatile unsigned long *)(addr))
-
-/* M25P80 */
-#define M25_READ 0x03
-
-#define __uses_spiboot2 __attribute__((section(".spiboot2.text")))
-static void __uses_spiboot2 spi_reset(void)
-{
- spi_write(0xfe, CR1);
-
- spi_write(0, SPIDMCOR);
- spi_write(0x00, CR1);
-
- spi_write(spi_read(CR2) | SPI_RSTF, CR2); /* fifo reset */
- spi_write(spi_read(CR2) & ~SPI_RSTF, CR2);
-}
-
-static void __uses_spiboot2 spi_read_flash(void *buf, unsigned long addr,
- unsigned long len)
-{
- spi_write(M25_READ, TBR);
- spi_write((addr >> 16) & 0xFF, TBR);
- spi_write((addr >> 8) & 0xFF, TBR);
- spi_write(addr & 0xFF, TBR);
-
- spi_write(SPIDMINTSR_DMEND, SPIDMINTSR);
- spi_write((unsigned long)buf, SPIWDMADR);
- spi_write(len & 0xFFFFFFE0, SPIWDMCNTR);
- spi_write(1, SPIDMCOR);
-
- spi_write(0xff, CR3);
- spi_write(spi_read(CR1) | SPI_SSDB, CR1);
- spi_write(spi_read(CR1) | SPI_SSA, CR1);
-
- while (!(spi_read(SPIDMINTSR) & SPIDMINTSR_DMEND))
- ;
-}
-
-void __uses_spiboot2 spiboot_main(void)
-{
- void (*_start)(void) = (void *)CONFIG_SYS_TEXT_BASE;
-
- spi_reset();
- spi_read_flash((void *)CONFIG_RAM_BOOT_PHYS, CONFIG_SPI_ADDR,
- CONFIG_SPI_LENGTH);
-
- _start();
-}
+++ /dev/null
-if TARGET_SH7763RDP
-
-config SYS_BOARD
- default "sh7763rdp"
-
-config SYS_VENDOR
- default "renesas"
-
-config SYS_CONFIG_NAME
- default "sh7763rdp"
-
-endif
+++ /dev/null
-SH7763RDP BOARD
-M: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
-M: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
-S: Maintained
-F: board/renesas/sh7763rdp/
-F: include/configs/sh7763rdp.h
-F: configs/sh7763rdp_defconfig
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (C) 2008 Renesas Solutions Corp.
-# Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
-# Copyright (C) 2007 Kenati Technologies, Inc.
-#
-# board/sh7763rdp/Makefile
-
-obj-y := sh7763rdp.o
-extra-y += lowlevel_init.o
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2008 Renesas Solutions Corp.
- * Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
- * Copyright (C) 2007 Kenati Technologies, Inc.
- *
- * board/sh7763rdp/lowlevel_init.S
- */
-
-#include <config.h>
-
-#include <asm/processor.h>
-#include <asm/macro.h>
-
- .global lowlevel_init
-
- .text
- .align 2
-
-lowlevel_init:
-
- write32 WDTCSR_A, WDTCSR_D /* Watchdog Control / Status Register */
-
- write32 WDTST_A, WDTST_D /* Watchdog Stop Time Register */
-
- write32 WDTBST_A, WDTBST_D /*
- * 0xFFCC0008
- * Watchdog Base Stop Time Register
- */
-
- write32 CCR_A, CCR_CACHE_ICI_D /* Address of Cache Control Register */
- /* Instruction Cache Invalidate */
-
- write32 MMUCR_A, MMU_CONTROL_TI_D /* MMU Control Register */
- /* TI == TLB Invalidate bit */
-
- write32 MSTPCR0_A, MSTPCR0_D /* Address of Power Control Register 0 */
-
- write32 MSTPCR1_A, MSTPCR1_D /* Address of Power Control Register 1 */
-
- write32 RAMCR_A, RAMCR_D
-
- mov.l MMSELR_A, r1
- mov.l MMSELR_D, r0
- synco
- mov.l r0, @r1
-
- mov.l @r1, r2 /* execute two reads after setting MMSELR */
- mov.l @r1, r2
- synco
-
- /* issue memory read */
- mov.l DDRSD_START_A, r1 /* memory address to read*/
- mov.l @r1, r0
- synco
-
- write32 MIM8_A, MIM8_D
-
- write32 MIMC_A, MIMC_D1
-
- write32 STRC_A, STRC_D
-
- write32 SDR4_A, SDR4_D
-
- write32 MIMC_A, MIMC_D2
-
- nop
- nop
- nop
-
- write32 SCR4_A, SCR4_D3
-
- write32 SCR4_A, SCR4_D2
-
- write32 SDMR02000_A, SDMR02000_D
-
- write32 SDMR00B08_A, SDMR00B08_D
-
- write32 SCR4_A, SCR4_D2
-
- write32 SCR4_A, SCR4_D4
-
- nop
- nop
- nop
- nop
-
- write32 SCR4_A, SCR4_D4
-
- nop
- nop
- nop
- nop
-
- write32 SDMR00308_A, SDMR00308_D
-
- write32 MIMC_A, MIMC_D3
-
- mov.l SCR4_A, r1
- mov.l SCR4_D1, r0
- mov.l DELAY60_D, r3
-
-delay_loop_60:
- mov.l r0, @r1
- dt r3
- bf delay_loop_60
- nop
-
- write32 CCR_A, CCR_CACHE_D_2 /* Address of Cache Control Register */
-
-bsc_init:
- write32 BCR_A, BCR_D
-
- write32 CS0BCR_A, CS0BCR_D
-
- write32 CS1BCR_A, CS1BCR_D
-
- write32 CS2BCR_A, CS2BCR_D
-
- write32 CS4BCR_A, CS4BCR_D
-
- write32 CS5BCR_A, CS5BCR_D
-
- write32 CS6BCR_A, CS6BCR_D
-
- write32 CS0WCR_A, CS0WCR_D
-
- write32 CS1WCR_A, CS1WCR_D
-
- write32 CS2WCR_A, CS2WCR_D
-
- write32 CS4WCR_A, CS4WCR_D
-
- write32 CS5WCR_A, CS5WCR_D
-
- write32 CS6WCR_A, CS6WCR_D
-
- write32 CS5PCR_A, CS5PCR_D
-
- write32 CS6PCR_A, CS6PCR_D
-
- mov.l DELAY200_D, r3
-
-delay_loop_200:
- dt r3
- bf delay_loop_200
- nop
-
- write16 PSEL0_A, PSEL0_D
-
- write16 PSEL1_A, PSEL1_D
-
- write32 ICR0_A, ICR0_D
-
- stc sr, r0 /* BL bit off(init=ON) */
- mov.l SR_MASK_D, r1
- and r1, r0
- ldc r0, sr
-
- rts
- nop
-
- .align 2
-
-DELAY60_D: .long 60
-DELAY200_D: .long 17800
-
-CCR_A: .long 0xFF00001C
-MMUCR_A: .long 0xFF000010
-RAMCR_A: .long 0xFF000074
-
-/* Low power mode control */
-MSTPCR0_A: .long 0xFFC80030
-MSTPCR1_A: .long 0xFFC80038
-
-/* RWBT */
-WDTST_A: .long 0xFFCC0000
-WDTCSR_A: .long 0xFFCC0004
-WDTBST_A: .long 0xFFCC0008
-
-/* BSC */
-MMSELR_A: .long 0xFE600020
-BCR_A: .long 0xFF801000
-CS0BCR_A: .long 0xFF802000
-CS1BCR_A: .long 0xFF802010
-CS2BCR_A: .long 0xFF802020
-CS4BCR_A: .long 0xFF802040
-CS5BCR_A: .long 0xFF802050
-CS6BCR_A: .long 0xFF802060
-CS0WCR_A: .long 0xFF802008
-CS1WCR_A: .long 0xFF802018
-CS2WCR_A: .long 0xFF802028
-CS4WCR_A: .long 0xFF802048
-CS5WCR_A: .long 0xFF802058
-CS6WCR_A: .long 0xFF802068
-CS5PCR_A: .long 0xFF802070
-CS6PCR_A: .long 0xFF802080
-DDRSD_START_A: .long 0xAC000000
-
-/* INTC */
-ICR0_A: .long 0xFFD00000
-
-/* DDR I/F */
-MIM8_A: .long 0xFE800008
-MIMC_A: .long 0xFE80000C
-SCR4_A: .long 0xFE800014
-STRC_A: .long 0xFE80001C
-SDR4_A: .long 0xFE800034
-SDMR00308_A: .long 0xFE900308
-SDMR00B08_A: .long 0xFE900B08
-SDMR02000_A: .long 0xFE902000
-
-/* GPIO */
-PSEL0_A: .long 0xFFEF0070
-PSEL1_A: .long 0xFFEF0072
-
-CCR_CACHE_ICI_D:.long 0x00000800
-CCR_CACHE_D_2: .long 0x00000103
-MMU_CONTROL_TI_D:.long 0x00000004
-RAMCR_D: .long 0x00000200
-MSTPCR0_D: .long 0x00000000
-MSTPCR1_D: .long 0x00000000
-
-MMSELR_D: .long 0xa5a50000
-BCR_D: .long 0x00000000
-CS0BCR_D: .long 0x77777770
-CS1BCR_D: .long 0x77777670
-CS2BCR_D: .long 0x77777670
-CS4BCR_D: .long 0x77777670
-CS5BCR_D: .long 0x77777670
-CS6BCR_D: .long 0x77777670
-CS0WCR_D: .long 0x7777770F
-CS1WCR_D: .long 0x22000002
-CS2WCR_D: .long 0x7777770F
-CS4WCR_D: .long 0x7777770F
-CS5WCR_D: .long 0x7777770F
-CS6WCR_D: .long 0x7777770F
-CS5PCR_D: .long 0x77000000
-CS6PCR_D: .long 0x77000000
-ICR0_D: .long 0x00E00000
-MIM8_D: .long 0x00000000
-MIMC_D1: .long 0x01d10008
-MIMC_D2: .long 0x01d10009
-MIMC_D3: .long 0x01d10209
-SCR4_D1: .long 0x00000001
-SCR4_D2: .long 0x00000002
-SCR4_D3: .long 0x00000003
-SCR4_D4: .long 0x00000004
-STRC_D: .long 0x000f3980
-SDR4_D: .long 0x00000300
-SDMR00308_D: .long 0x00000000
-SDMR00B08_D: .long 0x00000000
-SDMR02000_D: .long 0x00000000
-PSEL0_D: .word 0x00000001
-PSEL1_D: .word 0x00000244
-SR_MASK_D: .long 0xEFFFFF0F
-WDTST_D: .long 0x5A000FFF
-WDTCSR_D: .long 0xA5000000
-WDTBST_D: .long 0x55000000
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2008 Renesas Solutions Corp.
- * Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
- * Copyright (C) 2007 Kenati Technologies, Inc.
- *
- * board/sh7763rdp/sh7763rdp.c
- */
-
-#include <common.h>
-#include <init.h>
-#include <asm/io.h>
-#include <asm/processor.h>
-
-#define CPU_CMDREG 0xB1000006
-#define PDCR 0xffef0006
-#define PECR 0xffef0008
-#define PFCR 0xffef000a
-#define PGCR 0xffef000c
-#define PHCR 0xffef000e
-#define PJCR 0xffef0012
-#define PKCR 0xffef0014
-#define PLCR 0xffef0016
-#define PMCR 0xffef0018
-#define PSEL1 0xffef0072
-#define PSEL2 0xffef0074
-#define PSEL3 0xffef0076
-
-int checkboard(void)
-{
- puts("BOARD: Renesas SH7763 RDP\n");
- return 0;
-}
-
-int board_init(void)
-{
- vu_short dat;
-
- /* Enable mode */
- writew(inw(CPU_CMDREG)|0x0001, CPU_CMDREG);
-
- /* GPIO Setting (eth1) */
- dat = inw(PSEL1);
- writew(((dat & ~0xff00) | 0x2400), PSEL1);
- writew(0, PFCR);
- writew(0, PGCR);
- writew(0, PHCR);
-
- return 0;
-}
-
-void led_set_state(unsigned short value)
-{
-}
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xFFF80000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_MPC85xx=y
-# CONFIG_CMD_ERRATA is not set
-CONFIG_TARGET_MPC8544DS=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-# CONFIG_CONSOLE_MUX is not set
-# CONFIG_MISC_INIT_R is not set
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_REGINFO=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_EXT2=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xFFF70000
-CONFIG_SCSI_AHCI=y
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_RTL8139=y
-CONFIG_TSEC_ENET=y
-CONFIG_SCSI=y
-CONFIG_SYS_NS16550=y
-CONFIG_USB=y
-CONFIG_USB_EHCI_PCI=y
-CONFIG_USB_STORAGE=y
-CONFIG_VIDEO=y
-CONFIG_OF_LIBFDT=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_MPC8572DS=y
-CONFIG_PHYS_64BIT=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-# CONFIG_CONSOLE_MUX is not set
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_MISC_INIT_R is not set
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_REGINFO=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_EXT2=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_ADDR=0xEFF20000
-CONFIG_SCSI_AHCI=y
-CONFIG_SYS_FSL_DDR2=y
-# CONFIG_MMC is not set
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_USB=y
-CONFIG_USB_EHCI_PCI=y
-CONFIG_USB_STORAGE=y
-CONFIG_VIDEO=y
-CONFIG_ADDR_MAP=y
-CONFIG_OF_LIBFDT=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_MPC8572DS=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-# CONFIG_CONSOLE_MUX is not set
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_MISC_INIT_R is not set
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_REGINFO=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_EXT2=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_ADDR=0xEFF20000
-CONFIG_SCSI_AHCI=y
-CONFIG_SYS_FSL_DDR2=y
-# CONFIG_MMC is not set
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_USB=y
-CONFIG_USB_EHCI_PCI=y
-CONFIG_USB_STORAGE=y
-CONFIG_VIDEO=y
-CONFIG_OF_LIBFDT=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xfff00000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_MPC86xx=y
-CONFIG_HIGH_BATS=y
-CONFIG_TARGET_MPC8610HPCD=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-# CONFIG_CONSOLE_MUX is not set
-CONFIG_MISC_INIT_R=y
-CONFIG_HUSH_PARSER=y
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_BMP=y
-CONFIG_CMD_EXT2=y
-CONFIG_DOS_PARTITION=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_ADDR=0xFFF80000
-CONFIG_SCSI_AHCI=y
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SCSI=y
-CONFIG_SYS_NS16550=y
-CONFIG_USB=y
-CONFIG_USB_KEYBOARD=y
-CONFIG_VIDEO=y
-CONFIG_OF_LIBFDT=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xeff00000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_MPC86xx=y
-CONFIG_HIGH_BATS=y
-CONFIG_TARGET_MPC8641HPCN=y
-CONFIG_PHYS_64BIT=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-# CONFIG_CONSOLE_MUX is not set
-CONFIG_HUSH_PARSER=y
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_DOS_PARTITION=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_ADDR=0xEFF80000
-CONFIG_SCSI_AHCI=y
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_USB=y
-CONFIG_USB_KEYBOARD=y
-CONFIG_VIDEO=y
-CONFIG_ADDR_MAP=y
-CONFIG_SYS_NUM_ADDR_MAP=8
-CONFIG_OF_LIBFDT=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xeff00000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_MPC86xx=y
-CONFIG_HIGH_BATS=y
-CONFIG_TARGET_MPC8641HPCN=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-# CONFIG_CONSOLE_MUX is not set
-CONFIG_HUSH_PARSER=y
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_DOS_PARTITION=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_ADDR=0xEFF80000
-CONFIG_SCSI_AHCI=y
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_USB=y
-CONFIG_USB_KEYBOARD=y
-CONFIG_VIDEO=y
-CONFIG_ADDR_MAP=y
-CONFIG_SYS_NUM_ADDR_MAP=8
-CONFIG_OF_LIBFDT=y
+++ /dev/null
-CONFIG_SH=y
-CONFIG_SYS_TEXT_BASE=0x8FFC0000
-CONFIG_ENV_SIZE=0x20000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_TARGET_MIGOR=y
-CONFIG_BOOTDELAY=3
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttySC0,115200 root=1f01"
-# CONFIG_CMDLINE_EDITING is not set
-# CONFIG_AUTO_COMPLETE is not set
-# CONFIG_CMD_BDI is not set
-# CONFIG_CMD_CONSOLE is not set
-# CONFIG_CMD_BOOTD is not set
-# CONFIG_CMD_RUN is not set
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_XIMG is not set
-# CONFIG_CMD_EDITENV is not set
-# CONFIG_CMD_ENV_EXISTS is not set
-CONFIG_CMD_SDRAM=y
-# CONFIG_CMD_ECHO is not set
-# CONFIG_CMD_ITEST is not set
-# CONFIG_CMD_SOURCE is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_PING=y
-# CONFIG_CMD_SLEEP is not set
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xA0020000
-CONFIG_VERSION_VARIABLE=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SCIF_CONSOLE=y
-CONFIG_USE_PRIVATE_LIBGCC=y
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_ARCH_MX28=y
-CONFIG_SYS_TEXT_BASE=0x40002000
-CONFIG_SPL_GPIO_SUPPORT=y
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_ENV_SIZE=0x20000
-CONFIG_ENV_OFFSET=0x120000
-CONFIG_SPL_TEXT_BASE=0x00001000
-CONFIG_TARGET_APX4DEVKIT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_ENV_OFFSET_REDUND=0x180000
-CONFIG_BOOTDELAY=1
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_ARCH_MISC_INIT=y
-CONFIG_BOARD_EARLY_INIT_F=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_HUSH_PARSER=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=gpmi-nand:128k(bootstrap),1024k(boot),768k(env),-(root)"
-CONFIG_CMD_UBI=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_NAND=y
-CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_VERSION_VARIABLE=y
-CONFIG_MXS_GPIO=y
-CONFIG_MMC_MXS=y
-CONFIG_MTD=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_NAND_MXS=y
-CONFIG_MII=y
-CONFIG_CONS_INDEX=0
-CONFIG_USB=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_SYS_DCACHE_OFF=y
-CONFIG_ARCH_CPU_INIT=y
-CONFIG_SYS_THUMB_BUILD=y
-CONFIG_ARCH_KIRKWOOD=y
-CONFIG_SYS_TEXT_BASE=0x600000
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_TARGET_DB_88F6281_BP=y
-CONFIG_ENV_SIZE=0x1000
-CONFIG_ENV_OFFSET=0xC0000
-CONFIG_ENV_SECT_SIZE=0x40000
-CONFIG_IDENT_STRING="\nMarvell DB-88F6281-BP"
-CONFIG_DEFAULT_DEVICE_TREE="kirkwood-db-88f6281"
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_BOOTDELAY=3
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
-CONFIG_CMD_DM=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_IDE=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_JFFS2=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nand0=orion_nand"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:512K(uboot),512K(env),4M(kernel),-(rootfs)"
-CONFIG_ISO_PARTITION=y
-CONFIG_OF_CONTROL=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_NETCONSOLE=y
-CONFIG_DM=y
-CONFIG_MVSATA_IDE=y
-CONFIG_MTD=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_DM_SPI_FLASH=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_PHY_MARVELL=y
-CONFIG_DM_ETH=y
-CONFIG_MVGBE=y
-CONFIG_MII=y
-CONFIG_DM_RTC=y
-CONFIG_RTC_MV=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_KIRKWOOD_SPI=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_STORAGE=y
-CONFIG_LZMA=y
-CONFIG_LZO=y
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_SYS_DCACHE_OFF=y
-CONFIG_ARCH_CPU_INIT=y
-CONFIG_SYS_THUMB_BUILD=y
-CONFIG_ARCH_KIRKWOOD=y
-CONFIG_SYS_TEXT_BASE=0x600000
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_TARGET_DB_88F6281_BP=y
-CONFIG_ENV_SIZE=0x1000
-CONFIG_ENV_OFFSET=0xC0000
-CONFIG_ENV_SECT_SIZE=0x40000
-CONFIG_IDENT_STRING="\nMarvell DB-88F6281-BP"
-CONFIG_DEFAULT_DEVICE_TREE="kirkwood-db-88f6281-spi"
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_FIT=y
-CONFIG_BOOTDELAY=3
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
-CONFIG_CMD_DM=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_IDE=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_JFFS2=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nand0=orion_nand"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:512K(uboot),512K(env),4M(kernel),-(rootfs)"
-CONFIG_ISO_PARTITION=y
-CONFIG_OF_CONTROL=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_NETCONSOLE=y
-CONFIG_DM=y
-CONFIG_MVSATA_IDE=y
-CONFIG_MTD=y
-CONFIG_DM_SPI_FLASH=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_PHY_MARVELL=y
-CONFIG_DM_ETH=y
-CONFIG_MVGBE=y
-CONFIG_MII=y
-CONFIG_DM_RTC=y
-CONFIG_RTC_MV=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_KIRKWOOD_SPI=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_STORAGE=y
-CONFIG_LZMA=y
-CONFIG_LZO=y
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_TARGET_LS2080A_EMU=y
-CONFIG_SYS_TEXT_BASE=0x30100000
-CONFIG_NR_DRAM_BANKS=3
-CONFIG_ENV_SIZE=0x1000
-CONFIG_IDENT_STRING=" LS2080A-EMU"
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="EMU"
-CONFIG_BOOTDELAY=10
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
-# CONFIG_USE_BOOTCOMMAND is not set
-# CONFIG_DISPLAY_BOARDINFO is not set
-# CONFIG_CMD_CONSOLE is not set
-# CONFIG_CMD_XIMG is not set
-# CONFIG_CMD_EDITENV is not set
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-# CONFIG_CMD_LOADS is not set
-# CONFIG_CMD_ITEST is not set
-# CONFIG_CMD_SETEXPR is not set
-# CONFIG_CMD_NFS is not set
-CONFIG_CMD_CACHE=y
-# CONFIG_CMD_SLEEP is not set
-CONFIG_MP=y
-# CONFIG_DOS_PARTITION is not set
-# CONFIG_ISO_PARTITION is not set
-# CONFIG_EFI_PARTITION is not set
-CONFIG_ENV_OVERWRITE=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_FSL_CAAM=y
-# CONFIG_MMC is not set
-CONFIG_SYS_NS16550=y
-CONFIG_OF_LIBFDT=y
-CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_TARGET_LS2080A_SIMU=y
-CONFIG_SYS_TEXT_BASE=0x30100000
-CONFIG_NR_DRAM_BANKS=3
-CONFIG_ENV_SIZE=0x1000
-CONFIG_IDENT_STRING=" LS2080A-SIMU"
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SIMU"
-CONFIG_BOOTDELAY=10
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
-# CONFIG_USE_BOOTCOMMAND is not set
-# CONFIG_DISPLAY_BOARDINFO is not set
-# CONFIG_CMD_CONSOLE is not set
-# CONFIG_CMD_XIMG is not set
-# CONFIG_CMD_EDITENV is not set
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-# CONFIG_CMD_LOADS is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND=y
-# CONFIG_CMD_ITEST is not set
-# CONFIG_CMD_SETEXPR is not set
-# CONFIG_CMD_NFS is not set
-CONFIG_CMD_CACHE=y
-# CONFIG_CMD_SLEEP is not set
-CONFIG_MP=y
-# CONFIG_ISO_PARTITION is not set
-# CONFIG_EFI_PARTITION is not set
-CONFIG_ENV_OVERWRITE=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_FSL_CAAM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_SYS_NS16550=y
-CONFIG_OF_LIBFDT=y
-CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_TARGET_MX35PDK=y
-CONFIG_SYS_TEXT_BASE=0xA0000000
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_ENV_SIZE=0x20000
-CONFIG_ENV_SECT_SIZE=0x20000
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_DATE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nand0=mxc_nand,nor0=physmap-flash.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=mxc_nand:1m(boot),5m(linux),96m(root),8m(cfg),1938m(user);physmap-flash.0:512k(b),4m(k),30m(u),28m(r)"
-CONFIG_EFI_PARTITION=y
-# CONFIG_PARTITION_UUIDS is not set
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
-CONFIG_ENV_ADDR=0xA0080000
-CONFIG_ENV_ADDR_REDUND=0xA00A0000
-CONFIG_MXC_GPIO=y
-CONFIG_FSL_ESDHC_IMX=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_PROTECTION=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_NAND_MXC=y
-CONFIG_MII=y
-CONFIG_SMC911X=y
-CONFIG_SMC911X_BASE=0xB6000000
-CONFIG_MXC_UART=y
-CONFIG_SPI=y
-CONFIG_MXC_SPI=y
-CONFIG_USB=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
+++ /dev/null
-CONFIG_SH=y
-CONFIG_SYS_TEXT_BASE=0x0FFC0000
-CONFIG_ENV_SIZE=0x40000
-CONFIG_ENV_SECT_SIZE=0x40000
-CONFIG_TARGET_R7780MP=y
-CONFIG_BOOTDELAY=3
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttySC0,115200"
-# CONFIG_CMDLINE_EDITING is not set
-# CONFIG_AUTO_COMPLETE is not set
-# CONFIG_CMD_BDI is not set
-# CONFIG_CMD_CONSOLE is not set
-# CONFIG_CMD_BOOTD is not set
-# CONFIG_CMD_RUN is not set
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_XIMG is not set
-# CONFIG_CMD_EDITENV is not set
-# CONFIG_CMD_ENV_EXISTS is not set
-CONFIG_CMD_IDE=y
-# CONFIG_CMD_LOADB is not set
-# CONFIG_CMD_LOADS is not set
-CONFIG_CMD_PCI=y
-CONFIG_CMD_SDRAM=y
-# CONFIG_CMD_ECHO is not set
-# CONFIG_CMD_ITEST is not set
-# CONFIG_CMD_SOURCE is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_PING=y
-# CONFIG_CMD_SLEEP is not set
-CONFIG_CMD_EXT2=y
-CONFIG_DOS_PARTITION=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xA0040000
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_PCI=y
-CONFIG_SCIF_CONSOLE=y
-CONFIG_USE_PRIVATE_LIBGCC=y
+++ /dev/null
-CONFIG_SH=y
-CONFIG_SYS_TEXT_BASE=0x5ff80000
-CONFIG_ENV_SIZE=0x10000
-CONFIG_SH_32BIT=y
-CONFIG_TARGET_SH7752EVB=y
-CONFIG_BOOTDELAY=3
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttySC2,115200 root=/dev/nfs ip=dhcp"
-# CONFIG_CMD_BDI is not set
-# CONFIG_CMD_CONSOLE is not set
-# CONFIG_CMD_BOOTD is not set
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_XIMG is not set
-# CONFIG_CMD_EDITENV is not set
-# CONFIG_CMD_ENV_EXISTS is not set
-CONFIG_CMD_MD5SUM=y
-# CONFIG_CMD_LOADB is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SDRAM=y
-# CONFIG_CMD_ECHO is not set
-# CONFIG_CMD_ITEST is not set
-# CONFIG_CMD_SOURCE is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-# CONFIG_CMD_SLEEP is not set
-CONFIG_CMD_EXT2=y
-CONFIG_MAC_PARTITION=y
-CONFIG_DOS_PARTITION=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_VERSION_VARIABLE=y
-CONFIG_MMC=y
-CONFIG_SH_MMCIF=y
-CONFIG_BITBANGMII=y
-CONFIG_PHY_VITESSE=y
-CONFIG_SH_ETHER=y
-CONFIG_SCIF_CONSOLE=y
-CONFIG_SPI=y
-CONFIG_USE_PRIVATE_LIBGCC=y
+++ /dev/null
-CONFIG_SH=y
-CONFIG_SYS_TEXT_BASE=0x5ff80000
-CONFIG_ENV_SIZE=0x10000
-CONFIG_TARGET_SH7753EVB=y
-CONFIG_BOOTDELAY=3
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttySC2,115200 root=/dev/nfs ip=dhcp"
-# CONFIG_CMD_BDI is not set
-# CONFIG_CMD_CONSOLE is not set
-# CONFIG_CMD_BOOTD is not set
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_XIMG is not set
-# CONFIG_CMD_EDITENV is not set
-# CONFIG_CMD_ENV_EXISTS is not set
-CONFIG_CMD_MD5SUM=y
-# CONFIG_CMD_LOADB is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SDRAM=y
-# CONFIG_CMD_ECHO is not set
-# CONFIG_CMD_ITEST is not set
-# CONFIG_CMD_SOURCE is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-# CONFIG_CMD_SLEEP is not set
-CONFIG_CMD_EXT2=y
-CONFIG_MAC_PARTITION=y
-CONFIG_DOS_PARTITION=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_VERSION_VARIABLE=y
-CONFIG_MMC=y
-CONFIG_SH_MMCIF=y
-CONFIG_BITBANGMII=y
-CONFIG_PHY_VITESSE=y
-CONFIG_SH_ETHER=y
-CONFIG_SCIF_CONSOLE=y
-CONFIG_SPI=y
-CONFIG_USE_PRIVATE_LIBGCC=y
+++ /dev/null
-CONFIG_SH=y
-CONFIG_SYS_TEXT_BASE=0x8ef80000
-CONFIG_ENV_SIZE=0x10000
-CONFIG_SH_32BIT=y
-CONFIG_TARGET_SH7757LCR=y
-CONFIG_BOOTDELAY=3
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttySC2,115200 root=/dev/nfs ip=dhcp"
-# CONFIG_CMDLINE_EDITING is not set
-# CONFIG_AUTO_COMPLETE is not set
-# CONFIG_CMD_BDI is not set
-# CONFIG_CMD_CONSOLE is not set
-# CONFIG_CMD_BOOTD is not set
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_XIMG is not set
-# CONFIG_CMD_EDITENV is not set
-# CONFIG_CMD_ENV_EXISTS is not set
-CONFIG_CMD_MD5SUM=y
-# CONFIG_CMD_LOADB is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SDRAM=y
-# CONFIG_CMD_ECHO is not set
-# CONFIG_CMD_ITEST is not set
-# CONFIG_CMD_SOURCE is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-# CONFIG_CMD_SLEEP is not set
-CONFIG_CMD_EXT2=y
-CONFIG_MAC_PARTITION=y
-CONFIG_DOS_PARTITION=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_VERSION_VARIABLE=y
-CONFIG_MMC=y
-CONFIG_SH_MMCIF=y
-CONFIG_BITBANGMII=y
-CONFIG_SH_ETHER=y
-CONFIG_SCIF_CONSOLE=y
-CONFIG_SPI=y
-CONFIG_USE_PRIVATE_LIBGCC=y
+++ /dev/null
-CONFIG_SH=y
-CONFIG_SYS_TEXT_BASE=0x8FFC0000
-CONFIG_ENV_SIZE=0x20000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_TARGET_SH7763RDP=y
-CONFIG_BOOTDELAY=-1
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttySC2,115200 root=1f01"
-# CONFIG_CMDLINE_EDITING is not set
-# CONFIG_AUTO_COMPLETE is not set
-# CONFIG_CMD_BDI is not set
-# CONFIG_CMD_CONSOLE is not set
-# CONFIG_CMD_BOOTD is not set
-# CONFIG_CMD_RUN is not set
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_XIMG is not set
-# CONFIG_CMD_EDITENV is not set
-# CONFIG_CMD_ENV_EXISTS is not set
-# CONFIG_CMD_LOADB is not set
-# CONFIG_CMD_LOADS is not set
-CONFIG_CMD_SDRAM=y
-# CONFIG_CMD_ECHO is not set
-# CONFIG_CMD_ITEST is not set
-# CONFIG_CMD_SOURCE is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-# CONFIG_CMD_SLEEP is not set
-CONFIG_CMD_JFFS2=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
-CONFIG_ENV_ADDR=0xA0020000
-CONFIG_ENV_ADDR_REDUND=0xA0040000
-CONFIG_VERSION_VARIABLE=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_BITBANGMII=y
-CONFIG_SH_ETHER=y
-CONFIG_SCIF_CONSOLE=y
-CONFIG_USE_PRIVATE_LIBGCC=y
^^^^^^^^^^^^^^
This CPU has the SH4AL-DSP core.
-Renesas SH7780
-^^^^^^^^^^^^^^
-This CPU has the SH4A core.
-
Supported Boards
----------------
- NOR Flash
- Marubun PCMCIA
-Renesas R7780MP
-^^^^^^^^^^^^^^^
-Board specific code is in board/r7780mp
-To use this board, type "make r7780mp_config".
-Support devices are:
-
- - SCIF
- - DDR-SDRAM
- - NOR Flash
- - Compact Flash
- - ASIX ethernet
- - SH7780 PCI bridge
- - RTL8110 ethernet
-
In SuperH, S-record and binary of made u-boot work on the memory.
When u-boot is written in the flash, it is necessary to change the
address by using 'objcopy'::
intel/index
kontron/index
microchip/index
- renesas/index
rockchip/index
sifive/index
sipeed/index
+++ /dev/null
-.. SPDX-License-Identifier: GPL-2.0+
-
-Renesas
-=======
-
-.. toctree::
- :maxdepth: 2
-
- sh7752evb
- sh7753evb
+++ /dev/null
-.. SPDX-License-Identifier: GPL-2.0+
-
-R0P7752C00000RZ board
-=====================
-
-This board specification
-------------------------
-
-The R0P7752C00000RZ(board config name:sh7752evb) has the following device:
-
- - SH7752 (SH-4A)
- - DDR3-SDRAM 512MB
- - SPI ROM 8MB
- - Gigabit Ethernet controllers
- - eMMC 4GB
-
-
-Configuration for This board
-----------------------------
-
-You can select the configuration as follows:
-
- - make sh7752evb_config
-
-
-This board specific command
----------------------------
-
-This board has the following its specific command:
-
-write_mac:
- You can write MAC address to SPI ROM.
-
-Usage 1: Write MAC address
-
-.. code-block:: none
-
- write_mac [GETHERC ch0] [GETHERC ch1]
-
- For example:
- => write_mac 74:90:50:00:33:9e 74:90:50:00:33:9f
-
-* We have to input the command as a single line (without carriage return)
-* We have to reset after input the command.
-
-Usage 2: Show current data
-
-.. code-block:: none
-
- write_mac
-
- For example:
- => write_mac
- GETHERC ch0 = 74:90:50:00:33:9e
- GETHERC ch1 = 74:90:50:00:33:9f
-
-
-Update SPI ROM
---------------
-
-1. Copy u-boot image to RAM area.
-2. Probe SPI device.
-
-.. code-block:: none
-
- => sf probe 0
- SF: Detected MX25L6405D with page size 64KiB, total 8 MiB
-
-3. Erase SPI ROM.
-
-.. code-block:: none
-
- => sf erase 0 80000
-
-4. Write u-boot image to SPI ROM.
-
-.. code-block:: none
-
- => sf write 0x48000000 0 80000
+++ /dev/null
-.. SPDX-License-Identifier: GPL-2.0+
-
-SH7753 EVB board
-================
-
-This board specification
-------------------------
-
-The SH7753 EVB (board config name:sh7753evb) has the following device:
-
- - SH7753 (SH-4A)
- - DDR3-SDRAM 512MB
- - SPI ROM 8MB
- - Gigabit Ethernet controllers
- - eMMC 4GB
-
-
-Configuration for This board
-----------------------------
-
-You can select the configuration as follows:
-
- - make sh7753evb_config
-
-
-This board specific command
----------------------------
-
-This board has the following its specific command:
-
-write_mac:
- You can write MAC address to SPI ROM.
-
-Usage 1: Write MAC address
-
-.. code-block:: none
-
- write_mac [GETHERC ch0] [GETHERC ch1]
-
- For example:
- => write_mac 74:90:50:00:33:9e 74:90:50:00:33:9f
-
-* We have to input the command as a single line (without carriage return)
-* We have to reset after input the command.
-
-Usage 2: Show current data
-
-.. code-block:: none
-
- write_mac
-
- For example:
- => write_mac
- GETHERC ch0 = 74:90:50:00:33:9e
- GETHERC ch1 = 74:90:50:00:33:9f
-
-
-Update SPI ROM
---------------
-
-1. Copy u-boot image to RAM area.
-2. Probe SPI device.
-
-.. code-block:: none
-
- => sf probe 0
- SF: Detected MX25L6405D with page size 64KiB, total 8 MiB
-
-3. Erase SPI ROM.
-
-.. code-block:: none
-
- => sf erase 0 80000
-
-4. Write u-boot image to SPI ROM.
-
-.. code-block:: none
-
- => sf write 0x48000000 0 80000
if SYS_I2C_MXC_I2C1
config SYS_MXC_I2C1_SPEED
int "I2C Channel 1 speed"
- default 40000000 if TARGET_LS2080A_SIMU || TARGET_LS2080A_EMU
+ default 40000000 if TARGET_LS2080A_EMU
default 100000
help
MXC I2C Channel 1 speed
if SYS_I2C_MXC_I2C2
config SYS_MXC_I2C2_SPEED
int "I2C Channel 2 speed"
- default 40000000 if TARGET_LS2080A_SIMU || TARGET_LS2080A_EMU
+ default 40000000 if TARGET_LS2080A_EMU
default 100000
help
MXC I2C Channel 2 speed
obj-$(CONFIG_MVPP2) += mvpp2.o
obj-$(CONFIG_NATSEMI) += natsemi.o
obj-$(CONFIG_DRIVER_NE2000) += ne2000.o ne2000_base.o
-obj-$(CONFIG_DRIVER_AX88796L) += ax88796.o ne2000_base.o
obj-$(CONFIG_NETCONSOLE) += netconsole.o
obj-$(CONFIG_NS8382X) += ns8382x.o
obj-$(CONFIG_PCH_GBE) += pch_gbe.o
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (c) 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
- */
-#include <common.h>
-#include <linux/delay.h>
-#include "ax88796.h"
-
-/*
- * Set 1 bit data
- */
-static void ax88796_bitset(u32 bit)
-{
- /* DATA1 */
- if( bit )
- EEDI_HIGH;
- else
- EEDI_LOW;
-
- EECLK_LOW;
- udelay(1000);
- EECLK_HIGH;
- udelay(1000);
- EEDI_LOW;
-}
-
-/*
- * Get 1 bit data
- */
-static u8 ax88796_bitget(void)
-{
- u8 bit;
-
- EECLK_LOW;
- udelay(1000);
- /* DATA */
- bit = EEDO;
- EECLK_HIGH;
- udelay(1000);
-
- return bit;
-}
-
-/*
- * Send COMMAND to EEPROM
- */
-static void ax88796_eep_cmd(u8 cmd)
-{
- ax88796_bitset(BIT_DUMMY);
- switch(cmd){
- case MAC_EEP_READ:
- ax88796_bitset(1);
- ax88796_bitset(1);
- ax88796_bitset(0);
- break;
-
- case MAC_EEP_WRITE:
- ax88796_bitset(1);
- ax88796_bitset(0);
- ax88796_bitset(1);
- break;
-
- case MAC_EEP_ERACE:
- ax88796_bitset(1);
- ax88796_bitset(1);
- ax88796_bitset(1);
- break;
-
- case MAC_EEP_EWEN:
- ax88796_bitset(1);
- ax88796_bitset(0);
- ax88796_bitset(0);
- break;
-
- case MAC_EEP_EWDS:
- ax88796_bitset(1);
- ax88796_bitset(0);
- ax88796_bitset(0);
- break;
- default:
- break;
- }
-}
-
-static void ax88796_eep_setaddr(u16 addr)
-{
- int i ;
-
- for( i = 7 ; i >= 0 ; i-- )
- ax88796_bitset(addr & (1 << i));
-}
-
-/*
- * Get data from EEPROM
- */
-static u16 ax88796_eep_getdata(void)
-{
- ushort data = 0;
- int i;
-
- ax88796_bitget(); /* DUMMY */
- for( i = 0 ; i < 16 ; i++ ){
- data <<= 1;
- data |= ax88796_bitget();
- }
- return data;
-}
-
-static void ax88796_mac_read(u8 *buff)
-{
- int i ;
- u16 data;
- u16 addr = 0;
-
- for( i = 0 ; i < 3; i++ )
- {
- EECS_HIGH;
- EEDI_LOW;
- udelay(1000);
- /* READ COMMAND */
- ax88796_eep_cmd(MAC_EEP_READ);
- /* ADDRESS */
- ax88796_eep_setaddr(addr++);
- /* GET DATA */
- data = ax88796_eep_getdata();
- *buff++ = (uchar)(data & 0xff);
- *buff++ = (uchar)((data >> 8) & 0xff);
- EECLK_LOW;
- EEDI_LOW;
- EECS_LOW;
- }
-}
-
-int get_prom(u8* mac_addr, u8* base_addr)
-{
- u8 prom[32];
- int i;
-
- ax88796_mac_read(prom);
- for (i = 0; i < 6; i++){
- mac_addr[i] = prom[i];
- }
- return 1;
-}
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * AX88796L(NE2000) support
- *
- * (c) 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
- */
-
-#ifndef __DRIVERS_AX88796L_H__
-#define __DRIVERS_AX88796L_H__
-
-#define DP_DATA (0x10 << 1)
-#define START_PG 0x40 /* First page of TX buffer */
-#define START_PG2 0x48
-#define STOP_PG 0x80 /* Last page +1 of RX ring */
-#define TX_PAGES 12
-#define RX_START (START_PG+TX_PAGES)
-#define RX_END STOP_PG
-
-#define AX88796L_BASE_ADDRESS CONFIG_DRIVER_NE2000_BASE
-#define AX88796L_BYTE_ACCESS 0x00001000
-#define AX88796L_OFFSET 0x00000400
-#define AX88796L_ADDRESS_BYTE AX88796L_BASE_ADDRESS + \
- AX88796L_BYTE_ACCESS + AX88796L_OFFSET
-#define AX88796L_REG_MEMR AX88796L_ADDRESS_BYTE + (0x14<<1)
-#define AX88796L_REG_CR AX88796L_ADDRESS_BYTE + (0x00<<1)
-
-#define AX88796L_CR (*(vu_short *)(AX88796L_REG_CR))
-#define AX88796L_MEMR (*(vu_short *)(AX88796L_REG_MEMR))
-
-#define EECS_HIGH (AX88796L_MEMR |= 0x10)
-#define EECS_LOW (AX88796L_MEMR &= 0xef)
-#define EECLK_HIGH (AX88796L_MEMR |= 0x80)
-#define EECLK_LOW (AX88796L_MEMR &= 0x7f)
-#define EEDI_HIGH (AX88796L_MEMR |= 0x20)
-#define EEDI_LOW (AX88796L_MEMR &= 0xdf)
-#define EEDO ((AX88796L_MEMR & 0x40)>>6)
-
-#define PAGE0_SET (AX88796L_CR &= 0x3f)
-#define PAGE1_SET (AX88796L_CR = (AX88796L_CR & 0x3f) | 0x40)
-
-#define BIT_DUMMY 0
-#define MAC_EEP_READ 1
-#define MAC_EEP_WRITE 2
-#define MAC_EEP_ERACE 3
-#define MAC_EEP_EWEN 4
-#define MAC_EEP_EWDS 5
-
-/* R7780MP Specific code */
-#if defined(CONFIG_R7780MP)
-#define ISA_OFFSET 0x1400
-#define DP_IN(_b_, _o_, _d_) (_d_) = \
- *( (vu_short *) ((_b_) + ((_o_) * 2) + ISA_OFFSET))
-#define DP_OUT(_b_, _o_, _d_) \
- *((vu_short *)((_b_) + ((_o_) * 2) + ISA_OFFSET)) = (_d_)
-#define DP_IN_DATA(_b_, _d_) (_d_) = *( (vu_short *) ((_b_) + ISA_OFFSET))
-#define DP_OUT_DATA(_b_, _d_) *( (vu_short *) ((_b_)+ISA_OFFSET)) = (_d_)
-#else
-/* Please change for your target boards */
-#define ISA_OFFSET 0x0000
-#define DP_IN(_b_, _o_, _d_) (_d_) = *( (vu_short *)((_b_)+(_o_ )+ISA_OFFSET))
-#define DP_OUT(_b_, _o_, _d_) *((vu_short *)((_b_)+(_o_)+ISA_OFFSET)) = (_d_)
-#define DP_IN_DATA(_b_, _d_) (_d_) = *( (vu_short *) ((_b_)+ISA_OFFSET))
-#define DP_OUT_DATA(_b_, _d_) *( (vu_short *) ((_b_)+ISA_OFFSET)) = (_d_)
-#endif
-
-#endif /* __DRIVERS_AX88796L_H__ */
#define ADDR_TO_P2(addr) ((((uintptr_t)(addr) & ~0xe0000000) | 0xa0000000))
/* The ethernet controller needs to use physical addresses */
-#if defined(CONFIG_SH_32BIT)
-#define ADDR_TO_PHY(addr) ((((uintptr_t)(addr) & ~0xe0000000) | 0x40000000))
-#else
#define ADDR_TO_PHY(addr) ((uintptr_t)(addr) & ~0xe0000000)
-#endif
#elif defined(CONFIG_ARM)
#ifndef inl
#define inl readl
config MXC_UART
bool "IMX serial port support"
- depends on ARCH_MX25 || ARCH_MX31 || TARGET_APF27 || TARGET_FLEA3 || TARGET_MX35PDK \
+ depends on ARCH_MX25 || ARCH_MX31 || TARGET_APF27 || TARGET_FLEA3 \
|| MX5 || MX6 || MX7 || IMX8M
help
If you have a machine based on a Motorola IMX CPU you
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc.
- */
-
-/*
- * mpc8544ds board configuration file
- *
- */
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_PCI1 1 /* PCI controller 1 */
-#define CONFIG_PCIE1 1 /* PCIE controller 1 (slot 1) */
-#define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */
-#define CONFIG_PCIE3 1 /* PCIE controller 3 (ULI bridge) */
-#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
-#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
-#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
-
-#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
-
-#ifndef __ASSEMBLY__
-#include <linux/stringify.h>
-extern unsigned long get_board_sys_clk(unsigned long dummy);
-#endif
-#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */
-
-/*
- * These can be toggled for performance analysis, otherwise use default.
- */
-#define CONFIG_L2_CACHE /* toggle L2 cache */
-#define CONFIG_BTB /* toggle branch predition */
-
-/*
- * Only possible on E500 Version 2 or newer cores.
- */
-#define CONFIG_ENABLE_36BIT_PHYS 1
-
-#define CONFIG_SYS_CCSRBAR 0xe0000000
-#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
-
-/* DDR Setup */
-#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
-#define CONFIG_DDR_SPD
-
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
-#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
-
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_VERY_BIG_RAM
-
-#define CONFIG_DIMM_SLOTS_PER_CTLR 1
-#define CONFIG_CHIP_SELECTS_PER_CTRL 2
-
-/* I2C addresses of SPD EEPROMs */
-#define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
-
-/* Make sure required options are set */
-#ifndef CONFIG_SPD_EEPROM
-#error ("CONFIG_SPD_EEPROM is required")
-#endif
-
-/*
- * Memory map
- *
- * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
- *
- * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
- *
- * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable
- *
- * 0xe000_0000 0xe00f_ffff CCSR 1M non-cacheable
- * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable
- *
- * Localbus cacheable
- *
- * 0xf000_0000 0xf3ff_ffff SDRAM 64M Cacheable
- * 0xf401_0000 0xf401_3fff L1 for stack 4K Cacheable TLB0
- *
- * Localbus non-cacheable
- *
- * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M non-cacheable
- * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M non-cacheable
- * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M non-cacheable
- *
- */
-
-/*
- * Local Bus Definitions
- */
-#define CONFIG_SYS_BOOT_BLOCK 0xfc000000 /* boot TLB */
-
-#define CONFIG_SYS_FLASH_BASE 0xff800000 /* start of FLASH 8M */
-
-#define CONFIG_SYS_BR0_PRELIM 0xff801001
-#define CONFIG_SYS_BR1_PRELIM 0xfe801001
-
-#define CONFIG_SYS_OR0_PRELIM 0xff806e65
-#define CONFIG_SYS_OR1_PRELIM 0xff806e65
-
-#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
-
-#define CONFIG_SYS_FLASH_QUIET_TEST
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
-#undef CONFIG_SYS_FLASH_CHECKSUM
-#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
-
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-
-#define CONFIG_SYS_LBC_NONCACHE_BASE 0xf8000000
-
-#define CONFIG_SYS_BR2_PRELIM 0xf8201001 /* port size 16bit */
-#define CONFIG_SYS_OR2_PRELIM 0xfff06ff7 /* 1MB Compact Flash area*/
-
-#define CONFIG_SYS_BR3_PRELIM 0xf8100801 /* port size 8bit */
-#define CONFIG_SYS_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/
-
-#define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
-#define PIXIS_BASE 0xf8100000 /* PIXIS registers */
-#define PIXIS_ID 0x0 /* Board ID at offset 0 */
-#define PIXIS_VER 0x1 /* Board version at offset 1 */
-#define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */
-#define PIXIS_RST 0x4 /* PIXIS Reset Control register */
-#define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch
- * register */
-#define PIXIS_SPD 0x7 /* Register for SYSCLK speed */
-#define PIXIS_VCTL 0x10 /* VELA Control Register */
-#define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */
-#define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
-#define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */
-#define PIXIS_VBOOT_FMAP 0x80 /* VBOOT - CFG_FLASHMAP */
-#define PIXIS_VBOOT_FBANK 0x40 /* VBOOT - CFG_FLASHBANK */
-#define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */
-#define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
-#define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
-#define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
-#define PIXIS_VSPEED2 0x1d /* VELA VSpeed 2 */
-#define CONFIG_SYS_PIXIS_VBOOT_MASK 0x40 /* Reset altbank mask*/
-#define PIXIS_VSPEED2_TSEC1SER 0x2
-#define PIXIS_VSPEED2_TSEC3SER 0x1
-#define PIXIS_VCFGEN1_TSEC1SER 0x20
-#define PIXIS_VCFGEN1_TSEC3SER 0x40
-#define PIXIS_VSPEED2_MASK (PIXIS_VSPEED2_TSEC1SER|PIXIS_VSPEED2_TSEC3SER)
-#define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER|PIXIS_VCFGEN1_TSEC3SER)
-
-#define CONFIG_SYS_INIT_RAM_LOCK 1
-#define CONFIG_SYS_INIT_RAM_ADDR 0xf4010000 /* Initial L1 address */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
-#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
-
-/* Serial Port - controlled on board with jumper J8
- * open - index 2
- * shorted - index 1
- */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
-
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
-
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
-
-/* I2C */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED 400000
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x3100
-#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
-
-/*
- * General PCI
- * Memory space is mapped 1-1, but I/O space must start from 0.
- */
-#define CONFIG_SYS_PCIE_VIRT 0x80000000 /* 1G PCIE TLB */
-#define CONFIG_SYS_PCIE_PHYS 0x80000000 /* 1G PCIE TLB */
-#define CONFIG_SYS_PCI_VIRT 0xc0000000 /* 512M PCI TLB */
-#define CONFIG_SYS_PCI_PHYS 0xc0000000 /* 512M PCI TLB */
-
-#define CONFIG_SYS_PCI1_MEM_VIRT 0xc0000000
-#define CONFIG_SYS_PCI1_MEM_BUS 0xc0000000
-#define CONFIG_SYS_PCI1_MEM_PHYS 0xc0000000
-#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCI1_IO_VIRT 0xe1000000
-#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
-#define CONFIG_SYS_PCI1_IO_PHYS 0xe1000000
-#define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64k */
-
-/* controller 2, Slot 1, tgtid 1, Base address 9000 */
-#define CONFIG_SYS_PCIE2_NAME "Slot 1"
-#define CONFIG_SYS_PCIE2_MEM_VIRT 0x80000000
-#define CONFIG_SYS_PCIE2_MEM_BUS 0x80000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS 0x80000000
-#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE2_IO_VIRT 0xe1010000
-#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE2_IO_PHYS 0xe1010000
-#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
-
-/* controller 1, Slot 2,tgtid 2, Base address a000 */
-#define CONFIG_SYS_PCIE1_NAME "Slot 2"
-#define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000
-#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000
-#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCIE1_IO_VIRT 0xe1020000
-#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE1_IO_PHYS 0xe1020000
-#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
-
-/* controller 3, direct to uli, tgtid 3, Base address b000 */
-#define CONFIG_SYS_PCIE3_NAME "ULI"
-#define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000
-#define CONFIG_SYS_PCIE3_MEM_BUS 0xb0000000
-#define CONFIG_SYS_PCIE3_MEM_PHYS 0xb0000000
-#define CONFIG_SYS_PCIE3_MEM_SIZE 0x00100000 /* 1M */
-#define CONFIG_SYS_PCIE3_IO_VIRT 0xb0100000 /* reuse mem LAW */
-#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE3_IO_PHYS 0xb0100000 /* reuse mem LAW */
-#define CONFIG_SYS_PCIE3_IO_SIZE 0x00100000 /* 1M */
-#define CONFIG_SYS_PCIE3_MEM_VIRT2 0xb0200000
-#define CONFIG_SYS_PCIE3_MEM_BUS2 0xb0200000
-#define CONFIG_SYS_PCIE3_MEM_PHYS2 0xb0200000
-#define CONFIG_SYS_PCIE3_MEM_SIZE2 0x00200000 /* 1M */
-
-#if defined(CONFIG_PCI)
-
-/*PCIE video card used*/
-#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE2_IO_VIRT
-
-/*PCI video card used*/
-/*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_VIRT*/
-
-/* video */
-
-#if defined(CONFIG_VIDEO)
-#define CONFIG_BIOSEMU
-#define CONFIG_ATI_RADEON_FB
-#define CONFIG_VIDEO_LOGO
-#define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
-#endif
-
-
-#ifndef CONFIG_PCI_PNP
- #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS
- #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BUS
- #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */
-#endif
-
-#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-
-#ifdef CONFIG_SCSI_AHCI
-#define CONFIG_SATA_ULI5288
-#define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
-#define CONFIG_SYS_SCSI_MAX_LUN 1
-#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
-#endif /* CONFIG_SCSI_AHCI */
-
-#endif /* CONFIG_PCI */
-
-#if defined(CONFIG_TSEC_ENET)
-
-#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
-#define CONFIG_TSEC1 1
-#define CONFIG_TSEC1_NAME "eTSEC1"
-#define CONFIG_TSEC3 1
-#define CONFIG_TSEC3_NAME "eTSEC3"
-
-#define CONFIG_PIXIS_SGMII_CMD
-#define CONFIG_FSL_SGMII_RISER 1
-#define SGMII_RISER_PHY_OFFSET 0x1c
-
-#define TSEC1_PHY_ADDR 0
-#define TSEC3_PHY_ADDR 1
-
-#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
-#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
-
-#define TSEC1_PHYIDX 0
-#define TSEC3_PHYIDX 0
-
-#define CONFIG_ETHPRIME "eTSEC1"
-#endif /* CONFIG_TSEC_ENET */
-
-/*
- * Environment
- */
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-/*
- * USB
- */
-
-#ifdef CONFIG_USB_EHCI_HCD
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#define CONFIG_PCI_EHCI_DEVICE 0
-#endif
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 64 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
-#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#endif
-
-/*
- * Environment Configuration
- */
-
-/* The mac addresses for all ethernet interface */
-#if defined(CONFIG_TSEC_ENET)
-#define CONFIG_HAS_ETH0
-#define CONFIG_HAS_ETH1
-#endif
-
-#define CONFIG_IPADDR 192.168.1.251
-
-#define CONFIG_HOSTNAME "8544ds_unknown"
-#define CONFIG_ROOTPATH "/nfs/mpc85xx"
-#define CONFIG_BOOTFILE "8544ds/uImage.uboot"
-#define CONFIG_UBOOTPATH 8544ds/u-boot.bin /* TFTP server */
-
-#define CONFIG_SERVERIP 192.168.1.1
-#define CONFIG_GATEWAYIP 192.168.1.1
-#define CONFIG_NETMASK 255.255.0.0
-
-#define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
-"netdev=eth0\0" \
-"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
-"tftpflash=tftpboot $loadaddr $uboot; " \
- "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
- " +$filesize; " \
- "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
- " +$filesize; " \
- "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
- " $filesize; " \
- "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
- " +$filesize; " \
- "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
- " $filesize\0" \
-"consoledev=ttyS0\0" \
-"ramdiskaddr=2000000\0" \
-"ramdiskfile=8544ds/ramdisk.uboot\0" \
-"fdtaddr=1e00000\0" \
-"fdtfile=8544ds/mpc8544ds.dtb\0" \
-"bdev=sda3\0"
-
-#define CONFIG_NFSBOOTCOMMAND \
- "setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$serverip:$rootpath " \
- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_RAMBOOTCOMMAND \
- "setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $ramdiskaddr $ramdiskfile;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#define CONFIG_BOOTCOMMAND \
- "setenv bootargs root=/dev/$bdev rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
-
-#endif /* __CONFIG_H */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2007-2008,2010-2011 Freescale Semiconductor, Inc.
- */
-
-/*
- * mpc8572ds board configuration file
- *
- */
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <linux/stringify.h>
-
-#include "../board/freescale/common/ics307_clk.h"
-
-#ifndef CONFIG_RESET_VECTOR_ADDRESS
-#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
-#endif
-
-#ifndef CONFIG_SYS_MONITOR_BASE
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
-#endif
-
-/* High Level Configuration Options */
-
-#define CONFIG_PCIE1 1 /* PCIE controller 1 (slot 1) */
-#define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */
-#define CONFIG_PCIE3 1 /* PCIE controller 3 (ULI bridge) */
-#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
-#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
-#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
-
-#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */
-#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() /* ddrclk for MPC85xx */
-#define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */
-
-/*
- * These can be toggled for performance analysis, otherwise use default.
- */
-#define CONFIG_L2_CACHE /* toggle L2 cache */
-#define CONFIG_BTB /* toggle branch predition */
-
-#define CONFIG_ENABLE_36BIT_PHYS 1
-
-/*
- * Config the L2 Cache as L2 SRAM
- */
-#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull
-#else
-#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
-#endif
-#define CONFIG_SYS_L2_SIZE (512 << 10)
-#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
-
-#define CONFIG_SYS_CCSRBAR 0xffe00000
-#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
-
-#if defined(CONFIG_NAND_SPL)
-#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
-#endif
-
-/* DDR Setup */
-#define CONFIG_VERY_BIG_RAM
-#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
-#define CONFIG_DDR_SPD
-
-#define CONFIG_DDR_ECC
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
-#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
-
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-
-#define CONFIG_DIMM_SLOTS_PER_CTLR 1
-#define CONFIG_CHIP_SELECTS_PER_CTRL 2
-
-/* I2C addresses of SPD EEPROMs */
-#define CONFIG_SYS_SPD_BUS_NUM 1 /* SPD EEPROMS locate on I2C bus 1 */
-#define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */
-#define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 1 DIMM 0 */
-
-/* These are used when DDR doesn't use SPD. */
-#define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */
-#define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F
-#define CONFIG_SYS_DDR_CS0_CONFIG 0x80010202 /* Enable, no interleaving */
-#define CONFIG_SYS_DDR_TIMING_3 0x00020000
-#define CONFIG_SYS_DDR_TIMING_0 0x00260802
-#define CONFIG_SYS_DDR_TIMING_1 0x626b2634
-#define CONFIG_SYS_DDR_TIMING_2 0x062874cf
-#define CONFIG_SYS_DDR_MODE_1 0x00440462
-#define CONFIG_SYS_DDR_MODE_2 0x00000000
-#define CONFIG_SYS_DDR_INTERVAL 0x0c300100
-#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
-#define CONFIG_SYS_DDR_CLK_CTRL 0x00800000
-#define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
-#define CONFIG_SYS_DDR_OCD_STATUS 0x00000000
-#define CONFIG_SYS_DDR_CONTROL 0xc3000008 /* Type = DDR2 */
-#define CONFIG_SYS_DDR_CONTROL2 0x24400000
-
-#define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d
-#define CONFIG_SYS_DDR_ERR_DIS 0x00000000
-#define CONFIG_SYS_DDR_SBE 0x00010000
-
-/*
- * Make sure required options are set
- */
-#ifndef CONFIG_SPD_EEPROM
-#error ("CONFIG_SPD_EEPROM is required")
-#endif
-
-/*
- * Memory map
- *
- * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
- * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
- * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable
- * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable
- *
- * Localbus cacheable (TBD)
- * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable
- *
- * Localbus non-cacheable
- * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable
- * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable
- * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable
- * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0
- * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
- * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
- */
-
-/*
- * Local Bus Definitions
- */
-#define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
-#else
-#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
-#endif
-
-#define CONFIG_FLASH_BR_PRELIM \
- (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V)
-#define CONFIG_FLASH_OR_PRELIM 0xf8000ff7
-
-#define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
-#define CONFIG_SYS_OR1_PRELIM 0xf8000ff7
-
-#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
-#define CONFIG_SYS_FLASH_QUIET_TEST
-#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
-#undef CONFIG_SYS_FLASH_CHECKSUM
-#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-
-#undef CONFIG_SYS_RAMBOOT
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
-
-#define CONFIG_HWCONFIG /* enable hwconfig */
-#define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
-#define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
-#ifdef CONFIG_PHYS_64BIT
-#define PIXIS_BASE_PHYS 0xfffdf0000ull
-#else
-#define PIXIS_BASE_PHYS PIXIS_BASE
-#endif
-
-#define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
-#define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */
-
-#define PIXIS_ID 0x0 /* Board ID at offset 0 */
-#define PIXIS_VER 0x1 /* Board version at offset 1 */
-#define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */
-#define PIXIS_CSR 0x3 /* PIXIS General control/status register */
-#define PIXIS_RST 0x4 /* PIXIS Reset Control register */
-#define PIXIS_PWR 0x5 /* PIXIS Power status register */
-#define PIXIS_AUX 0x6 /* Auxiliary 1 register */
-#define PIXIS_SPD 0x7 /* Register for SYSCLK speed */
-#define PIXIS_AUX2 0x8 /* Auxiliary 2 register */
-#define PIXIS_VCTL 0x10 /* VELA Control Register */
-#define PIXIS_VSTAT 0x11 /* VELA Status Register */
-#define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */
-#define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
-#define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */
-#define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */
-#define PIXIS_VBOOT_LBMAP 0xc0 /* VBOOT - CFG_LBMAP */
-#define PIXIS_VBOOT_LBMAP_NOR0 0x00 /* cfg_lbmap - boot from NOR 0 */
-#define PIXIS_VBOOT_LBMAP_PJET 0x01 /* cfg_lbmap - boot from projet */
-#define PIXIS_VBOOT_LBMAP_NAND 0x02 /* cfg_lbmap - boot from NAND */
-#define PIXIS_VBOOT_LBMAP_NOR1 0x03 /* cfg_lbmap - boot from NOR 1 */
-#define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */
-#define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
-#define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */
-#define PIXIS_VSYSCLK0 0x1C /* VELA SYSCLK0 Register */
-#define PIXIS_VSYSCLK1 0x1D /* VELA SYSCLK1 Register */
-#define PIXIS_VSYSCLK2 0x1E /* VELA SYSCLK2 Register */
-#define PIXIS_VDDRCLK0 0x1F /* VELA DDRCLK0 Register */
-#define PIXIS_VDDRCLK1 0x20 /* VELA DDRCLK1 Register */
-#define PIXIS_VDDRCLK2 0x21 /* VELA DDRCLK2 Register */
-#define PIXIS_VWATCH 0x24 /* Watchdog Register */
-#define PIXIS_LED 0x25 /* LED Register */
-
-#define PIXIS_SPD_SYSCLK_MASK 0x7 /* SYSCLK option */
-
-/* old pixis referenced names */
-#define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
-#define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
-#define CONFIG_SYS_PIXIS_VBOOT_MASK 0xc0
-#define PIXIS_VSPEED2_TSEC1SER 0x8
-#define PIXIS_VSPEED2_TSEC2SER 0x4
-#define PIXIS_VSPEED2_TSEC3SER 0x2
-#define PIXIS_VSPEED2_TSEC4SER 0x1
-#define PIXIS_VCFGEN1_TSEC1SER 0x20
-#define PIXIS_VCFGEN1_TSEC2SER 0x20
-#define PIXIS_VCFGEN1_TSEC3SER 0x20
-#define PIXIS_VCFGEN1_TSEC4SER 0x20
-#define PIXIS_VSPEED2_MASK (PIXIS_VSPEED2_TSEC1SER \
- | PIXIS_VSPEED2_TSEC2SER \
- | PIXIS_VSPEED2_TSEC3SER \
- | PIXIS_VSPEED2_TSEC4SER)
-#define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER \
- | PIXIS_VCFGEN1_TSEC2SER \
- | PIXIS_VCFGEN1_TSEC3SER \
- | PIXIS_VCFGEN1_TSEC4SER)
-
-#define CONFIG_SYS_INIT_RAM_LOCK 1
-#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
-#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
-
-#ifndef CONFIG_NAND_SPL
-#define CONFIG_SYS_NAND_BASE 0xffa00000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
-#else
-#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
-#endif
-#else
-#define CONFIG_SYS_NAND_BASE 0xfff00000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull
-#else
-#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
-#endif
-#endif
-
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\
- CONFIG_SYS_NAND_BASE + 0x40000, \
- CONFIG_SYS_NAND_BASE + 0x80000,\
- CONFIG_SYS_NAND_BASE + 0xC0000}
-#define CONFIG_SYS_MAX_NAND_DEVICE 4
-#define CONFIG_NAND_FSL_ELBC 1
-#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
-#define CONFIG_SYS_NAND_MAX_OOBFREE 5
-#define CONFIG_SYS_NAND_MAX_ECCPOS 56
-
-/* NAND boot: 4K NAND loader config */
-#define CONFIG_SYS_NAND_SPL_SIZE 0x1000
-#define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000)
-#define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR)
-#define CONFIG_SYS_NAND_U_BOOT_START \
- (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE)
-#define CONFIG_SYS_NAND_U_BOOT_OFFS (0)
-#define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000)
-#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
-
-/* NAND flash config */
-#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
- | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
- | BR_PS_8 /* Port Size = 8 bit */ \
- | BR_MS_FCM /* MSEL = FCM */ \
- | BR_V) /* valid */
-#define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
- | OR_FCM_PGS /* Large Page*/ \
- | OR_FCM_CSCT \
- | OR_FCM_CST \
- | OR_FCM_CHT \
- | OR_FCM_SCY_1 \
- | OR_FCM_TRLX \
- | OR_FCM_EHTR)
-
-#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
-#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
-#define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
-#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
-#define CONFIG_SYS_BR4_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x40000) \
- | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
- | BR_PS_8 /* Port Size = 8 bit */ \
- | BR_MS_FCM /* MSEL = FCM */ \
- | BR_V) /* valid */
-#define CONFIG_SYS_OR4_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
-#define CONFIG_SYS_BR5_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x80000)\
- | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
- | BR_PS_8 /* Port Size = 8 bit */ \
- | BR_MS_FCM /* MSEL = FCM */ \
- | BR_V) /* valid */
-#define CONFIG_SYS_OR5_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
-
-#define CONFIG_SYS_BR6_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0xc0000)\
- | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
- | BR_PS_8 /* Port Size = 8 bit */ \
- | BR_MS_FCM /* MSEL = FCM */ \
- | BR_V) /* valid */
-#define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
-
-/* Serial Port - controlled on board with jumper J8
- * open - index 2
- * shorted - index 1
- */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
-#ifdef CONFIG_NAND_SPL
-#define CONFIG_NS16550_MIN_FUNCTIONS
-#endif
-
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
-
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
-
-/* I2C */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED 400000
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
-#define CONFIG_SYS_FSL_I2C2_SPEED 400000
-#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
-#define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
-
-/*
- * I2C2 EEPROM
- */
-#define CONFIG_ID_EEPROM
-#ifdef CONFIG_ID_EEPROM
-#define CONFIG_SYS_I2C_EEPROM_NXID
-#endif
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_EEPROM_BUS_NUM 1
-
-/*
- * General PCI
- * Memory space is mapped 1-1, but I/O space must start from 0.
- */
-
-/* controller 3, direct to uli, tgtid 3, Base address 8000 */
-#define CONFIG_SYS_PCIE3_NAME "ULI"
-#define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
-#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull
-#else
-#define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000
-#define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000
-#endif
-#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000
-#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull
-#else
-#define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000
-#endif
-#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
-
-/* controller 2, Slot 2, tgtid 2, Base address 9000 */
-#define CONFIG_SYS_PCIE2_NAME "Slot 1"
-#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
-#else
-#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
-#endif
-#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
-#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
-#else
-#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
-#endif
-#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
-
-/* controller 1, Slot 1, tgtid 1, Base address a000 */
-#define CONFIG_SYS_PCIE1_NAME "Slot 2"
-#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull
-#else
-#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
-#endif
-#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000
-#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull
-#else
-#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000
-#endif
-#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
-
-#if defined(CONFIG_PCI)
-
-/*PCIE video card used*/
-#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT
-
-/* video */
-
-#if defined(CONFIG_VIDEO)
-#define CONFIG_BIOSEMU
-#define CONFIG_ATI_RADEON_FB
-#define CONFIG_VIDEO_LOGO
-#define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
-#endif
-
-
-#ifndef CONFIG_PCI_PNP
- #define PCI_ENET0_IOADDR CONFIG_SYS_PCIE3_IO_BUS
- #define PCI_ENET0_MEMADDR CONFIG_SYS_PCIE3_IO_BUS
- #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */
-#endif
-
-#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-
-#ifdef CONFIG_SCSI_AHCI
-#define CONFIG_SATA_ULI5288
-#define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
-#define CONFIG_SYS_SCSI_MAX_LUN 1
-#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
-#endif /* SCSI */
-
-#endif /* CONFIG_PCI */
-
-#if defined(CONFIG_TSEC_ENET)
-
-#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
-#define CONFIG_TSEC1 1
-#define CONFIG_TSEC1_NAME "eTSEC1"
-#define CONFIG_TSEC2 1
-#define CONFIG_TSEC2_NAME "eTSEC2"
-#define CONFIG_TSEC3 1
-#define CONFIG_TSEC3_NAME "eTSEC3"
-#define CONFIG_TSEC4 1
-#define CONFIG_TSEC4_NAME "eTSEC4"
-
-#define CONFIG_PIXIS_SGMII_CMD
-#define CONFIG_FSL_SGMII_RISER 1
-#define SGMII_RISER_PHY_OFFSET 0x1c
-
-#ifdef CONFIG_FSL_SGMII_RISER
-#define CONFIG_SYS_TBIPA_VALUE 0x10 /* avoid conflict with eTSEC4 paddr */
-#endif
-
-#define TSEC1_PHY_ADDR 0
-#define TSEC2_PHY_ADDR 1
-#define TSEC3_PHY_ADDR 2
-#define TSEC4_PHY_ADDR 3
-
-#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
-#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
-#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
-#define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
-
-#define TSEC1_PHYIDX 0
-#define TSEC2_PHYIDX 0
-#define TSEC3_PHYIDX 0
-#define TSEC4_PHYIDX 0
-
-#define CONFIG_ETHPRIME "eTSEC1"
-#endif /* CONFIG_TSEC_ENET */
-
-/*
- * Environment
- */
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-/*
- * USB
- */
-
-#ifdef CONFIG_USB_EHCI_HCD
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#define CONFIG_PCI_EHCI_DEVICE 0
-#endif
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 64 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
-#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#endif
-
-/*
- * Environment Configuration
- */
-#if defined(CONFIG_TSEC_ENET)
-#define CONFIG_HAS_ETH0
-#define CONFIG_HAS_ETH1
-#define CONFIG_HAS_ETH2
-#define CONFIG_HAS_ETH3
-#endif
-
-#define CONFIG_IPADDR 192.168.1.254
-
-#define CONFIG_HOSTNAME "unknown"
-#define CONFIG_ROOTPATH "/opt/nfsroot"
-#define CONFIG_BOOTFILE "uImage"
-#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
-
-#define CONFIG_SERVERIP 192.168.1.1
-#define CONFIG_GATEWAYIP 192.168.1.1
-#define CONFIG_NETMASK 255.255.255.0
-
-/* default location for tftp and bootm */
-#define CONFIG_LOADADDR 1000000
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
-"hwconfig=fsl_ddr:ctlr_intlv=bank,bank_intlv=cs0_cs1,ecc=off\0" \
-"netdev=eth0\0" \
-"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
-"tftpflash=tftpboot $loadaddr $uboot; " \
- "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
- " +$filesize; " \
- "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
- " +$filesize; " \
- "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
- " $filesize; " \
- "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
- " +$filesize; " \
- "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
- " $filesize\0" \
-"consoledev=ttyS0\0" \
-"ramdiskaddr=2000000\0" \
-"ramdiskfile=8572ds/ramdisk.uboot\0" \
-"fdtaddr=1e00000\0" \
-"fdtfile=8572ds/mpc8572ds.dtb\0" \
-"bdev=sda3\0"
-
-#define CONFIG_HDBOOT \
- "setenv bootargs root=/dev/$bdev rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_NFSBOOTCOMMAND \
- "setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$serverip:$rootpath " \
- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_RAMBOOTCOMMAND \
- "setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $ramdiskaddr $ramdiskfile;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
-
-#endif /* __CONFIG_H */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright 2007-2011 Freescale Semiconductor, Inc.
- */
-
-/*
- * MPC8610HPCD board configuration file
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <linux/stringify.h>
-
-/* High Level Configuration Options */
-#define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */
-
-/* video */
-#define CONFIG_FSL_DIU_FB
-
-#ifdef CONFIG_FSL_DIU_FB
-#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x2c000)
-#define CONFIG_VIDEO_LOGO
-#define CONFIG_VIDEO_BMP_LOGO
-#endif
-
-#ifdef RUN_DIAG
-#define CONFIG_SYS_DIAG_ADDR 0xff800000
-#endif
-
-/*
- * virtual address to be used for temporary mappings. There
- * should be 128k free at this VA.
- */
-#define CONFIG_SYS_SCRATCH_VA 0xc0000000
-
-#define CONFIG_PCI1 1 /* PCI controller 1 */
-#define CONFIG_PCIE1 1 /* PCIe 1 connected to ULI bridge */
-#define CONFIG_PCIE2 1 /* PCIe 2 connected to slot */
-#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
-#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
-#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
-
-#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
-
-#define CONFIG_BAT_RW 1 /* Use common BAT rw code */
-#define CONFIG_ALTIVEC 1
-
-/*
- * L2CR setup -- make sure this is right for your board!
- */
-#define CONFIG_SYS_L2
-#define L2_INIT 0
-#define L2_ENABLE (L2CR_L2E |0x00100000 )
-
-#ifndef CONFIG_SYS_CLK_FREQ
-#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
-#endif
-
-/*
- * Base addresses -- Note these are effective addresses where the
- * actual resources get mapped (not physical addresses)
- */
-#define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
-#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
-
-#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
-#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0
-#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR_PHYS_LOW
-
-/* DDR Setup */
-#define CONFIG_SPD_EEPROM /* Use SPD for DDR */
-#define CONFIG_DDR_SPD
-
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
-#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
-
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */
-#define CONFIG_VERY_BIG_RAM
-
-#define CONFIG_DIMM_SLOTS_PER_CTLR 1
-#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
-
-#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
-
-/* These are used when DDR doesn't use SPD. */
-#define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */
-
-#if 0 /* TODO */
-#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F
-#define CONFIG_SYS_DDR_CS0_CONFIG 0x80010202 /* Enable, no interleaving */
-#define CONFIG_SYS_DDR_TIMING_3 0x00000000
-#define CONFIG_SYS_DDR_TIMING_0 0x00260802
-#define CONFIG_SYS_DDR_TIMING_1 0x3935d322
-#define CONFIG_SYS_DDR_TIMING_2 0x14904cc8
-#define CONFIG_SYS_DDR_MODE_1 0x00480432
-#define CONFIG_SYS_DDR_MODE_2 0x00000000
-#define CONFIG_SYS_DDR_INTERVAL 0x06180100
-#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
-#define CONFIG_SYS_DDR_CLK_CTRL 0x03800000
-#define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
-#define CONFIG_SYS_DDR_OCD_STATUS 0x00000000
-#define CONFIG_SYS_DDR_CONTROL 0xe3008000 /* Type = DDR2 */
-#define CONFIG_SYS_DDR_CONTROL2 0x04400010
-
-#define CONFIG_SYS_DDR_ERR_INT_EN 0x00000000
-#define CONFIG_SYS_DDR_ERR_DIS 0x00000000
-#define CONFIG_SYS_DDR_SBE 0x000f0000
-
-#endif
-
-#define CONFIG_ID_EEPROM
-#define CONFIG_SYS_I2C_EEPROM_NXID
-#define CONFIG_ID_EEPROM
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-
-#define CONFIG_SYS_FLASH_BASE 0xf0000000 /* start of FLASH 128M */
-#define CONFIG_SYS_FLASH_BASE2 0xf8000000
-
-#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
-
-#define CONFIG_SYS_BR0_PRELIM 0xf8001001 /* port size 16bit */
-#define CONFIG_SYS_OR0_PRELIM 0xf8006e65 /* 128MB NOR Flash*/
-
-#define CONFIG_SYS_BR1_PRELIM 0xf0001001 /* port size 16bit */
-#define CONFIG_SYS_OR1_PRELIM 0xf8006e65 /* 128MB Promjet */
-#if 0 /* TODO */
-#define CONFIG_SYS_BR2_PRELIM 0xf0000000
-#define CONFIG_SYS_OR2_PRELIM 0xf0000000 /* 256MB NAND Flash - bank 1 */
-#endif
-#define CONFIG_SYS_BR3_PRELIM 0xe8000801 /* port size 8bit */
-#define CONFIG_SYS_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/
-
-#define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
-#define PIXIS_BASE 0xe8000000 /* PIXIS registers */
-#define PIXIS_ID 0x0 /* Board ID at offset 0 */
-#define PIXIS_VER 0x1 /* Board version at offset 1 */
-#define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */
-#define PIXIS_RST 0x4 /* PIXIS Reset Control register */
-#define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch */
-#define PIXIS_SPD 0x7 /* Register for SYSCLK speed */
-#define PIXIS_BRDCFG0 0x8 /* PIXIS Board Configuration Register0*/
-#define PIXIS_VCTL 0x10 /* VELA Control Register */
-#define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */
-#define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
-#define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */
-#define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */
-#define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
-#define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
-#define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
-#define CONFIG_SYS_PIXIS_VBOOT_MASK 0xC0 /* Reset altbank mask */
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
-
-#undef CONFIG_SYS_FLASH_CHECKSUM
-#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
-#define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-#define CONFIG_SYS_RAMBOOT
-#else
-#undef CONFIG_SYS_RAMBOOT
-#endif
-
-#if defined(CONFIG_SYS_RAMBOOT)
-#undef CONFIG_SPD_EEPROM
-#define CONFIG_SYS_SDRAM_SIZE 256
-#endif
-
-#define CONFIG_SYS_INIT_RAM_LOCK 1
-#ifndef CONFIG_SYS_INIT_RAM_LOCK
-#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
-#else
-#define CONFIG_SYS_INIT_RAM_ADDR 0xe4000000 /* Initial RAM address */
-#endif
-#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */
-#define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024) /* Reserved for malloc */
-
-/* Serial Port */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
-
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
-
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
-
-/* maximum size of the flat tree (8K) */
-#define OF_FLAT_TREE_MAX_SIZE 8192
-
-/*
- * I2C
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED 400000
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
-#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
-
-/*
- * General PCI
- * Addresses are mapped 1-1.
- */
-#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
-#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS
-#define CONFIG_SYS_PCI1_MEM_VIRT CONFIG_SYS_PCI1_MEM_BUS
-#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCI1_IO_BUS 0x0000000
-#define CONFIG_SYS_PCI1_IO_PHYS 0xe1000000
-#define CONFIG_SYS_PCI1_IO_VIRT 0xe1000000
-#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
-
-/* controller 1, Base address 0xa000 */
-#define CONFIG_SYS_PCIE1_NAME "ULI"
-#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS
-#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000
-#define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */
-
-/* controller 2, Base Address 0x9000 */
-#define CONFIG_SYS_PCIE2_NAME "Slot 1"
-#define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS
-#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 /* reuse mem LAW */
-#define CONFIG_SYS_PCIE2_IO_PHYS 0xe2000000
-#define CONFIG_SYS_PCIE2_IO_SIZE 0x00100000 /* 1M */
-
-#if defined(CONFIG_PCI)
-
-#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-
-#define CONFIG_ULI526X
-
-/************************************************************
- * USB support
- ************************************************************/
-#define CONFIG_PCI_OHCI 1
-#define CONFIG_USB_OHCI_NEW 1
-#define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci"
-#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
-#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1
-
-#if !defined(CONFIG_PCI_PNP)
-#define PCI_ENET0_IOADDR 0xe0000000
-#define PCI_ENET0_MEMADDR 0xe0000000
-#define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
-#endif
-
-#ifdef CONFIG_SCSI_AHCI
-#define CONFIG_SATA_ULI5288
-#define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
-#define CONFIG_SYS_SCSI_MAX_LUN 1
-#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
-#endif
-
-#endif /* CONFIG_PCI */
-
-/*
- * BAT0 2G Cacheable, non-guarded
- * 0x0000_0000 2G DDR
- */
-#define CONFIG_SYS_DBAT0L (BATL_PP_RW)
-#define CONFIG_SYS_IBAT0L (BATL_PP_RW)
-
-/*
- * BAT1 1G Cache-inhibited, guarded
- * 0x8000_0000 256M PCI-1 Memory
- * 0xa000_0000 256M PCI-Express 1 Memory
- * 0x9000_0000 256M PCI-Express 2 Memory
- */
-
-#define CONFIG_SYS_DBAT1L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCI1_MEM_VIRT | BATU_BL_1G | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U
-
-/*
- * BAT2 16M Cache-inhibited, guarded
- * 0xe100_0000 1M PCI-1 I/O
- */
-
-#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI1_IO_VIRT | BATU_BL_16M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
-
-/*
- * BAT3 4M Cache-inhibited, guarded
- * 0xe000_0000 4M CCSR
- */
-
-#define CONFIG_SYS_DBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR | BATU_BL_1M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U
-
-#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
-#define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
- | BATL_PP_RW | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \
- | BATU_BL_1M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
- | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU
-#endif
-
-/*
- * BAT4 32M Cache-inhibited, guarded
- * 0xe200_0000 1M PCI-Express 2 I/O
- * 0xe300_0000 1M PCI-Express 1 I/O
- */
-
-#define CONFIG_SYS_DBAT4L (CONFIG_SYS_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE2_IO_PHYS | BATU_BL_32M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U
-
-/*
- * BAT5 128K Cacheable, non-guarded
- * 0xe400_0000 128K Init RAM for stack in the CPU DCache (no backing memory)
- */
-#define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L
-#define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U
-
-/*
- * BAT6 256M Cache-inhibited, guarded
- * 0xf000_0000 256M FLASH
- */
-#define CONFIG_SYS_DBAT6L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT6U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT6L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U
-
-/* Map the last 1M of flash where we're running from reset */
-#define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
- | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
- | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY
-
-/*
- * BAT7 4M Cache-inhibited, guarded
- * 0xe800_0000 4M PIXIS
- */
-#define CONFIG_SYS_DBAT7L (PIXIS_BASE | BATL_PP_RW | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT7U (PIXIS_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT7L (PIXIS_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT7U CONFIG_SYS_DBAT7U
-
-/*
- * Environment
- */
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-#define CONFIG_WATCHDOG /* watchdog enabled */
-#define CONFIG_SYS_WATCHDOG_FREQ 5000 /* Feed interval, 5s */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux*/
-#define CONFIG_SYS_BOOTM_LEN (256 << 20) /* Increase max gunzip size */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#endif
-
-/*
- * Environment Configuration
- */
-#define CONFIG_IPADDR 192.168.1.100
-
-#define CONFIG_HOSTNAME "unknown"
-#define CONFIG_ROOTPATH "/opt/nfsroot"
-#define CONFIG_BOOTFILE "uImage"
-#define CONFIG_UBOOTPATH 8610hpcd/u-boot.bin
-
-#define CONFIG_SERVERIP 192.168.1.1
-#define CONFIG_GATEWAYIP 192.168.1.1
-#define CONFIG_NETMASK 255.255.255.0
-
-/* default location for tftp and bootm */
-#define CONFIG_LOADADDR 0x10000000
-
-#if defined(CONFIG_PCI1)
-#define PCI_ENV \
- "pcireg=md ${a}000 3; echo o;md ${a}c00 25; echo i; md ${a}da0 15;" \
- "echo e;md ${a}e00 9\0" \
- "pci1regs=setenv a e0008; run pcireg\0" \
- "pcierr=md ${a}e00 8; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;" \
- "pci d.w $b.0 56 1\0" \
- "pcierrc=mw ${a}e00 ffffffff; pci w.b $b.0 7 ff; pci w.w $b.0 1e ffff;" \
- "pci w.w $b.0 56 ffff\0" \
- "pci1err=setenv a e0008; run pcierr\0" \
- "pci1errc=setenv a e0008; run pcierrc\0"
-#else
-#define PCI_ENV ""
-#endif
-
-#if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2)
-#define PCIE_ENV \
- "pciereg=md ${a}000 6; md ${a}020 4; md ${a}bf8 2; echo o;md ${a}c00 25;" \
- "echo i; md ${a}da0 15; echo e;md ${a}e00 e; echo d; md ${a}f00 c\0" \
- "pcie1regs=setenv a e000a; run pciereg\0" \
- "pcie2regs=setenv a e0009; run pciereg\0" \
- "pcieerr=md ${a}020 1; md ${a}e00; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;"\
- "pci d.w $b.0 56 1; pci d $b.0 104 1; pci d $b.0 110 1;" \
- "pci d $b.0 130 1\0" \
- "pcieerrc=mw ${a}020 ffffffff; mw ${a}e00 ffffffff; pci w.b $b.0 7 ff;"\
- "pci w.w $b.0 1e ffff; pci w.w $b.0 56 ffff; pci w $b.0 104 ffffffff;" \
- "pci w $b.0 110 ffffffff; pci w $b.0 130 ffffffff\0" \
- "pciecfg=pci d $b.0 0 20; pci d $b.0 100 e; pci d $b.0 400 69\0" \
- "pcie1err=setenv a e000a; run pcieerr\0" \
- "pcie2err=setenv a e0009; run pcieerr\0" \
- "pcie1errc=setenv a e000a; run pcieerrc\0" \
- "pcie2errc=setenv a e0009; run pcieerrc\0"
-#else
-#define PCIE_ENV ""
-#endif
-
-#define DMA_ENV \
- "dma0=mw ${d}104 ffffffff;mw ${d}110 50000;mw ${d}114 $sad0;mw ${d}118 50000;"\
- "mw ${d}120 $bc0;mw ${d}100 f03c404; mw ${d}11c $dad0; md ${d}100 9\0" \
- "dma1=mw ${d}184 ffffffff;mw ${d}190 50000;mw ${d}194 $sad1;mw ${d}198 50000;"\
- "mw ${d}1a0 $bc1;mw ${d}180 f03c404; mw ${d}19c $dad1; md ${d}180 9\0" \
- "dma2=mw ${d}204 ffffffff;mw ${d}210 50000;mw ${d}214 $sad2;mw ${d}218 50000;"\
- "mw ${d}220 $bc2;mw ${d}200 f03c404; mw ${d}21c $dad2; md ${d}200 9\0" \
- "dma3=mw ${d}284 ffffffff;mw ${d}290 50000;mw ${d}294 $sad3;mw ${d}298 50000;"\
- "mw ${d}2a0 $bc3;mw ${d}280 f03c404; mw ${d}29c $dad3; md ${d}280 9\0"
-
-#ifdef ENV_DEBUG
-#define CONFIG_EXTRA_ENV_SETTINGS \
-"netdev=eth0\0" \
-"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
-"tftpflash=tftpboot $loadaddr $uboot; " \
- "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
- " +$filesize; " \
- "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
- " +$filesize; " \
- "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
- " $filesize; " \
- "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
- " +$filesize; " \
- "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
- " $filesize\0" \
-"consoledev=ttyS0\0" \
-"ramdiskaddr=0x18000000\0" \
-"ramdiskfile=8610hpcd/ramdisk.uboot\0" \
-"fdtaddr=0x17c00000\0" \
-"fdtfile=8610hpcd/mpc8610_hpcd.dtb\0" \
-"bdev=sda3\0" \
-"en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \
-"dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \
-"maxcpus=1" \
-"eoi=mw e00400b0 0\0" \
-"iack=md e00400a0 1\0" \
-"ddrreg=md ${a}000 8; md ${a}080 8;md ${a}100 d; md ${a}140 4;" \
- "md ${a}bf0 4; md ${a}e00 3; md ${a}e20 3; md ${a}e40 7;" \
- "md ${a}f00 5\0" \
-"ddr1regs=setenv a e0002; run ddrreg\0" \
-"gureg=md ${a}000 2c; md ${a}0b0 1; md ${a}0c0 1; md ${a}800 1;" \
- "md ${a}900 6; md ${a}a00 1; md ${a}b20 3; md ${a}e00 1;" \
- "md ${a}e60 1; md ${a}ef0 1d\0" \
-"guregs=setenv a e00e0; run gureg\0" \
-"mcmreg=md ${a}000 1b; md ${a}bf8 2; md ${a}e00 5\0" \
-"mcmregs=setenv a e0001; run mcmreg\0" \
-"diuregs=md e002c000 1d\0" \
-"dium=mw e002c01c\0" \
-"diuerr=md e002c014 1\0" \
-"pmregs=md e00e1000 2b\0" \
-"lawregs=md e0000c08 4b\0" \
-"lbcregs=md e0005000 36\0" \
-"dma0regs=md e0021100 12\0" \
-"dma1regs=md e0021180 12\0" \
-"dma2regs=md e0021200 12\0" \
-"dma3regs=md e0021280 12\0" \
- PCI_ENV \
- PCIE_ENV \
- DMA_ENV
-#else
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
- "consoledev=ttyS0\0" \
- "ramdiskaddr=0x18000000\0" \
- "ramdiskfile=8610hpcd/ramdisk.uboot\0" \
- "fdtaddr=0x17c00000\0" \
- "fdtfile=8610hpcd/mpc8610_hpcd.dtb\0" \
- "bdev=sda3\0"
-#endif
-
-#define CONFIG_NFSBOOTCOMMAND \
- "setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$serverip:$rootpath " \
- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_RAMBOOTCOMMAND \
- "setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $ramdiskaddr $ramdiskfile;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#define CONFIG_BOOTCOMMAND \
- "setenv bootargs root=/dev/$bdev rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
-
-#endif /* __CONFIG_H */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2006, 2010-2011 Freescale Semiconductor.
- *
- * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
- */
-
-/*
- * MPC8641HPCN board configuration file
- *
- * Make sure you change the MAC address and other network params first,
- * search for CONFIG_SERVERIP, etc. in this file.
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <linux/stringify.h>
-
-/* High Level Configuration Options */
-#define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */
-
-/*
- * default CCSRBAR is at 0xff700000
- * assume U-Boot is less than 0.5MB
- */
-
-#ifdef RUN_DIAG
-#define CONFIG_SYS_DIAG_ADDR CONFIG_SYS_FLASH_BASE
-#endif
-
-/*
- * virtual address to be used for temporary mappings. There
- * should be 128k free at this VA.
- */
-#define CONFIG_SYS_SCRATCH_VA 0xe0000000
-
-#define CONFIG_SYS_SRIO
-#define CONFIG_SRIO1 /* SRIO port 1 */
-
-#define CONFIG_PCIE1 1 /* PCIE controller 1 (ULI bridge) */
-#define CONFIG_PCIE2 1 /* PCIE controller 2 (slot) */
-#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
-#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
-
-#define CONFIG_BAT_RW 1 /* Use common BAT rw code */
-
-#define CONFIG_ALTIVEC 1
-
-/*
- * L2CR setup -- make sure this is right for your board!
- */
-#define CONFIG_SYS_L2
-#define L2_INIT 0
-#define L2_ENABLE (L2CR_L2E)
-
-#ifndef CONFIG_SYS_CLK_FREQ
-#ifndef __ASSEMBLY__
-extern unsigned long get_board_sys_clk(unsigned long dummy);
-#endif
-#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
-#endif
-
-/*
- * With the exception of PCI Memory and Rapid IO, most devices will simply
- * add CONFIG_SYS_PHYS_ADDR_HIGH to the front of the 32-bit VA to get the PA
- * when 36-bit is enabled. When 36-bit is not enabled, these bits are 0.
- */
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PHYS_ADDR_HIGH 0x0000000f
-#else
-#define CONFIG_SYS_PHYS_ADDR_HIGH 0x00000000
-#endif
-
-/*
- * Base addresses -- Note these are effective addresses where the
- * actual resources get mapped (not physical addresses)
- */
-#define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */
-#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
-
-/* Physical addresses */
-#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
-#define CONFIG_SYS_CCSRBAR_PHYS_HIGH CONFIG_SYS_PHYS_ADDR_HIGH
-#define CONFIG_SYS_CCSRBAR_PHYS \
- PAIRED_PHYS_TO_PHYS(CONFIG_SYS_CCSRBAR_PHYS_LOW, \
- CONFIG_SYS_CCSRBAR_PHYS_HIGH)
-
-#define CONFIG_HWCONFIG /* use hwconfig to control memory interleaving */
-
-/*
- * DDR Setup
- */
-#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
-#define CONFIG_DDR_SPD
-
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
-#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
-
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */
-#define CONFIG_VERY_BIG_RAM
-
-#define CONFIG_DIMM_SLOTS_PER_CTLR 2
-#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
-
-/*
- * I2C addresses of SPD EEPROMs
- */
-#define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */
-#define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 0 DIMM 1 */
-#define SPD_EEPROM_ADDRESS3 0x53 /* CTLR 1 DIMM 0 */
-#define SPD_EEPROM_ADDRESS4 0x54 /* CTLR 1 DIMM 1 */
-
-/*
- * These are used when DDR doesn't use SPD.
- */
-#define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */
-#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F
-#define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */
-#define CONFIG_SYS_DDR_TIMING_3 0x00000000
-#define CONFIG_SYS_DDR_TIMING_0 0x00260802
-#define CONFIG_SYS_DDR_TIMING_1 0x39357322
-#define CONFIG_SYS_DDR_TIMING_2 0x14904cc8
-#define CONFIG_SYS_DDR_MODE_1 0x00480432
-#define CONFIG_SYS_DDR_MODE_2 0x00000000
-#define CONFIG_SYS_DDR_INTERVAL 0x06090100
-#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
-#define CONFIG_SYS_DDR_CLK_CTRL 0x03800000
-#define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
-#define CONFIG_SYS_DDR_OCD_STATUS 0x00000000
-#define CONFIG_SYS_DDR_CONTROL 0xe3008000 /* Type = DDR2 */
-#define CONFIG_SYS_DDR_CONTROL2 0x04400000
-
-#define CONFIG_ID_EEPROM
-#define CONFIG_SYS_I2C_EEPROM_NXID
-#define CONFIG_ID_EEPROM
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-
-#define CONFIG_SYS_FLASH_BASE 0xef800000 /* start of FLASH 8M */
-#define CONFIG_SYS_FLASH_BASE_PHYS_LOW CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_FLASH_BASE_PHYS \
- PAIRED_PHYS_TO_PHYS(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \
- CONFIG_SYS_PHYS_ADDR_HIGH)
-
-#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
-
-#define CONFIG_SYS_BR0_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
- | 0x00001001) /* port size 16bit */
-#define CONFIG_SYS_OR0_PRELIM 0xff806ff7 /* 8MB Boot Flash area*/
-
-#define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(CF_BASE_PHYS) \
- | 0x00001001) /* port size 16bit */
-#define CONFIG_SYS_OR2_PRELIM 0xffffeff7 /* 32k Compact Flash */
-
-#define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) \
- | 0x00000801) /* port size 8bit */
-#define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32k PIXIS area*/
-
-/*
- * The LBC_BASE is the base of the region that contains the PIXIS and the CF.
- * The PIXIS and CF by themselves aren't large enough to take up the 128k
- * required for the smallest BAT mapping, so there's a 64k hole.
- */
-#define CONFIG_SYS_LBC_BASE 0xffde0000
-#define CONFIG_SYS_LBC_BASE_PHYS_LOW CONFIG_SYS_LBC_BASE
-
-#define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
-#define PIXIS_BASE (CONFIG_SYS_LBC_BASE + 0x00010000)
-#define PIXIS_BASE_PHYS_LOW (CONFIG_SYS_LBC_BASE_PHYS_LOW + 0x00010000)
-#define PIXIS_BASE_PHYS PAIRED_PHYS_TO_PHYS(PIXIS_BASE_PHYS_LOW, \
- CONFIG_SYS_PHYS_ADDR_HIGH)
-#define PIXIS_SIZE 0x00008000 /* 32k */
-#define PIXIS_ID 0x0 /* Board ID at offset 0 */
-#define PIXIS_VER 0x1 /* Board version at offset 1 */
-#define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */
-#define PIXIS_RST 0x4 /* PIXIS Reset Control register */
-#define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch register */
-#define PIXIS_SPD 0x7 /* Register for SYSCLK speed */
-#define PIXIS_VCTL 0x10 /* VELA Control Register */
-#define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */
-#define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
-#define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */
-#define PIXIS_VBOOT_FMAP 0x80 /* VBOOT - CFG_FLASHMAP */
-#define PIXIS_VBOOT_FBANK 0x40 /* VBOOT - CFG_FLASHBANK */
-#define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */
-#define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
-#define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
-#define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
-#define CONFIG_SYS_PIXIS_VBOOT_MASK 0x40 /* Reset altbank mask*/
-
-/* Compact flash shares a BAT with PIXIS; make sure they're contiguous */
-#define CF_BASE (PIXIS_BASE + PIXIS_SIZE)
-#define CF_BASE_PHYS (PIXIS_BASE_PHYS + PIXIS_SIZE)
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
-
-#undef CONFIG_SYS_FLASH_CHECKSUM
-#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
-#define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-#define CONFIG_SYS_RAMBOOT
-#else
-#undef CONFIG_SYS_RAMBOOT
-#endif
-
-#if defined(CONFIG_SYS_RAMBOOT)
-#undef CONFIG_SPD_EEPROM
-#define CONFIG_SYS_SDRAM_SIZE 256
-#endif
-
-#define CONFIG_SYS_INIT_RAM_LOCK 1
-#ifndef CONFIG_SYS_INIT_RAM_LOCK
-#define CONFIG_SYS_INIT_RAM_ADDR 0x0fd00000 /* Initial RAM address */
-#else
-#define CONFIG_SYS_INIT_RAM_ADDR 0xf8400000 /* Initial RAM address */
-#endif
-#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
-#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
-
-/* Serial Port */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
-
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
-
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
-
-/*
- * I2C
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED 400000
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x3100
-#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
-
-/*
- * RapidIO MMU
- */
-#define CONFIG_SYS_SRIO1_MEM_BASE 0x80000000 /* base address */
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_SRIO1_MEM_PHYS_LOW 0x00000000
-#define CONFIG_SYS_SRIO1_MEM_PHYS_HIGH 0x0000000c
-#else
-#define CONFIG_SYS_SRIO1_MEM_PHYS_LOW CONFIG_SYS_SRIO1_MEM_BASE
-#define CONFIG_SYS_SRIO1_MEM_PHYS_HIGH 0x00000000
-#endif
-#define CONFIG_SYS_SRIO1_MEM_PHYS \
- PAIRED_PHYS_TO_PHYS(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \
- CONFIG_SYS_SRIO1_MEM_PHYS_HIGH)
-#define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 128M */
-
-/*
- * General PCI
- * Addresses are mapped 1-1.
- */
-
-#define CONFIG_SYS_PCIE1_NAME "ULI"
-#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS_LOW 0x00000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS_HIGH 0x0000000c
-#else
-#define CONFIG_SYS_PCIE1_MEM_BUS CONFIG_SYS_PCIE1_MEM_VIRT
-#define CONFIG_SYS_PCIE1_MEM_PHYS_LOW CONFIG_SYS_PCIE1_MEM_VIRT
-#define CONFIG_SYS_PCIE1_MEM_PHYS_HIGH 0x00000000
-#endif
-#define CONFIG_SYS_PCIE1_MEM_PHYS \
- PAIRED_PHYS_TO_PHYS(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \
- CONFIG_SYS_PCIE1_MEM_PHYS_HIGH)
-#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
-#define CONFIG_SYS_PCIE1_IO_PHYS_LOW CONFIG_SYS_PCIE1_IO_VIRT
-#define CONFIG_SYS_PCIE1_IO_PHYS \
- PAIRED_PHYS_TO_PHYS(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \
- CONFIG_SYS_PHYS_ADDR_HIGH)
-#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64K */
-
-#ifdef CONFIG_PHYS_64BIT
-/*
- * Use the same PCI bus address on PCIE1 and PCIE2 if we have PHYS_64BIT.
- * This will increase the amount of PCI address space available for
- * for mapping RAM.
- */
-#define CONFIG_SYS_PCIE2_MEM_BUS CONFIG_SYS_PCIE1_MEM_BUS
-#else
-#define CONFIG_SYS_PCIE2_MEM_BUS (CONFIG_SYS_PCIE1_MEM_BUS \
- + CONFIG_SYS_PCIE1_MEM_SIZE)
-#endif
-#define CONFIG_SYS_PCIE2_MEM_VIRT (CONFIG_SYS_PCIE1_MEM_VIRT \
- + CONFIG_SYS_PCIE1_MEM_SIZE)
-#define CONFIG_SYS_PCIE2_MEM_PHYS_LOW (CONFIG_SYS_PCIE1_MEM_PHYS_LOW \
- + CONFIG_SYS_PCIE1_MEM_SIZE)
-#define CONFIG_SYS_PCIE2_MEM_PHYS_HIGH CONFIG_SYS_PCIE1_MEM_PHYS_HIGH
-#define CONFIG_SYS_PCIE2_MEM_PHYS (CONFIG_SYS_PCIE1_MEM_PHYS \
- + CONFIG_SYS_PCIE1_MEM_SIZE)
-#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE2_IO_VIRT (CONFIG_SYS_PCIE1_IO_VIRT \
- + CONFIG_SYS_PCIE1_IO_SIZE)
-#define CONFIG_SYS_PCIE2_IO_PHYS_LOW (CONFIG_SYS_PCIE1_IO_PHYS_LOW \
- + CONFIG_SYS_PCIE1_IO_SIZE)
-#define CONFIG_SYS_PCIE2_IO_PHYS (CONFIG_SYS_PCIE1_IO_PHYS \
- + CONFIG_SYS_PCIE1_IO_SIZE)
-#define CONFIG_SYS_PCIE2_IO_SIZE CONFIG_SYS_PCIE1_IO_SIZE
-
-#if defined(CONFIG_PCI)
-
-#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-
-
-/************************************************************
- * USB support
- ************************************************************/
-#define CONFIG_PCI_OHCI 1
-#define CONFIG_USB_OHCI_NEW 1
-#define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci"
-#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
-#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1
-
-/*PCIE video card used*/
-#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE2_IO_VIRT
-
-/*PCI video card used*/
-/*#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT*/
-
-/* video */
-
-#if defined(CONFIG_VIDEO)
-#define CONFIG_BIOSEMU
-#define CONFIG_ATI_RADEON_FB
-#define CONFIG_VIDEO_LOGO
-#define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE2_IO_VIRT
-#endif
-
-#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-
-#ifdef CONFIG_SCSI_AHCI
-#define CONFIG_SATA_ULI5288
-#define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
-#define CONFIG_SYS_SCSI_MAX_LUN 1
-#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
-#endif
-
-#endif /* CONFIG_PCI */
-
-#if defined(CONFIG_TSEC_ENET)
-#define CONFIG_TSEC1 1
-#define CONFIG_TSEC1_NAME "eTSEC1"
-#define CONFIG_TSEC2 1
-#define CONFIG_TSEC2_NAME "eTSEC2"
-#define CONFIG_TSEC3 1
-#define CONFIG_TSEC3_NAME "eTSEC3"
-#define CONFIG_TSEC4 1
-#define CONFIG_TSEC4_NAME "eTSEC4"
-
-#define TSEC1_PHY_ADDR 0
-#define TSEC2_PHY_ADDR 1
-#define TSEC3_PHY_ADDR 2
-#define TSEC4_PHY_ADDR 3
-#define TSEC1_PHYIDX 0
-#define TSEC2_PHYIDX 0
-#define TSEC3_PHYIDX 0
-#define TSEC4_PHYIDX 0
-#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
-#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
-#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
-#define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
-
-#define CONFIG_ETHPRIME "eTSEC1"
-
-#endif /* CONFIG_TSEC_ENET */
-
-#ifdef CONFIG_PHYS_64BIT
-#define PHYS_HIGH_TO_BXPN(x) ((x & 0x0000000e) << 8)
-#define PHYS_HIGH_TO_BX(x) ((x & 0x00000001) << 2)
-
-/* Put physical address into the BAT format */
-#define BAT_PHYS_ADDR(low, high) \
- (low | PHYS_HIGH_TO_BXPN(high) | PHYS_HIGH_TO_BX(high))
-/* Convert high/low pairs to actual 64-bit value */
-#define PAIRED_PHYS_TO_PHYS(low, high) (low | ((u64)high << 32))
-#else
-/* 32-bit systems just ignore the "high" bits */
-#define BAT_PHYS_ADDR(low, high) (low)
-#define PAIRED_PHYS_TO_PHYS(low, high) (low)
-#endif
-
-/*
- * BAT0 DDR
- */
-#define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
-
-/*
- * BAT1 LBC (PIXIS/CF)
- */
-#define CONFIG_SYS_DBAT1L (BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS_LOW, \
- CONFIG_SYS_PHYS_ADDR_HIGH) \
- | BATL_PP_RW | BATL_CACHEINHIBIT | \
- BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT1U (CONFIG_SYS_LBC_BASE | BATU_BL_128K \
- | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT1L (BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS_LOW, \
- CONFIG_SYS_PHYS_ADDR_HIGH) \
- | BATL_PP_RW | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U
-
-/* if CONFIG_PCI:
- * BAT2 PCIE1 and PCIE1 MEM
- * if CONFIG_RIO
- * BAT2 Rapidio Memory
- */
-#ifdef CONFIG_PCI
-#define CONFIG_PCI_INDIRECT_BRIDGE
-#define CONFIG_SYS_DBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \
- CONFIG_SYS_PCIE1_MEM_PHYS_HIGH) \
- | BATL_PP_RW | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCIE1_MEM_VIRT | BATU_BL_1G \
- | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \
- CONFIG_SYS_PCIE1_MEM_PHYS_HIGH) \
- | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
-#else /* CONFIG_RIO */
-#define CONFIG_SYS_DBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \
- CONFIG_SYS_SRIO1_MEM_PHYS_HIGH) \
- | BATL_PP_RW | BATL_CACHEINHIBIT | \
- BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT2U (CONFIG_SYS_SRIO1_MEM_BASE | BATU_BL_512M \
- | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \
- CONFIG_SYS_SRIO1_MEM_PHYS_HIGH) \
- | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
-#endif
-
-/*
- * BAT3 CCSR Space
- */
-#define CONFIG_SYS_DBAT3L (BAT_PHYS_ADDR(CONFIG_SYS_CCSRBAR_PHYS_LOW, \
- CONFIG_SYS_CCSRBAR_PHYS_HIGH) \
- | BATL_PP_RW | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR | BATU_BL_1M | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_IBAT3L (BAT_PHYS_ADDR(CONFIG_SYS_CCSRBAR_PHYS_LOW, \
- CONFIG_SYS_CCSRBAR_PHYS_HIGH) \
- | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U
-
-#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
-#define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
- | BATL_PP_RW | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \
- | BATU_BL_1M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
- | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU
-#endif
-
-/*
- * BAT4 PCIE1_IO and PCIE2_IO
- */
-#define CONFIG_SYS_DBAT4L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \
- CONFIG_SYS_PHYS_ADDR_HIGH) \
- | BATL_PP_RW | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE1_IO_VIRT | BATU_BL_128K \
- | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT4L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \
- CONFIG_SYS_PHYS_ADDR_HIGH) \
- | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U
-
-/*
- * BAT5 Init RAM for stack in the CPU DCache (no backing memory)
- */
-#define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L
-#define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U
-
-/*
- * BAT6 FLASH
- */
-#define CONFIG_SYS_DBAT6L (BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \
- CONFIG_SYS_PHYS_ADDR_HIGH) \
- | BATL_PP_RW | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT6U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_IBAT6L (BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \
- CONFIG_SYS_PHYS_ADDR_HIGH) \
- | BATL_PP_RW | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U
-
-/* Map the last 1M of flash where we're running from reset */
-#define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
- | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
- | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY
-
-/*
- * BAT7 FREE - used later for tmp mappings
- */
-#define CONFIG_SYS_DBAT7L 0x00000000
-#define CONFIG_SYS_DBAT7U 0x00000000
-#define CONFIG_SYS_IBAT7L 0x00000000
-#define CONFIG_SYS_IBAT7U 0x00000000
-
-/*
- * Environment
- */
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux*/
-#define CONFIG_SYS_BOOTM_LEN (256 << 20) /* Increase max gunzip size */
-
-#if defined(CONFIG_CMD_KGDB)
- #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#endif
-
-/*
- * Environment Configuration
- */
-
-#define CONFIG_HAS_ETH0 1
-#define CONFIG_HAS_ETH1 1
-#define CONFIG_HAS_ETH2 1
-#define CONFIG_HAS_ETH3 1
-
-#define CONFIG_IPADDR 192.168.1.100
-
-#define CONFIG_HOSTNAME "unknown"
-#define CONFIG_ROOTPATH "/opt/nfsroot"
-#define CONFIG_BOOTFILE "uImage"
-#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
-
-#define CONFIG_SERVERIP 192.168.1.1
-#define CONFIG_GATEWAYIP 192.168.1.1
-#define CONFIG_NETMASK 255.255.255.0
-
-/* default location for tftp and bootm */
-#define CONFIG_LOADADDR 0x10000000
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
- "tftpflash=tftpboot $loadaddr $uboot; " \
- "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
- " +$filesize; " \
- "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
- " +$filesize; " \
- "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
- " $filesize; " \
- "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
- " +$filesize; " \
- "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
- " $filesize\0" \
- "consoledev=ttyS0\0" \
- "ramdiskaddr=0x18000000\0" \
- "ramdiskfile=your.ramdisk.u-boot\0" \
- "fdtaddr=0x17c00000\0" \
- "fdtfile=mpc8641_hpcn.dtb\0" \
- "en-wd=mw.b ffdf0010 0x08; echo -expect:- 08; md.b ffdf0010 1\0" \
- "dis-wd=mw.b ffdf0010 0x00; echo -expect:- 00; md.b ffdf0010 1\0" \
- "maxcpus=2"
-
-#define CONFIG_NFSBOOTCOMMAND \
- "setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$serverip:$rootpath " \
- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_RAMBOOTCOMMAND \
- "setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $ramdiskaddr $ramdiskfile;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
-
-#endif /* __CONFIG_H */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Configuation settings for the Renesas Solutions Migo-R board
- *
- * Copyright (C) 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
- */
-
-#ifndef __MIGO_R_H
-#define __MIGO_R_H
-
-#define CONFIG_CPU_SH7722 1
-
-#define CONFIG_DISPLAY_BOARDINFO
-
-/* SMC9111 */
-#define CONFIG_SMC91111
-#define CONFIG_SMC91111_BASE (0xB0000000)
-
-/* MEMORY */
-#define MIGO_R_SDRAM_BASE (0x8C000000)
-#define MIGO_R_FLASH_BASE_1 (0xA0000000)
-#define MIGO_R_FLASH_BANK_SIZE (64 * 1024 * 1024)
-
-#define CONFIG_SYS_PBSIZE 256 /* Buffer size for Console output */
-#define CONFIG_SYS_BAUDRATE_TABLE { 115200 } /* List of legal baudrate settings for this board */
-
-/* SCIF */
-#define CONFIG_CONS_SCIF0 1
-
-/* Enable alternate, more extensive, memory test */
-/* Scratch address used by the alternate memory test */
-
-/* Enable temporary baudrate change while serial download */
-#undef CONFIG_SYS_LOADS_BAUD_CHANGE
-
-#define CONFIG_SYS_SDRAM_BASE (MIGO_R_SDRAM_BASE)
-/* maybe more, but if so u-boot doesn't know about it... */
-#define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024)
-/* default load address for scripts ?!? */
-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024)
-
-/* Address of u-boot image in Flash (NOT run time address in SDRAM) ?!? */
-#define CONFIG_SYS_MONITOR_BASE (MIGO_R_FLASH_BASE_1)
-/* Monitor size */
-#define CONFIG_SYS_MONITOR_LEN (128 * 1024)
-/* Size of DRAM reserved for malloc() use */
-#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
-#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
-
-/* FLASH */
-#undef CONFIG_SYS_FLASH_QUIET_TEST
-/* print 'E' for empty sector on flinfo */
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-/* Physical start address of Flash memory */
-#define CONFIG_SYS_FLASH_BASE (MIGO_R_FLASH_BASE_1)
-/* Max number of sectors on each Flash chip */
-#define CONFIG_SYS_MAX_FLASH_SECT 512
-
-/* if you use all NOR Flash , you change dip-switch. Please see MIGO_R01 Manual. */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE + (0 * MIGO_R_FLASH_BANK_SIZE) }
-
-/* Timeout for Flash erase operations (in ms) */
-#define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000)
-/* Timeout for Flash write operations (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000)
-/* Timeout for Flash set sector lock bit operations (in ms) */
-#define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000)
-/* Timeout for Flash clear lock bit operations (in ms) */
-#define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000)
-
-/* Use hardware flash sectors protection instead of U-Boot software protection */
-#undef CONFIG_SYS_DIRECT_FLASH_TFTP
-
-/* ENV setting */
-/* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */
-
-/* Board Clock */
-#define CONFIG_SYS_CLK_FREQ 33333333
-#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
-
-#endif /* __MIGO_R_H */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2012 Bluegiga Technologies Oy
- *
- * Authors:
- * Veli-Pekka Peltola <veli-pekka.peltola@bluegiga.com>
- * Lauri Hintsala <lauri.hintsala@bluegiga.com>
- *
- * Based on m28evk.h:
- * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
- * on behalf of DENX Software Engineering GmbH
- */
-#ifndef __CONFIGS_APX4DEVKIT_H__
-#define __CONFIGS_APX4DEVKIT_H__
-
-/* System configurations */
-#define CONFIG_MACH_TYPE MACH_TYPE_APX4DEVKIT
-
-/* Memory configuration */
-#define PHYS_SDRAM_1 0x40000000 /* Base address */
-#define PHYS_SDRAM_1_SIZE 0x20000000 /* Max 512 MB RAM */
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-
-/* Environment is in NAND */
-#if defined(CONFIG_CMD_NAND) && defined(CONFIG_ENV_IS_IN_NAND)
-#define CONFIG_ENV_RANGE (384 * 1024)
-#endif
-
-/* UBI and NAND partitioning */
-
-/* FEC Ethernet on SoC */
-#ifdef CONFIG_CMD_NET
-#define CONFIG_FEC_MXC
-#define CONFIG_ETHPRIME "FEC"
-#define CONFIG_FEC_MXC_PHYADDR 0
-#define IMX_FEC_BASE MXS_ENET0_BASE
-#endif
-
-/* USB */
-#ifdef CONFIG_CMD_USB
-#define CONFIG_EHCI_MXS_PORT1
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
-#endif
-
-/* Boot Linux */
-#define CONFIG_BOOTFILE "uImage"
-#define CONFIG_BOOTCOMMAND "run bootcmd_nand"
-#define CONFIG_LOADADDR 0x41000000
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-#define CONFIG_SERIAL_TAG
-#define CONFIG_REVISION_TAG
-
-/* Extra Environments */
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
- "verify=no\0" \
- "bootcmd=run bootcmd_nand\0" \
- "kernelargs=console=tty0 console=ttyAMA0,115200 consoleblank=0\0" \
- "bootargs_nand=" \
- "setenv bootargs ${kernelargs} ubi.mtd=3,2048 " \
- "root=ubi0:rootfs rootfstype=ubifs ${mtdparts} rw\0" \
- "bootcmd_nand=" \
- "run bootargs_nand && ubi part root 2048 && " \
- "ubifsmount ubi:rootfs && ubifsload 41000000 boot/uImage && " \
- "bootm 41000000\0" \
- "bootargs_mmc=" \
- "setenv bootargs ${kernelargs} " \
- "root=/dev/mmcblk0p2 rootwait ${mtdparts} rw\0" \
- "bootcmd_mmc=" \
- "run bootargs_mmc && mmc rescan && " \
- "ext2load mmc 0:2 41000000 boot/uImage && bootm 41000000\0" \
-""
-
-/* The rest of the configuration is shared */
-#include <configs/mxs.h>
-
-#endif /* __CONFIGS_APX4DEVKIT_H__ */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-
-#ifndef _CONFIG_DB_88F6281_BP_H
-#define _CONFIG_DB_88F6281_BP_H
-
-/*
- * High Level Configuration Options (easy to change)
- */
-#define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */
-#define CONFIG_KW88F6281 1 /* SOC Name */
-#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
-#define CONFIG_SYS_TCLK 166666667
-#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage.cfg
-
-/* additions for new ARM relocation support */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-
-#define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */
-#define CONFIG_KIRKWOOD_PCIE_INIT /* Enable PCIE Port0 */
-#define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */
-#define CONFIG_KIRKWOOD_GPIO 1
-
-/*
- * NS16550 Configuration
- */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE (-4)
-#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK
-#define CONFIG_SYS_NS16550_COM1 KW_UART0_BASE
-
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-
-/*
- * Environment variables configurations
- */
-#define CONFIG_ENV_SPI_BUS 0
-#define CONFIG_ENV_SPI_CS 0
-#define CONFIG_ENV_SPI_MAX_HZ 20000000 /* 20Mhz */
-#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
-
-/*
- * U-Boot bootcode configuration
- */
-
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for monitor */
-#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* Reserve 4.0 MB for malloc */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Mem map for Linux*/
-
-/* size in bytes reserved for initial data */
-
-#include <asm/arch/config.h>
-/* There is no PHY directly connected so don't ask it for link status */
-#undef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
-
-/*
- * Other required minimal configurations
- */
-#define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */
-
-/*
- * SDIO/MMC Card Configuration
- */
-#ifdef CONFIG_CMD_MMC
-#define CONFIG_MVEBU_MMC
-#define CONFIG_SYS_MMC_BASE KW_SDIO_BASE
-#endif /* CONFIG_CMD_MMC */
-
-/*
- * SATA Driver configuration
- */
-#ifdef CONFIG_MVSATA_IDE
-#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET
-#endif /*CONFIG_MVSATA_IDE*/
-
-#define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default location for tftp and bootm */
-
-#endif /* _CONFIG_DB_88F6281_BP_H */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2014 Freescale Semiconductor
- */
-
-#ifndef __LS2_EMU_H
-#define __LS2_EMU_H
-
-#include "ls2080a_common.h"
-
-#define CONFIG_SYS_CLK_FREQ 100000000
-#define CONFIG_DDR_CLK_FREQ 133333333
-
-#define CONFIG_DDR_SPD
-#define CONFIG_SYS_FSL_DDR_EMU /* Support emulator */
-#define SPD_EEPROM_ADDRESS1 0x51
-#define SPD_EEPROM_ADDRESS2 0x52
-#define SPD_EEPROM_ADDRESS3 0x53
-#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
-#define CONFIG_SYS_SPD_BUS_NUM 1 /* SPD on I2C bus 1 */
-#define CONFIG_DIMM_SLOTS_PER_CTLR 1
-#define CONFIG_CHIP_SELECTS_PER_CTRL 4
-#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
-#define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1
-#endif
-
-#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
-#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
-/*
- * NOR Flash Timing Params
- */
-#define CONFIG_SYS_NOR0_CSPR \
- (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
- CSPR_PORT_SIZE_16 | \
- CSPR_MSEL_NOR | \
- CSPR_V)
-#define CONFIG_SYS_NOR0_CSPR_EARLY \
- (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \
- CSPR_PORT_SIZE_16 | \
- CSPR_MSEL_NOR | \
- CSPR_V)
-#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12)
-#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \
- FTIM0_NOR_TEADC(0x1) | \
- FTIM0_NOR_TEAHC(0x1))
-#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \
- FTIM1_NOR_TRAD_NOR(0x1))
-#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x0) | \
- FTIM2_NOR_TCH(0x0) | \
- FTIM2_NOR_TWP(0x1))
-#define CONFIG_SYS_NOR_FTIM3 0x04000000
-#define CONFIG_SYS_IFC_CCR 0x01000000
-
-#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
-#define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
-
-/* Debug Server firmware */
-#define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
-#define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580C00000ULL
-
-/*
- * This trick allows users to load MC images into DDR directly without
- * copying from NOR flash. It dramatically improves speed.
- */
-#define CONFIG_SYS_LS_MC_FW_IN_DDR
-#define CONFIG_SYS_LS_MC_DPL_IN_DDR
-#define CONFIG_SYS_LS_MC_DPC_IN_DDR
-
-#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 200000
-
-/* Store environment at top of flash */
-
-#endif /* __LS2_EMU_H */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2014 Freescale Semiconductor
- */
-
-#ifndef __LS2_SIMU_H
-#define __LS2_SIMU_H
-
-#include "ls2080a_common.h"
-
-#define CONFIG_SYS_CLK_FREQ 100000000
-#define CONFIG_DDR_CLK_FREQ 133333333
-
-#define CONFIG_DIMM_SLOTS_PER_CTLR 1
-#define CONFIG_CHIP_SELECTS_PER_CTRL 4
-#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
-#define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1
-#endif
-
-/* SMSC 91C111 ethernet configuration */
-#define CONFIG_SMC91111
-#define CONFIG_SMC91111_BASE (0x2210000)
-
-#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
-#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
-
-#ifdef CONFIG_MTD_NOR_FLASH
-#define CONFIG_SYS_FLASH_QUIET_TEST
-#endif
-
-/*
- * NOR Flash Timing Params
- */
-#define CONFIG_SYS_NOR0_CSPR \
- (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
- CSPR_PORT_SIZE_16 | \
- CSPR_MSEL_NOR | \
- CSPR_V)
-#define CONFIG_SYS_NOR0_CSPR_EARLY \
- (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \
- CSPR_PORT_SIZE_16 | \
- CSPR_MSEL_NOR | \
- CSPR_V)
-#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12)
-#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \
- FTIM0_NOR_TEADC(0x1) | \
- FTIM0_NOR_TEAHC(0x1))
-#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \
- FTIM1_NOR_TRAD_NOR(0x1))
-#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x0) | \
- FTIM2_NOR_TCH(0x0) | \
- FTIM2_NOR_TWP(0x1))
-#define CONFIG_SYS_NOR_FTIM3 0x04000000
-#define CONFIG_SYS_IFC_CCR 0x01000000
-
-#ifdef CONFIG_MTD_NOR_FLASH
-#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
-#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
-#endif
-
-#define CONFIG_NAND_FSL_IFC
-#define CONFIG_SYS_NAND_MAX_ECCPOS 256
-#define CONFIG_SYS_NAND_MAX_OOBFREE 2
-
-#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
-#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
- | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
- | CSPR_MSEL_NAND /* MSEL = NAND */ \
- | CSPR_V)
-#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
-
-#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
- | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
- | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
- | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
- | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
- | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
- | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
-
-#define CONFIG_SYS_NAND_ONFI_DETECTION
-
-/* ONFI NAND Flash mode0 Timing Params */
-#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
- FTIM0_NAND_TWP(0x18) | \
- FTIM0_NAND_TWCHT(0x07) | \
- FTIM0_NAND_TWH(0x0a))
-#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
- FTIM1_NAND_TWBE(0x39) | \
- FTIM1_NAND_TRR(0x0e) | \
- FTIM1_NAND_TRP(0x18))
-#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
- FTIM2_NAND_TREH(0x0a) | \
- FTIM2_NAND_TWHRE(0x1e))
-#define CONFIG_SYS_NAND_FTIM3 0x0
-
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_MTD_NAND_VERIFY_WRITE
-
-#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
-
-#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
-#define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
-
-/* MMC */
-#ifdef CONFIG_MMC
-#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
-#endif
-
-/* Debug Server firmware */
-#define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
-#define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580C00000ULL
-
-/* MC firmware */
-#define CONFIG_SYS_LS_MC_DPL_IN_NOR
-#define CONFIG_SYS_LS_MC_DPL_ADDR 0x5806C0000ULL
-
-#define CONFIG_SYS_LS_MC_DPC_IN_NOR
-#define CONFIG_SYS_LS_MC_DPC_ADDR 0x5806F8000ULL
-
-#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 200000
-
-/* Store environment at top of flash */
-
-#endif /* __LS2_SIMU_H */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2010, Stefano Babic <sbabic@denx.de>
- *
- * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
- *
- * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
- *
- * Configuration for the MX35pdk Freescale board.
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <asm/arch/imx-regs.h>
-
- /* High Level Configuration Options */
-#define CONFIG_MX35
-
-#define CONFIG_SYS_FSL_CLK
-
-/* Set TEXT at the beginning of the NOR flash */
-
-#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
-#define CONFIG_REVISION_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-
-/*
- * Size of malloc() pool
- */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024)
-
-/*
- * Hardware drivers
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_MXC
-#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
-#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
-#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
-
-/*
- * PMIC Configs
- */
-#define CONFIG_POWER
-#define CONFIG_POWER_I2C
-#define CONFIG_POWER_FSL
-#define CONFIG_POWER_FSL_MC13892
-#define CONFIG_SYS_FSL_PMIC_I2C_ADDR 0x08
-#define CONFIG_RTC_MC13XXX
-
-/*
- * MFD MC9SDZ60
- */
-#define CONFIG_FSL_MC9SDZ60
-#define CONFIG_SYS_FSL_MC9SDZ60_I2C_ADDR 0x69
-
-/*
- * UART (console)
- */
-#define CONFIG_MXC_UART_BASE UART1_BASE
-
-/*
- * Command definition
- */
-
-#define CONFIG_NET_RETRY_COUNT 100
-
-
-#define CONFIG_LOADADDR 0x80800000 /* loadaddr env var */
-
-/*
- * Ethernet on the debug board (SMC911)
- */
-#define CONFIG_HAS_ETH1
-#define CONFIG_ETHPRIME
-
-/*
- * Ethernet on SOC (FEC)
- */
-#define CONFIG_FEC_MXC
-#define IMX_FEC_BASE FEC_BASE_ADDR
-#define CONFIG_FEC_MXC_PHYADDR 0x1F
-
-#define CONFIG_ARP_TIMEOUT 200UL
-
-/*
- * Miscellaneous configurable options
- */
-
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-
-/*
- * Physical Memory Map
- */
-#define PHYS_SDRAM_1 CSD0_BASE_ADDR
-#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024)
-#define PHYS_SDRAM_2 CSD1_BASE_ADDR
-#define PHYS_SDRAM_2_SIZE (128 * 1024 * 1024)
-
-#define CONFIG_SYS_SDRAM_BASE CSD0_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR + 0x10000)
-#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE / 2)
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
- GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_GBL_DATA_OFFSET)
-
-/*
- * MTD Command for mtdparts
- */
-
-/*
- * FLASH and environment organization
- */
-#define CONFIG_SYS_FLASH_BASE CS0_BASE_ADDR
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
-/* Monitor at beginning of flash */
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
-
-/* Address and size of Redundant Environment Sector */
-
-/*
- * CFI FLASH driver setup
- */
-
-/* A non-standard buffered write algorithm */
-#define CONFIG_FLASH_SPANSION_S29WS_N
-
-/*
- * NAND FLASH driver setup
- */
-#define CONFIG_MXC_NAND_REGS_BASE (NFC_BASE_ADDR)
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_NAND_BASE (NFC_BASE_ADDR)
-#define CONFIG_MXC_NAND_HWECC
-#define CONFIG_SYS_NAND_LARGEPAGE
-
-/* EHCI driver */
-#define CONFIG_EHCI_IS_TDI
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#define CONFIG_USB_EHCI_MXC
-#define CONFIG_MXC_USB_PORT 0
-#define CONFIG_MXC_USB_FLAGS (MXC_EHCI_INTERFACE_DIFF_UNI | \
- MXC_EHCI_POWER_PINS_ENABLED | \
- MXC_EHCI_OC_PIN_ACTIVE_LOW)
-#define CONFIG_MXC_USB_PORTSC (MXC_EHCI_UTMI_16BIT | MXC_EHCI_MODE_UTMI)
-
-/* mmc driver */
-#define CONFIG_SYS_FSL_ESDHC_ADDR 0
-#define CONFIG_SYS_FSL_ESDHC_NUM 1
-
-/*
- * Default environment and default scripts
- * to update uboot and load kernel
- */
-
-#define CONFIG_HOSTNAME "mx35pdk"
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth1\0" \
- "ethprime=smc911x\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=${serverip}:${rootpath}\0" \
- "ramargs=setenv bootargs root=/dev/ram rw\0" \
- "addip_sta=setenv bootargs ${bootargs} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
- ":${hostname}:${netdev}:off panic=1\0" \
- "addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \
- "addip=if test -n ${ipdyn};then run addip_dyn;" \
- "else run addip_sta;fi\0" \
- "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
- "addtty=setenv bootargs ${bootargs}" \
- " console=ttymxc0,${baudrate}\0" \
- "addmisc=setenv bootargs ${bootargs} ${misc}\0" \
- "loadaddr=80800000\0" \
- "kernel_addr_r=80800000\0" \
- "hostname=" CONFIG_HOSTNAME "\0" \
- "bootfile=" CONFIG_HOSTNAME "/uImage\0" \
- "ramdisk_file=" CONFIG_HOSTNAME "/uRamdisk\0" \
- "flash_self=run ramargs addip addtty addmtd addmisc;" \
- "bootm ${kernel_addr} ${ramdisk_addr}\0" \
- "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \
- "bootm ${kernel_addr}\0" \
- "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
- "run nfsargs addip addtty addmtd addmisc;" \
- "bootm ${kernel_addr_r}\0" \
- "net_self_load=tftp ${kernel_addr_r} ${bootfile};" \
- "tftp ${ramdisk_addr_r} ${ramdisk_file};\0" \
- "u-boot=" CONFIG_HOSTNAME "/u-boot.bin\0" \
- "load=tftp ${loadaddr} ${u-boot}\0" \
- "uboot_addr=" __stringify(CONFIG_SYS_MONITOR_BASE) "\0" \
- "update=protect off ${uboot_addr} +80000;" \
- "erase ${uboot_addr} +80000;" \
- "cp.b ${loadaddr} ${uboot_addr} ${filesize}\0" \
- "upd=if run load;then echo Updating u-boot;if run update;" \
- "then echo U-Boot updated;" \
- "else echo Error updating u-boot !;" \
- "echo Board without bootloader !!;" \
- "fi;" \
- "else echo U-Boot not downloaded..exiting;fi\0" \
- "bootcmd=run net_nfs\0"
-
-#endif /* __CONFIG_H */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Configuation settings for the Renesas R7780MP board
- *
- * Copyright (C) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
- * Copyright (C) 2008 Yusuke Goda <goda.yusuke@renesas.com>
- */
-
-#ifndef __R7780RP_H
-#define __R7780RP_H
-
-#define CONFIG_CPU_SH7780 1
-#define CONFIG_R7780MP 1
-#define CONFIG_SYS_R7780MP_OLD_FLASH 1
-#define __LITTLE_ENDIAN__ 1
-
-#define CONFIG_DISPLAY_BOARDINFO
-
-#define CONFIG_CONS_SCIF0 1
-
-#define CONFIG_SYS_SDRAM_BASE (0x08000000)
-#define CONFIG_SYS_SDRAM_SIZE (128 * 1024 * 1024)
-
-#define CONFIG_SYS_PBSIZE 256
-
-/* Flash board support */
-#define CONFIG_SYS_FLASH_BASE (0xA0000000)
-#ifdef CONFIG_SYS_R7780MP_OLD_FLASH
-/* NOR Flash (S29PL127J60TFI130) */
-# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT
-# define CONFIG_SYS_MAX_FLASH_BANKS (2)
-# define CONFIG_SYS_MAX_FLASH_SECT 270
-# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\
- CONFIG_SYS_FLASH_BASE + 0x100000,\
- CONFIG_SYS_FLASH_BASE + 0x400000,\
- CONFIG_SYS_FLASH_BASE + 0x700000, }
-#else /* CONFIG_SYS_R7780MP_OLD_FLASH */
-/* NOR Flash (Spantion S29GL256P) */
-# define CONFIG_SYS_MAX_FLASH_BANKS (1)
-# define CONFIG_SYS_MAX_FLASH_SECT 256
-# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
-#endif /* CONFIG_SYS_R7780MP_OLD_FLASH */
-
-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024)
-/* Address of u-boot image in Flash */
-#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE)
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
-/* Size of DRAM reserved for malloc() use */
-#define CONFIG_SYS_MALLOC_LEN (1204 * 1024)
-
-#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
-#define CONFIG_SYS_RX_ETH_BUFFER (8)
-
-#undef CONFIG_SYS_FLASH_CFI_BROKEN_TABLE
-#undef CONFIG_SYS_FLASH_QUIET_TEST
-/* print 'E' for empty sector on flinfo */
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500
-
-/* Board Clock */
-#define CONFIG_SYS_CLK_FREQ 33333333
-#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
-
-/* PCI Controller */
-#if defined(CONFIG_CMD_PCI)
-#define CONFIG_SH4_PCI
-#define CONFIG_SH7780_PCI
-#define CONFIG_SH7780_PCI_LSR 0x07f00001
-#define CONFIG_SH7780_PCI_LAR CONFIG_SYS_SDRAM_SIZE
-#define CONFIG_SH7780_PCI_BAR CONFIG_SYS_SDRAM_SIZE
-#define CONFIG_PCI_SCAN_SHOW 1
-#define __mem_pci
-
-#define CONFIG_PCI_MEM_BUS 0xFD000000 /* Memory space base addr */
-#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
-#define CONFIG_PCI_MEM_SIZE 0x01000000 /* Size of Memory window */
-
-#define CONFIG_PCI_IO_BUS 0xFE200000 /* IO space base address */
-#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
-#define CONFIG_PCI_IO_SIZE 0x00200000 /* Size of IO window */
-#define CONFIG_PCI_SYS_PHYS CONFIG_SYS_SDRAM_BASE
-#define CONFIG_PCI_SYS_BUS CONFIG_SYS_SDRAM_BASE
-#define CONFIG_PCI_SYS_SIZE CONFIG_SYS_SDRAM_SIZE
-#endif /* CONFIG_CMD_PCI */
-
-#if defined(CONFIG_CMD_NET)
-/* AX88796L Support(NE2000 base chip) */
-#define CONFIG_DRIVER_AX88796L
-#define CONFIG_DRIVER_NE2000_BASE 0xA4100000
-#endif
-
-/* Compact flash Support */
-#if defined(CONFIG_IDE)
-#define CONFIG_IDE_RESET 1
-#define CONFIG_SYS_PIO_MODE 1
-#define CONFIG_SYS_IDE_MAXBUS 1 /* IDE bus */
-#define CONFIG_SYS_IDE_MAXDEVICE 1
-#define CONFIG_SYS_ATA_BASE_ADDR 0xb4000000
-#define CONFIG_SYS_ATA_STRIDE 2 /* 1bit shift */
-#define CONFIG_SYS_ATA_DATA_OFFSET 0x1000 /* data reg offset */
-#define CONFIG_SYS_ATA_REG_OFFSET 0x1000 /* reg offset */
-#define CONFIG_SYS_ATA_ALT_OFFSET 0x800 /* alternate register offset */
-#define CONFIG_IDE_SWAP_IO
-#endif /* CONFIG_IDE */
-
-#endif /* __R7780RP_H */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Configuation settings for the sh7752evb board
- *
- * Copyright (C) 2012 Renesas Solutions Corp.
- */
-
-#ifndef __SH7752EVB_H
-#define __SH7752EVB_H
-
-#define CONFIG_CPU_SH7752 1
-
-#define CONFIG_DISPLAY_BOARDINFO
-
-/* MEMORY */
-#define SH7752EVB_SDRAM_BASE (0x40000000)
-#define SH7752EVB_SDRAM_SIZE (512 * 1024 * 1024)
-
-#define CONFIG_SYS_PBSIZE 256
-#define CONFIG_SYS_BAUDRATE_TABLE { 115200 }
-
-/* SCIF */
-#define CONFIG_CONS_SCIF2 1
-
-#undef CONFIG_SYS_LOADS_BAUD_CHANGE
-
-#define CONFIG_SYS_SDRAM_BASE (SH7752EVB_SDRAM_BASE)
-#define CONFIG_SYS_SDRAM_SIZE (SH7752EVB_SDRAM_SIZE)
-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + \
- 128 * 1024 * 1024)
-
-#define CONFIG_SYS_MONITOR_BASE 0x00000000
-#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
-#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
-#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
-
-/* Ether */
-#define CONFIG_SH_ETHER_USE_PORT 0
-#define CONFIG_SH_ETHER_PHY_ADDR 18
-#define CONFIG_SH_ETHER_CACHE_WRITEBACK 1
-#define CONFIG_SH_ETHER_USE_GETHER 1
-#define CONFIG_BITBANGMII_MULTI
-#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RGMII
-
-#define SH7752EVB_ETHERNET_MAC_BASE_SPI 0x00090000
-#define SH7752EVB_SPI_SECTOR_SIZE (64 * 1024)
-#define SH7752EVB_ETHERNET_MAC_BASE SH7752EVB_ETHERNET_MAC_BASE_SPI
-#define SH7752EVB_ETHERNET_MAC_SIZE 17
-#define SH7752EVB_ETHERNET_NUM_CH 2
-
-/* SPI */
-#define CONFIG_SH_SPI_BASE 0xfe002000
-
-/* MMCIF */
-#define CONFIG_SH_MMCIF_ADDR 0xffcb0000
-#define CONFIG_SH_MMCIF_CLK 48000000
-
-/* ENV setting */
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netboot=bootp; bootm\0"
-
-/* Board Clock */
-#define CONFIG_SYS_CLK_FREQ 48000000
-#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
-#endif /* __SH7752EVB_H */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Configuation settings for the sh7753evb board
- *
- * Copyright (C) 2012 Renesas Solutions Corp.
- */
-
-#ifndef __SH7753EVB_H
-#define __SH7753EVB_H
-
-#define CONFIG_CPU_SH7753 1
-
-#define CONFIG_DISPLAY_BOARDINFO
-
-/* MEMORY */
-#define SH7753EVB_SDRAM_BASE (0x40000000)
-#define SH7753EVB_SDRAM_SIZE (512 * 1024 * 1024)
-
-#define CONFIG_SYS_PBSIZE 256
-#define CONFIG_SYS_BAUDRATE_TABLE { 115200 }
-
-/* SCIF */
-#define CONFIG_CONS_SCIF2 1
-
-#undef CONFIG_SYS_LOADS_BAUD_CHANGE
-
-#define CONFIG_SYS_SDRAM_BASE (SH7753EVB_SDRAM_BASE)
-#define CONFIG_SYS_SDRAM_SIZE (SH7753EVB_SDRAM_SIZE)
-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + \
- 128 * 1024 * 1024)
-
-#define CONFIG_SYS_MONITOR_BASE 0x00000000
-#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
-#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
-#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
-
-/* Ether */
-#define CONFIG_SH_ETHER_USE_PORT 0
-#define CONFIG_SH_ETHER_PHY_ADDR 18
-#define CONFIG_SH_ETHER_CACHE_WRITEBACK 1
-#define CONFIG_SH_ETHER_USE_GETHER 1
-#define CONFIG_BITBANGMII_MULTI
-#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RGMII
-
-#define SH7753EVB_ETHERNET_MAC_BASE_SPI 0x00090000
-#define SH7753EVB_SPI_SECTOR_SIZE (64 * 1024)
-#define SH7753EVB_ETHERNET_MAC_BASE SH7753EVB_ETHERNET_MAC_BASE_SPI
-#define SH7753EVB_ETHERNET_MAC_SIZE 17
-#define SH7753EVB_ETHERNET_NUM_CH 2
-
-/* SPI */
-#define CONFIG_SH_SPI_BASE 0xfe002000
-
-/* MMCIF */
-#define CONFIG_SH_MMCIF_ADDR 0xffcb0000
-#define CONFIG_SH_MMCIF_CLK 48000000
-
-/* ENV setting */
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netboot=bootp; bootm\0"
-
-/* Board Clock */
-#define CONFIG_SYS_CLK_FREQ 48000000
-#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
-#endif /* __SH7753EVB_H */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Configuation settings for the sh7757lcr board
- *
- * Copyright (C) 2011 Renesas Solutions Corp.
- */
-
-#ifndef __SH7757LCR_H
-#define __SH7757LCR_H
-
-#define CONFIG_CPU_SH7757 1
-#define CONFIG_SH7757LCR_DDR_ECC 1
-
-#define CONFIG_DISPLAY_BOARDINFO
-
-/* MEMORY */
-#define SH7757LCR_SDRAM_BASE (0x80000000)
-#define SH7757LCR_SDRAM_SIZE (240 * 1024 * 1024)
-#define SH7757LCR_SDRAM_ECC_SETTING 0x0f000000 /* 240MByte */
-#define SH7757LCR_SDRAM_DVC_SIZE (16 * 1024 * 1024)
-
-#define CONFIG_SYS_PBSIZE 256
-#define CONFIG_SYS_BAUDRATE_TABLE { 115200 }
-
-/* SCIF */
-#define CONFIG_CONS_SCIF2 1
-
-#undef CONFIG_SYS_LOADS_BAUD_CHANGE
-
-#define CONFIG_SYS_SDRAM_BASE (SH7757LCR_SDRAM_BASE)
-#define CONFIG_SYS_SDRAM_SIZE (SH7757LCR_SDRAM_SIZE)
-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + \
- (128 + 16) * 1024 * 1024)
-
-#define CONFIG_SYS_MONITOR_BASE 0x00000000
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
-#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
-#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
-
-/* Ether */
-#define CONFIG_SH_ETHER_USE_PORT 0
-#define CONFIG_SH_ETHER_PHY_ADDR 1
-#define CONFIG_SH_ETHER_CACHE_WRITEBACK 1
-#define CONFIG_BITBANGMII_MULTI
-#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII
-
-#define SH7757LCR_ETHERNET_MAC_BASE_SPI 0x000b0000
-#define SH7757LCR_SPI_SECTOR_SIZE (64 * 1024)
-#define SH7757LCR_ETHERNET_MAC_BASE SH7757LCR_ETHERNET_MAC_BASE_SPI
-#define SH7757LCR_ETHERNET_MAC_SIZE 17
-#define SH7757LCR_ETHERNET_NUM_CH 2
-
-/* Gigabit Ether */
-#define SH7757LCR_GIGA_ETHERNET_NUM_CH 2
-
-/* SPI */
-#define CONFIG_SH_SPI_BASE 0xfe002000
-
-/* MMCIF */
-#define CONFIG_SH_MMCIF_ADDR 0xffcb0000
-#define CONFIG_SH_MMCIF_CLK 48000000
-
-/* SH7757 board */
-#define SH7757LCR_SDRAM_PHYS_TOP 0x40000000
-#define SH7757LCR_GRA_OFFSET 0x1f000000
-#define SH7757LCR_PCIEBRG_ADDR_B0 0x000a0000
-#define SH7757LCR_PCIEBRG_SIZE_B0 (64 * 1024)
-#define SH7757LCR_PCIEBRG_ADDR 0x00090000
-#define SH7757LCR_PCIEBRG_SIZE (96 * 1024)
-
-/* ENV setting */
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netboot=bootp; bootm\0"
-
-/* Board Clock */
-#define CONFIG_SYS_CLK_FREQ 48000000
-#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
-#endif /* __SH7757LCR_H */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Configuation settings for the Renesas SH7763RDP board
- *
- * Copyright (C) 2008 Renesas Solutions Corp.
- * Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
- */
-
-#ifndef __SH7763RDP_H
-#define __SH7763RDP_H
-
-#define CONFIG_CPU_SH7763 1
-#define __LITTLE_ENDIAN 1
-
-#define CONFIG_DISPLAY_BOARDINFO
-
-/* SCIF */
-#define CONFIG_CONS_SCIF2 1
-
-#define CONFIG_SYS_PBSIZE 256 /* Buffer size for Console output */
-#define CONFIG_SYS_BAUDRATE_TABLE { 115200 } /* List of legal baudrate
- settings for this board */
-
-/* SDRAM */
-#define CONFIG_SYS_SDRAM_BASE (0x8C000000)
-#define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024)
-
-/* Flash(NOR) */
-#define CONFIG_SYS_FLASH_BASE (0xA0000000)
-#define CONFIG_SYS_FLASH_CFI_WIDTH (FLASH_CFI_16BIT)
-#define CONFIG_SYS_MAX_FLASH_BANKS (1)
-#define CONFIG_SYS_MAX_FLASH_SECT (520)
-
-/* U-Boot setting */
-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024)
-#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE)
-#define CONFIG_SYS_MONITOR_LEN (128 * 1024)
-/* Size of DRAM reserved for malloc() use */
-#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
-#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
-
-#undef CONFIG_SYS_FLASH_QUIET_TEST
-#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
-/* Timeout for Flash erase operations (in ms) */
-#define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000)
-/* Timeout for Flash write operations (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000)
-/* Timeout for Flash set sector lock bit operations (in ms) */
-#define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000)
-/* Timeout for Flash clear lock bit operations (in ms) */
-#define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000)
-/* Use hardware flash sectors protection instead of U-Boot software protection */
-#undef CONFIG_SYS_DIRECT_FLASH_TFTP
-/* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */
-
-/* Clock */
-#define CONFIG_SYS_CLK_FREQ 66666666
-#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
-
-/* Ether */
-#define CONFIG_SH_ETHER_USE_PORT (1)
-#define CONFIG_SH_ETHER_PHY_ADDR (0x01)
-#define CONFIG_BITBANGMII_MULTI
-#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII
-
-#endif /* __SH7763RDP_H */
projects / platform / kernel / u-boot.git / commitdiff