tu_cs_emit_draw_state(cs, TU_DRAW_STATE_DYNAMIC + i, pipeline->dynamic_state[i]);
}
+ cmd->state.pipeline_draw_states = pipeline->set_state_mask;
+ u_foreach_bit(i, pipeline->set_state_mask)
+ cmd->state.dynamic_state[i] = pipeline->dynamic_state[i];
+
if (pipeline->active_stages & VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT) {
cmd->state.rp.has_tess = true;
}
for (uint32_t i = 0; i < ARRAY_SIZE(cmd->state.dynamic_state); i++) {
tu_cs_emit_draw_state(cs, TU_DRAW_STATE_DYNAMIC + i,
- ((pipeline->set_state_mask & BIT(i)) ?
- pipeline->dynamic_state[i] :
- cmd->state.dynamic_state[i]));
+ cmd->state.dynamic_state[i]);
}
} else {
/* emit draw states that were just updated */
bool pipeline_feedback_loop_ds;
bool pipeline_blend_lrz;
+ uint32_t pipeline_draw_states;
/* VK_QUERY_PIPELINE_STATISTIC_CLIPPING_INVOCATIONS_BIT and
* VK_QUERY_TYPE_PRIMITIVES_GENERATED_EXT are allowed to run simultaniously,
ARRAY_SIZE(tu_##name##_state))
#define DRAW_STATE_COND(name, id, extra_cond, ...) \
if ((EMIT_STATE(name) || extra_cond) && \
- !(cmd->state.pipeline->base.set_state_mask & (1u << id))) { \
+ !(cmd->state.pipeline_draw_states & (1u << id))) { \
unsigned size = tu6_##name##_size<CHIP>(cmd->device, __VA_ARGS__); \
if (size > 0) { \
tu_cs_begin_sub_stream(&cmd->sub_cs, size, &cs); \
}
#define DRAW_STATE_FDM(name, id, ...) \
if ((EMIT_STATE(name) || (cmd->state.dirty & TU_CMD_DIRTY_FDM)) && \
- !(cmd->state.pipeline->base.set_state_mask & (1u << id))) { \
+ !(cmd->state.pipeline_draw_states & (1u << id))) { \
if (cmd->state.shaders[MESA_SHADER_FRAGMENT]->fs.has_fdm) { \
tu_cs_set_writeable(&cmd->sub_cs, true); \
tu6_emit_##name##_fdm(&cs, cmd, __VA_ARGS__); \