radv: Shift left the tile swizzle more on GFX11.

ac/surface puts the raw pip_bank_xor there, which needs the extra
shift for the actual tile_swizzle.

(I think long term we should refactor this in ac/surface but for
 now lets fix like radeonsi to avoid race conditions.)

CC: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20979>
(cherry picked from commit b0a9772cc6154e29ba6e3d21a91096dd891ef302)

diff --git a/.pick_status.json b/.pick_status.json
index 9892160..3fbab24 100644 (file)
--- a/.pick_status.json
+++ b/.pick_status.json
@@ -4288,7 +4288,7 @@
         "description": "radv: Shift left the tile swizzle more on GFX11.",
         "nominated": true,
         "nomination_type": 0,
-        "resolution": 0,
+        "resolution": 1,
         "main_sha": null,
         "because_sha": null
     },

diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index eec7833..658b795 100644 (file)
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -6563,6 +6563,8 @@ radv_initialise_color_surface(struct radv_device *device, struct radv_color_buff
       tile_swizzle = iview->nbc_view.tile_swizzle;
    }
 
+   tile_swizzle = radv_adjust_tile_swizzle(device->physical_device, tile_swizzle);
+
    cb->cb_color_base = va >> 8;
 
    if (device->physical_device->rad_info.gfx_level >= GFX9) {

diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index 6959a90..27f8304 100644 (file)
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -789,6 +789,8 @@ si_set_mutable_tex_desc_fields(struct radv_device *device, struct radv_image *im
    } else
       va += (uint64_t)base_level_info->offset_256B * 256;
 
+   swizzle = radv_adjust_tile_swizzle(device->physical_device, swizzle);
+
    state[0] = va >> 8;
    if (gfx_level >= GFX9 || base_level_info->mode == RADEON_SURF_MODE_2D)
       state[0] |= swizzle;
@@ -803,7 +805,7 @@ si_set_mutable_tex_desc_fields(struct radv_device *device, struct radv_image *im
          if (gfx_level <= GFX8)
             meta_va += plane->surface.u.legacy.color.dcc_level[base_level].dcc_offset;
 
-         unsigned dcc_tile_swizzle = plane->surface.tile_swizzle << 8;
+         unsigned dcc_tile_swizzle = swizzle << 8;
          dcc_tile_swizzle &= (1 << plane->surface.meta_alignment_log2) - 1;
          meta_va |= dcc_tile_swizzle;
       } else if (!disable_compression && radv_image_is_tc_compat_htile(image)) {

diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index f3728ab..8f6371c 100644 (file)
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -3196,6 +3196,12 @@ radv_has_shader_buffer_float_minmax(const struct radv_physical_device *pdevice,
           (pdevice->rad_info.gfx_level == GFX11 && bitsize == 32);
 }
 
+static inline unsigned
+radv_adjust_tile_swizzle(const struct radv_physical_device *dev, unsigned pipe_bank_xor)
+{
+   return pipe_bank_xor << (dev->rad_info.gfx_level >= GFX11 ? 2 : 0);
+}
+
 /* radv_perfcounter.c */
 void radv_perfcounter_emit_shaders(struct radeon_cmdbuf *cs, unsigned shaders);
 void radv_perfcounter_emit_spm_reset(struct radeon_cmdbuf *cs);

diff --git a/src/amd/vulkan/radv_sdma_copy_image.c b/src/amd/vulkan/radv_sdma_copy_image.c
index 93044c6..7c8c8ae 100644 (file)
--- a/src/amd/vulkan/radv_sdma_copy_image.c
+++ b/src/amd/vulkan/radv_sdma_copy_image.c
@@ -139,8 +139,11 @@ radv_sdma_v4_v5_copy_image_to_buffer(struct radv_cmd_buffer *cmd_buffer, struct
                                   (tmz ? 4 : 0)) |
                      dcc << 19 | (is_v5 ? 0 : 0 /* tiled->buffer.b.b.last_level */) << 20 |
                      1u << 31);
-      radeon_emit(cmd_buffer->cs,
-                  (uint32_t)tiled_address | (image->planes[0].surface.tile_swizzle << 8));
+      radeon_emit(
+         cmd_buffer->cs,
+         (uint32_t)tiled_address |
+            (radv_adjust_tile_swizzle(device->physical_device, image->planes[0].surface.tile_swizzle)
+             << 8));
       radeon_emit(cmd_buffer->cs, (uint32_t)(tiled_address >> 32));
       radeon_emit(cmd_buffer->cs, 0);
       radeon_emit(cmd_buffer->cs, ((tiled_width - 1) << 16));