rtw89: pci: handle hardware watchdog timeout interrupt status
authorPing-Ke Shih <pkshih@realtek.com>
Fri, 20 May 2022 07:17:28 +0000 (15:17 +0800)
committerKalle Valo <kvalo@kernel.org>
Mon, 30 May 2022 09:35:58 +0000 (12:35 +0300)
This watchdog timeout status bit indicates hardware gets wrong, so run SER
L2 flow that calls mac80211 to restart hardware.

Signed-off-by: Ping-Ke Shih <pkshih@realtek.com>
Signed-off-by: Kalle Valo <kvalo@kernel.org>
Link: https://lore.kernel.org/r/20220520071731.38563-4-pkshih@realtek.com
drivers/net/wireless/realtek/rtw89/mac.h
drivers/net/wireless/realtek/rtw89/pci.c
drivers/net/wireless/realtek/rtw89/pci.h

index 9f511c8d8a376b7975474e6d98e483ba282bac7e..f66619354734d079144d2fe53cb80056bf1b18e2 100644 (file)
@@ -666,6 +666,7 @@ enum mac_ax_err_info {
        MAC_AX_ERR_L2_ERR_APB_BBRF_TO_RX4281 = 0x2360,
        MAC_AX_ERR_L2_ERR_APB_BBRF_TO_OTHERS = 0x2370,
        MAC_AX_ERR_L2_RESET_DONE = 0x2400,
+       MAC_AX_ERR_L2_ERR_WDT_TIMEOUT_INT = 0x2599,
        MAC_AX_ERR_CPU_EXCEPTION = 0x3000,
        MAC_AX_ERR_ASSERTION = 0x4000,
        MAC_AX_GET_ERR_MAX,
index 0ef7821b2e0fcc2437dbb55cde27dc66a44df2ef..25872dfb4da1ccee6e60d5e88dd3e62f5ccb9d5a 100644 (file)
@@ -738,6 +738,9 @@ static irqreturn_t rtw89_pci_interrupt_threadfn(int irq, void *dev)
        if (unlikely(isrs.halt_c2h_isrs & B_AX_HALT_C2H_INT_EN))
                rtw89_ser_notify(rtwdev, rtw89_mac_get_err_status(rtwdev));
 
+       if (unlikely(isrs.halt_c2h_isrs & B_AX_WDT_TIMEOUT_INT_EN))
+               rtw89_ser_notify(rtwdev, MAC_AX_ERR_L2_ERR_WDT_TIMEOUT_INT);
+
        if (unlikely(rtwpci->under_recovery))
                goto enable_intr;
 
@@ -3126,7 +3129,7 @@ static void rtw89_pci_recovery_intr_mask_v1(struct rtw89_dev *rtwdev)
        struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
 
        rtwpci->ind_intrs = B_AX_HS0ISR_IND_INT_EN;
-       rtwpci->halt_c2h_intrs = B_AX_HALT_C2H_INT_EN;
+       rtwpci->halt_c2h_intrs = B_AX_HALT_C2H_INT_EN | B_AX_WDT_TIMEOUT_INT_EN;
        rtwpci->intrs[0] = 0;
        rtwpci->intrs[1] = 0;
 }
@@ -3138,7 +3141,7 @@ static void rtw89_pci_default_intr_mask_v1(struct rtw89_dev *rtwdev)
        rtwpci->ind_intrs = B_AX_HCI_AXIDMA_INT_EN |
                            B_AX_HS1ISR_IND_INT_EN |
                            B_AX_HS0ISR_IND_INT_EN;
-       rtwpci->halt_c2h_intrs = B_AX_HALT_C2H_INT_EN;
+       rtwpci->halt_c2h_intrs = B_AX_HALT_C2H_INT_EN | B_AX_WDT_TIMEOUT_INT_EN;
        rtwpci->intrs[0] = B_AX_TXDMA_STUCK_INT_EN |
                           B_AX_RXDMA_INT_EN |
                           B_AX_RXP1DMA_INT_EN |
@@ -3155,7 +3158,7 @@ static void rtw89_pci_low_power_intr_mask_v1(struct rtw89_dev *rtwdev)
 
        rtwpci->ind_intrs = B_AX_HS1ISR_IND_INT_EN |
                            B_AX_HS0ISR_IND_INT_EN;
-       rtwpci->halt_c2h_intrs = B_AX_HALT_C2H_INT_EN;
+       rtwpci->halt_c2h_intrs = B_AX_HALT_C2H_INT_EN | B_AX_WDT_TIMEOUT_INT_EN;
        rtwpci->intrs[0] = 0;
        rtwpci->intrs[1] = B_AX_GPIO18_INT_EN;
 }
index bb585ed1919084dfb5ca23cb527d0b20fff1b597..a118647213e35322fad5e97f26fa2d1fb2f497e2 100644 (file)
@@ -94,6 +94,7 @@
 
 /* Interrupts */
 #define R_AX_HIMR0 0x01A0
+#define B_AX_WDT_TIMEOUT_INT_EN BIT(22)
 #define B_AX_HALT_C2H_INT_EN BIT(21)
 #define R_AX_HISR0 0x01A4