Fix for string-opt-7 failure on rs6000 -maix64.

From-SVN: r49593

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 12898da..43107d3 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,11 @@
+2002-02-07  Tom Rix  <trix@redhat.com>
+
+       * config/rs6000/rs6000.c (reg_or_aligned_short_operand): New. For 
+       immediates in ldu and stdu DS opcode field.
+       * config/rs6000/rs6000.md (movdi_update, movdi_update1): Use.
+       * config/rs6000/rs6000-protos.h: Add reg_or_aligned_short_operand.
+       * config/rs6000/rs6000.h (PREDICATE_CODES): Same.
+
 2002-02-07  Jeff Sturm  <jsturm@one-point.com>
 
        * config/sparc/sparc.c (compute_frame_size): Don't correct frame

diff --git a/gcc/config/rs6000/rs6000-protos.h b/gcc/config/rs6000/rs6000-protos.h
index c40689e..a588360 100644 (file)
--- a/gcc/config/rs6000/rs6000-protos.h
+++ b/gcc/config/rs6000/rs6000-protos.h
@@ -40,6 +40,7 @@ extern int cc_reg_operand PARAMS ((rtx, enum machine_mode));
 extern int cc_reg_not_cr0_operand PARAMS ((rtx, enum machine_mode));
 extern int reg_or_short_operand PARAMS ((rtx, enum machine_mode));
 extern int reg_or_neg_short_operand PARAMS ((rtx, enum machine_mode));
+extern int reg_or_aligned_short_operand PARAMS ((rtx, enum machine_mode));
 extern int reg_or_u_short_operand PARAMS ((rtx, enum machine_mode));
 extern int reg_or_cint_operand PARAMS ((rtx, enum machine_mode));
 extern int reg_or_arith_cint_operand PARAMS ((rtx, enum machine_mode));

diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 0143981..23a05f4 100644 (file)
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -850,6 +850,24 @@ reg_or_neg_short_operand (op, mode)
   return gpc_reg_operand (op, mode);
 }
 
+/* Returns 1 if OP is either a constant integer valid for a DS-field or
+   a non-special register.  If a register, it must be in the proper
+   mode unless MODE is VOIDmode.  */
+
+int
+reg_or_aligned_short_operand (op, mode)
+      rtx op;
+      enum machine_mode mode;
+{
+  if (gpc_reg_operand (op, mode))
+    return 1;
+  else if (short_cint_operand (op, mode) && !(INTVAL (op) & 3))
+    return 1;
+
+  return 0;
+}
+
+
 /* Return 1 if the operand is either a register or an integer whose
    high-order 16 bits are zero.  */
 

diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index b0d1a12..22f2042 100644 (file)
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -2715,6 +2715,7 @@ extern char rs6000_reg_names[][8];        /* register names (0 vs. %r0).  */
   {"cc_reg_not_cr0_operand", {SUBREG, REG}},                              \
   {"reg_or_short_operand", {SUBREG, REG, CONST_INT}},                     \
   {"reg_or_neg_short_operand", {SUBREG, REG, CONST_INT}},                 \
+  {"reg_or_aligned_short_operand", {SUBREG, REG, CONST_INT}},             \
   {"reg_or_u_short_operand", {SUBREG, REG, CONST_INT}},                           \
   {"reg_or_cint_operand", {SUBREG, REG, CONST_INT}},                      \
   {"reg_or_arith_cint_operand", {SUBREG, REG, CONST_INT}},                \

diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 1d15331..a1e0303 100644 (file)
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -9173,7 +9173,7 @@
 (define_insn "*movdi_update1"
   [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r")
        (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
-                        (match_operand:DI 2 "reg_or_short_operand" "r,I"))))
+                        (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I"))))
    (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
        (plus:DI (match_dup 1) (match_dup 2)))]
   "TARGET_POWERPC64 && TARGET_UPDATE"
@@ -9195,7 +9195,7 @@
 
 (define_insn "movdi_update"
   [(set (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
-                        (match_operand:DI 2 "reg_or_short_operand" "r,I")))
+                        (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I")))
        (match_operand:DI 3 "gpc_reg_operand" "r,r"))
    (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
        (plus:DI (match_dup 1) (match_dup 2)))]
@@ -15323,7 +15323,7 @@
        (eq:SI (reg:CC 74)
               (const_int 0)))]
   "TARGET_ALTIVEC"
-  "")
+  "")  
 
 (define_expand "cr6_test_for_zero_reverse"
   [(set (match_operand:SI 0 "register_operand" "=r")