ARM: dts: aspeed: Add LPC clock phandles

The LPC device uses LCLK.

Tested-by: Lei YU <mine260309@gmail.com>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>

diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi
index 8b18176dca59162d4833450e49e68e057fbbf933..48c28a71ae7e366eda11254ce92731bd3e630d11 100644 (file)
--- a/arch/arm/boot/dts/aspeed-g4.dtsi
+++ b/arch/arm/boot/dts/aspeed-g4.dtsi
@@ -233,6 +233,7 @@
                                        lpc_ctrl: lpc-ctrl@0 {
                                                compatible = "aspeed,ast2400-lpc-ctrl";
                                                reg = <0x0 0x80>;
+                                               clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
                                                status = "disabled";
                                        };
 

diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
index e0b6803f6845a972e76cb0e8b66d1b2d6e344109..8eac57c338804707e14d5dee08ce297ebde43241 100644 (file)
--- a/arch/arm/boot/dts/aspeed-g5.dtsi
+++ b/arch/arm/boot/dts/aspeed-g5.dtsi
@@ -283,6 +283,7 @@
                                        lpc_ctrl: lpc-ctrl@0 {
                                                compatible = "aspeed,ast2500-lpc-ctrl";
                                                reg = <0x0 0x80>;
+                                               clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
                                                status = "disabled";
                                        };