Pre-RA scheduling can move instructions around in nontrivial ways, yet it must
maintain the IR's ordering invariants (for preloads, phis, etc.) Running
validation before and after makes scheduler bugs more obvious.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>
bi_opt_dead_code_eliminate(ctx);
}
- if (likely(!(bifrost_debug & BIFROST_DBG_NOPSCHED)))
- bi_pressure_schedule(ctx);
-
bi_validate(ctx, "Late lowering");
+ if (likely(!(bifrost_debug & BIFROST_DBG_NOPSCHED))) {
+ bi_pressure_schedule(ctx);
+ bi_validate(ctx, "Pre-RA scheduling");
+ }
+
bi_register_allocate(ctx);
if (likely(optimize))