arm: ls102xa: enable all the snoop signal for masters.
authorYao Yuan <yao.yuan@freescale.com>
Sat, 5 Dec 2015 06:59:11 +0000 (14:59 +0800)
committerYork Sun <yorksun@freescale.com>
Mon, 14 Dec 2015 02:27:29 +0000 (18:27 -0800)
Enable the IP feature's snoop signal to support
hardware snoop for cache coherence.

SNPCNFGCR contains the bits to drive snoop signal
for various masters.

Signed-off-by: Yuan Yao <yao.yuan@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
arch/arm/cpu/armv7/ls102xa/soc.c
arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h

index 0fdd6d4..6036473 100644 (file)
@@ -62,5 +62,13 @@ int arch_soc_init(void)
                out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
        }
 
+       /* Enable all the snoop signal for various masters */
+       out_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SEC_RD_WR |
+                               SCFG_SNPCNFGCR_DCU_RD_WR |
+                               SCFG_SNPCNFGCR_SATA_RD_WR |
+                               SCFG_SNPCNFGCR_USB3_RD_WR |
+                               SCFG_SNPCNFGCR_DBG_RD_WR |
+                               SCFG_SNPCNFGCR_EDMA_SNP);
+
        return 0;
 }
index c12706d..9317272 100644 (file)
@@ -152,6 +152,12 @@ struct ccsr_gur {
 #define SCFG_ETSECCMCR_GE1_CLK125      0x08000000
 #define SCFG_PIXCLKCR_PXCKEN           0x80000000
 #define SCFG_QSPI_CLKSEL               0xc0100000
+#define SCFG_SNPCNFGCR_SEC_RD_WR       0xc0000000
+#define SCFG_SNPCNFGCR_DCU_RD_WR       0x03000000
+#define SCFG_SNPCNFGCR_SATA_RD_WR      0x00c00000
+#define SCFG_SNPCNFGCR_USB3_RD_WR      0x00300000
+#define SCFG_SNPCNFGCR_DBG_RD_WR       0x000c0000
+#define SCFG_SNPCNFGCR_EDMA_SNP                0x00020000
 #define SCFG_ENDIANCR_LE               0x80000000
 
 /* Supplemental Configuration Unit */