drm/amd/display: Add double buffer machanism to ICSC

- Video playback shows tearing when adjusting
brightness through radeon custom settings.
- Now added double buffer mechanism to switch
input CSC from register buffer ICSC and COMA
- Improved tab alignment

Signed-off-by: Xingyue Tao <xingyue.tao@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h
index 17b062a..b81b2aa 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h
@@ -108,6 +108,8 @@
        SRI(CM_DGAM_LUT_DATA, CM, id), \
        SRI(CM_CONTROL, CM, id), \
        SRI(CM_DGAM_CONTROL, CM, id), \
+       SRI(CM_TEST_DEBUG_INDEX, CM, id), \
+       SRI(CM_TEST_DEBUG_DATA, CM, id), \
        SRI(FORMAT_CONTROL, CNVC_CFG, id), \
        SRI(CNVC_SURFACE_PIXEL_FORMAT, CNVC_CFG, id), \
        SRI(CURSOR0_CONTROL, CNVC_CUR, id), \
@@ -300,6 +302,7 @@
        TF_SF(CM0_CM_DGAM_LUT_INDEX, CM_DGAM_LUT_INDEX, mask_sh), \
        TF_SF(CM0_CM_DGAM_LUT_DATA, CM_DGAM_LUT_DATA, mask_sh), \
        TF_SF(CM0_CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, mask_sh), \
+       TF_SF(CM0_CM_TEST_DEBUG_INDEX, CM_TEST_DEBUG_INDEX, mask_sh), \
        TF_SF(CNVC_CFG0_FORMAT_CONTROL, CNVC_BYPASS, mask_sh), \
        TF2_SF(CNVC_CFG0, FORMAT_CONTROL__ALPHA_EN, mask_sh), \
        TF_SF(CNVC_CFG0_FORMAT_CONTROL, FORMAT_EXPANSION_MODE, mask_sh), \
@@ -1010,6 +1013,8 @@
        type CUR0_EXPANSION_MODE; \
        type CUR0_ENABLE; \
        type CM_BYPASS; \
+       type CM_TEST_DEBUG_INDEX; \
+       type CM_TEST_DEBUG_DATA_ID9_ICSC_MODE; \
        type FORMAT_CONTROL__ALPHA_EN; \
        type CUR0_COLOR0; \
        type CUR0_COLOR1; \
@@ -1255,6 +1260,8 @@ struct dcn_dpp_mask {
        uint32_t CM_IGAM_LUT_RW_CONTROL; \
        uint32_t CM_IGAM_LUT_RW_INDEX; \
        uint32_t CM_IGAM_LUT_SEQ_COLOR; \
+       uint32_t CM_TEST_DEBUG_INDEX; \
+       uint32_t CM_TEST_DEBUG_DATA; \
        uint32_t FORMAT_CONTROL; \
        uint32_t CNVC_SURFACE_PIXEL_FORMAT; \
        uint32_t CURSOR_CONTROL; \
@@ -1289,8 +1296,8 @@ struct dcn10_dpp {
 
 enum dcn10_input_csc_select {
        INPUT_CSC_SELECT_BYPASS = 0,
-       INPUT_CSC_SELECT_ICSC,
-       INPUT_CSC_SELECT_COMA
+       INPUT_CSC_SELECT_ICSC = 1,
+       INPUT_CSC_SELECT_COMA = 2
 };
 
 void dpp1_set_cursor_attributes(

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
index fb32975..cc51141 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
@@ -267,6 +267,7 @@ void dpp1_cm_set_output_csc_default(
                BREAK_TO_DEBUGGER();
                return;
        }
+
        dpp1_cm_program_color_matrix(dpp, regval);
        REG_SET(CM_OCSC_CONTROL, 0, CM_OCSC_MODE, ocsc_mode);
 }
@@ -330,6 +331,7 @@ void dpp1_cm_set_output_csc_adjustment(
 {
        struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
        uint32_t ocsc_mode = 4;
+
        dpp1_cm_program_color_matrix(dpp, regval);
        REG_SET(CM_OCSC_CONTROL, 0, CM_OCSC_MODE, ocsc_mode);
 }
@@ -437,17 +439,18 @@ void dpp1_cm_program_regamma_lutb_settings(
 void dpp1_program_input_csc(
                struct dpp *dpp_base,
                enum dc_color_space color_space,
-               enum dcn10_input_csc_select select,
+               enum dcn10_input_csc_select input_select,
                const struct out_csc_color_matrix *tbl_entry)
 {
        struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
        int i;
        int arr_size = sizeof(dcn10_input_csc_matrix)/sizeof(struct dcn10_input_csc_matrix);
        const uint16_t *regval = NULL;
-       uint32_t selection = 1;
+       uint32_t cur_select = 0;
+       enum dcn10_input_csc_select select;
        struct color_matrices_reg gam_regs;
 
-       if (select == INPUT_CSC_SELECT_BYPASS) {
+       if (input_select == INPUT_CSC_SELECT_BYPASS) {
                REG_SET(CM_ICSC_CONTROL, 0, CM_ICSC_MODE, 0);
                return;
        }
@@ -467,36 +470,45 @@ void dpp1_program_input_csc(
                regval = tbl_entry->regval;
        }
 
-       if (select == INPUT_CSC_SELECT_COMA)
-               selection = 2;
-       REG_SET(CM_ICSC_CONTROL, 0,
-                       CM_ICSC_MODE, selection);
+       /* determine which CSC matrix (icsc or coma) we are using
+        * currently.  select the alternate set to double buffer
+        * the CSC update so CSC is updated on frame boundary
+        */
+       REG_SET(CM_TEST_DEBUG_INDEX, 0,
+                       CM_TEST_DEBUG_INDEX, 9);
+
+       REG_GET(CM_TEST_DEBUG_DATA,
+                       CM_TEST_DEBUG_DATA_ID9_ICSC_MODE, &cur_select);
+
+       if (cur_select != INPUT_CSC_SELECT_ICSC)
+               select = INPUT_CSC_SELECT_ICSC;
+       else
+               select = INPUT_CSC_SELECT_COMA;
 
        gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_ICSC_C11;
        gam_regs.masks.csc_c11  = dpp->tf_mask->CM_ICSC_C11;
        gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_ICSC_C12;
        gam_regs.masks.csc_c12 = dpp->tf_mask->CM_ICSC_C12;
 
-
        if (select == INPUT_CSC_SELECT_ICSC) {
 
                gam_regs.csc_c11_c12 = REG(CM_ICSC_C11_C12);
                gam_regs.csc_c33_c34 = REG(CM_ICSC_C33_C34);
 
-               cm_helper_program_color_matrices(
-                               dpp->base.ctx,
-                               regval,
-                               &gam_regs);
        } else {
 
                gam_regs.csc_c11_c12 = REG(CM_COMA_C11_C12);
                gam_regs.csc_c33_c34 = REG(CM_COMA_C33_C34);
 
-               cm_helper_program_color_matrices(
-                               dpp->base.ctx,
-                               regval,
-                               &gam_regs);
        }
+
+       cm_helper_program_color_matrices(
+                       dpp->base.ctx,
+                       regval,
+                       &gam_regs);
+
+       REG_SET(CM_ICSC_CONTROL, 0,
+                               CM_ICSC_MODE, select);
 }
 
 //keep here for now, decide multi dce support later

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
index a3fe343..d321da9 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
@@ -319,12 +319,41 @@ static const struct dcn_dpp_registers tf_regs[] = {
        tf_regs(3),
 };
 
+/*
+ *
+       DCN1 CM debug status register definition
+
+       register :ID9_CM_STATUS do
+       implement_ref :cm
+       map to:  :cmdebugind, at: j
+       width 32
+       disclosure   NEVER
+
+               field :ID9_VUPDATE_CFG, [0], R
+               field :ID9_IGAM_LUT_MODE, [2..1], R
+               field :ID9_BNS_BYPASS, [3], R
+               field :ID9_ICSC_MODE, [5..4], R
+               field :ID9_DGAM_LUT_MODE, [8..6], R
+               field :ID9_HDR_BYPASS, [9], R
+               field :ID9_GAMUT_REMAP_MODE, [11..10], R
+               field :ID9_RGAM_LUT_MODE, [14..12], R
+               #1 free bit
+               field :ID9_OCSC_MODE, [18..16], R
+               field :ID9_DENORM_MODE, [21..19], R
+               field :ID9_ROUND_TRUNC_MODE, [25..22], R
+               field :ID9_DITHER_EN, [26], R
+               field :ID9_DITHER_MODE, [28..27], R
+       end
+*/
+
 static const struct dcn_dpp_shift tf_shift = {
-       TF_REG_LIST_SH_MASK_DCN10(__SHIFT)
+       TF_REG_LIST_SH_MASK_DCN10(__SHIFT),
+       .CM_TEST_DEBUG_DATA_ID9_ICSC_MODE = 0x4
 };
 
 static const struct dcn_dpp_mask tf_mask = {
        TF_REG_LIST_SH_MASK_DCN10(_MASK),
+       .CM_TEST_DEBUG_DATA_ID9_ICSC_MODE = 0x30
 };
 
 static const struct dcn_mpc_registers mpc_regs = {