- "mediatek,mt7981-thermal", "mediatek,mt7986-thermal" : For MT7981 SoC
- "mediatek,mt7986-thermal" : For MT7986 SoC
- "mediatek,mt8183-thermal" : For MT8183 family of SoCs
+ - "mediatek,mt8365-thermal" : For MT8365 family of SoCs
- "mediatek,mt8516-thermal", "mediatek,mt2701-thermal : For MT8516 family of SoCs
- reg: Address range of the thermal controller
- interrupts: IRQ for the thermal controller
#
# Makefile for sensor chip drivers.
#
-
+CFLAGS_thermal_core.o := -I$(src)
obj-$(CONFIG_THERMAL) += thermal_sys.o
thermal_sys-y += thermal_core.o thermal_sysfs.o
thermal_sys-y += thermal_trip.o thermal_helpers.o
thermal_sys-$(CONFIG_THERMAL_ACPI) += thermal_acpi.o
# governors
+CFLAGS_gov_power_allocator.o := -I$(src)
thermal_sys-$(CONFIG_THERMAL_GOV_FAIR_SHARE) += gov_fair_share.o
thermal_sys-$(CONFIG_THERMAL_GOV_BANG_BANG) += gov_bang_bang.o
thermal_sys-$(CONFIG_THERMAL_GOV_STEP_WISE) += gov_step_wise.o
#include <linux/thermal.h>
#include <linux/units.h>
-#include <trace/events/thermal.h>
+#include "thermal_trace.h"
/*
* Cooling state <-> CPUFreq frequency
struct db8500_thermal_zone {
struct thermal_zone_device *tz;
+ struct device *dev;
unsigned long interpolated_temp;
unsigned int cur_index;
};
idx -= 1;
db8500_thermal_update_config(th, idx, next_low, next_high);
- dev_dbg(&th->tz->device,
+ dev_dbg(th->dev,
"PRCMU set max %ld, min %ld\n", next_high, next_low);
thermal_zone_device_update(th->tz, THERMAL_EVENT_UNSPECIFIED);
db8500_thermal_update_config(th, idx, next_low, next_high);
- dev_dbg(&th->tz->device,
+ dev_dbg(th->dev,
"PRCMU set max %ld, min %ld\n", next_high, next_low);
} else if (idx == num_points - 1)
/* So we roof out 1 degree over the max point */
if (!th)
return -ENOMEM;
+ th->dev = dev;
+
low_irq = platform_get_irq_byname(pdev, "IRQ_HOTMON_LOW");
if (low_irq < 0)
return low_irq;
#include <linux/thermal.h>
#include <linux/units.h>
-#include <trace/events/thermal.h>
+#include "thermal_trace.h"
#define SCALE_ERROR_MITIGATION 100
*/
#include <linux/thermal.h>
-#include <trace/events/thermal.h>
+#include "thermal_trace.h"
#include "thermal_core.h"
#include <linux/thermal.h>
#define CREATE_TRACE_POINTS
-#include <trace/events/thermal_power_allocator.h>
+#include "thermal_trace_ipa.h"
#include "thermal_core.h"
#include <linux/thermal.h>
#include <linux/minmax.h>
-#include <trace/events/thermal.h>
+#include "thermal_trace.h"
#include "thermal_core.h"
{
struct hisi_thermal_data *data;
struct device *dev = &pdev->dev;
- struct resource *res;
int i, ret;
data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
platform_set_drvdata(pdev, data);
data->ops = of_device_get_match_data(dev);
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- data->regs = devm_ioremap_resource(dev, res);
+ data->regs = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(data->regs))
return PTR_ERR(data->regs);
return 0;
}
-static int imx_get_crit_temp(struct thermal_zone_device *tz, int *temp)
-{
- *temp = trips[IMX_TRIP_CRITICAL].temperature;
-
- return 0;
-}
-
-static int imx_set_trip_temp(struct thermal_zone_device *tz, int trip,
+static int imx_set_trip_temp(struct thermal_zone_device *tz, int trip_id,
int temp)
{
struct imx_thermal_data *data = thermal_zone_device_priv(tz);
+ struct thermal_trip trip;
int ret;
ret = pm_runtime_resume_and_get(data->dev);
if (ret < 0)
return ret;
+ ret = __thermal_zone_get_trip(tz, trip_id, &trip);
+ if (ret)
+ return ret;
+
/* do not allow changing critical threshold */
- if (trip == IMX_TRIP_CRITICAL)
+ if (trip.type == THERMAL_TRIP_CRITICAL)
return -EPERM;
/* do not allow passive to be set higher than critical */
if (temp < 0 || temp > trips[IMX_TRIP_CRITICAL].temperature)
return -EINVAL;
- trips[IMX_TRIP_PASSIVE].temperature = temp;
-
imx_set_alarm_temp(data, temp);
pm_runtime_put(data->dev);
.unbind = imx_unbind,
.get_temp = imx_get_temp,
.change_mode = imx_change_mode,
- .get_crit_temp = imx_get_crit_temp,
.set_trip_temp = imx_set_trip_temp,
};
#define AUXADC_CON2_V 0x010
#define AUXADC_DATA(channel) (0x14 + (channel) * 4)
+#define APMIXED_SYS_TS_CON0 0x600
#define APMIXED_SYS_TS_CON1 0x604
/* Thermal Controller Registers */
/* The calibration coefficient of sensor */
#define MT7986_CALIBRATION 165
+/* MT8365 */
+#define MT8365_TEMP_AUXADC_CHANNEL 11
+#define MT8365_CALIBRATION 164
+#define MT8365_NUM_CONTROLLER 1
+#define MT8365_NUM_BANKS 1
+#define MT8365_NUM_SENSORS 3
+#define MT8365_NUM_SENSORS_PER_ZONE 3
+#define MT8365_TS1 0
+#define MT8365_TS2 1
+#define MT8365_TS3 2
+
struct mtk_thermal;
struct thermal_bank_cfg {
bool need_switch_bank;
struct thermal_bank_cfg bank_data[MAX_NUM_ZONES];
enum mtk_thermal_version version;
+ u32 apmixed_buffer_ctl_reg;
+ u32 apmixed_buffer_ctl_mask;
+ u32 apmixed_buffer_ctl_set;
};
struct mtk_thermal {
static const int mt7986_vts_index[MT7986_NUM_SENSORS] = { VTS1 };
static const int mt7986_tc_offset[MT7986_NUM_CONTROLLER] = { 0x0, };
+/* MT8365 thermal sensor data */
+static const int mt8365_bank_data[MT8365_NUM_SENSORS] = {
+ MT8365_TS1, MT8365_TS2, MT8365_TS3
+};
+
+static const int mt8365_msr[MT8365_NUM_SENSORS_PER_ZONE] = {
+ TEMP_MSR0, TEMP_MSR1, TEMP_MSR2
+};
+
+static const int mt8365_adcpnp[MT8365_NUM_SENSORS_PER_ZONE] = {
+ TEMP_ADCPNP0, TEMP_ADCPNP1, TEMP_ADCPNP2
+};
+
+static const int mt8365_mux_values[MT8365_NUM_SENSORS] = { 0, 1, 2 };
+static const int mt8365_tc_offset[MT8365_NUM_CONTROLLER] = { 0 };
+
+static const int mt8365_vts_index[MT8365_NUM_SENSORS] = { VTS1, VTS2, VTS3 };
+
/*
* The MT8173 thermal controller has four banks. Each bank can read up to
* four temperature sensors simultaneously. The MT8173 has a total of 5
};
/*
+ * The MT8365 thermal controller has one bank, which can read up to
+ * four temperature sensors simultaneously. The MT8365 has a total of 3
+ * temperature sensors.
+ *
+ * The thermal core only gets the maximum temperature of this one bank,
+ * so the bank concept wouldn't be necessary here. However, the SVS (Smart
+ * Voltage Scaling) unit makes its decisions based on the same bank
+ * data.
+ */
+static const struct mtk_thermal_data mt8365_thermal_data = {
+ .auxadc_channel = MT8365_TEMP_AUXADC_CHANNEL,
+ .num_banks = MT8365_NUM_BANKS,
+ .num_sensors = MT8365_NUM_SENSORS,
+ .vts_index = mt8365_vts_index,
+ .cali_val = MT8365_CALIBRATION,
+ .num_controller = MT8365_NUM_CONTROLLER,
+ .controller_offset = mt8365_tc_offset,
+ .need_switch_bank = false,
+ .bank_data = {
+ {
+ .num_sensors = MT8365_NUM_SENSORS,
+ .sensors = mt8365_bank_data
+ },
+ },
+ .msr = mt8365_msr,
+ .adcpnp = mt8365_adcpnp,
+ .sensor_mux_values = mt8365_mux_values,
+ .version = MTK_THERMAL_V1,
+ .apmixed_buffer_ctl_reg = APMIXED_SYS_TS_CON0,
+ .apmixed_buffer_ctl_mask = (u32) ~GENMASK(29, 28),
+ .apmixed_buffer_ctl_set = 0,
+};
+
+/*
* The MT2712 thermal controller has one bank, which can read up to
* four temperature sensors simultaneously. The MT2712 has a total of 4
* temperature sensors.
.adcpnp = mt7622_adcpnp,
.sensor_mux_values = mt7622_mux_values,
.version = MTK_THERMAL_V2,
+ .apmixed_buffer_ctl_reg = APMIXED_SYS_TS_CON1,
+ .apmixed_buffer_ctl_mask = GENMASK(31, 6) | BIT(3),
+ .apmixed_buffer_ctl_set = BIT(0),
};
/*
mt, conf->bank_data[bank->id].sensors[i], raw);
- /*
- * The first read of a sensor often contains very high bogus
- * temperature value. Filter these out so that the system does
- * not immediately shut down.
- */
- if (temp > 200000)
- temp = 0;
-
if (temp > max)
max = temp;
}
{
.compatible = "mediatek,mt8183-thermal",
.data = (void *)&mt8183_thermal_data,
+ },
+ {
+ .compatible = "mediatek,mt8365-thermal",
+ .data = (void *)&mt8365_thermal_data,
}, {
},
};
MODULE_DEVICE_TABLE(of, mtk_thermal_of_match);
-static void mtk_thermal_turn_on_buffer(void __iomem *apmixed_base)
+static void mtk_thermal_turn_on_buffer(struct mtk_thermal *mt,
+ void __iomem *apmixed_base)
{
- int tmp;
+ u32 tmp;
- tmp = readl(apmixed_base + APMIXED_SYS_TS_CON1);
- tmp &= ~(0x37);
- tmp |= 0x1;
- writel(tmp, apmixed_base + APMIXED_SYS_TS_CON1);
+ if (!mt->conf->apmixed_buffer_ctl_reg)
+ return;
+
+ tmp = readl(apmixed_base + mt->conf->apmixed_buffer_ctl_reg);
+ tmp &= mt->conf->apmixed_buffer_ctl_mask;
+ tmp |= mt->conf->apmixed_buffer_ctl_set;
+ writel(tmp, apmixed_base + mt->conf->apmixed_buffer_ctl_reg);
udelay(200);
}
goto err_disable_clk_auxadc;
}
- if (mt->conf->version != MTK_THERMAL_V1) {
- mtk_thermal_turn_on_buffer(apmixed_base);
+ mtk_thermal_turn_on_buffer(mt, apmixed_base);
+
+ if (mt->conf->version != MTK_THERMAL_V2)
mtk_thermal_release_periodic_ts(mt, auxadc_base);
- }
if (mt->conf->version == MTK_THERMAL_V1)
mt->raw_to_mcelsius = raw_to_mcelsius_v1;
platform_set_drvdata(pdev, mt);
+ /* Delay for thermal banks to be ready */
+ msleep(30);
+
tzdev = devm_thermal_of_zone_register(&pdev->dev, 0, mt,
&mtk_thermal_ops);
if (IS_ERR(tzdev)) {
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
-#include <linux/sys_soc.h>
#include <linux/thermal.h>
#include "thermal_hwmon.h"
#define REG_GEN3_IRQTEMP1 0x14
#define REG_GEN3_IRQTEMP2 0x18
#define REG_GEN3_IRQTEMP3 0x1C
-#define REG_GEN3_CTSR 0x20
#define REG_GEN3_THCTR 0x20
#define REG_GEN3_TEMP 0x28
#define REG_GEN3_THCODE1 0x50
#define IRQ_TEMPD2 BIT(4)
#define IRQ_TEMPD3 BIT(5)
-/* CTSR bits */
-#define CTSR_PONM BIT(8)
-#define CTSR_AOUT BIT(7)
-#define CTSR_THBGR BIT(5)
-#define CTSR_VMEN BIT(4)
-#define CTSR_VMST BIT(1)
-#define CTSR_THSST BIT(0)
-
/* THCTR bits */
#define THCTR_PONM BIT(6)
#define THCTR_THSST BIT(0)
struct rcar_gen3_thermal_tsc *tscs[TSC_MAX_NUM];
struct thermal_zone_device_ops ops;
unsigned int num_tscs;
- void (*thermal_init)(struct rcar_gen3_thermal_priv *priv,
- struct rcar_gen3_thermal_tsc *tsc);
int ptat[3];
};
return IRQ_HANDLED;
}
-static const struct soc_device_attribute r8a7795es1[] = {
- { .soc_id = "r8a7795", .revision = "ES1.*" },
- { /* sentinel */ }
-};
-
static bool rcar_gen3_thermal_read_fuses(struct rcar_gen3_thermal_priv *priv)
{
unsigned int i;
return true;
}
-static void rcar_gen3_thermal_init_r8a7795es1(struct rcar_gen3_thermal_priv *priv,
- struct rcar_gen3_thermal_tsc *tsc)
-{
- rcar_gen3_thermal_write(tsc, REG_GEN3_CTSR, CTSR_THBGR);
- rcar_gen3_thermal_write(tsc, REG_GEN3_CTSR, 0x0);
-
- usleep_range(1000, 2000);
-
- rcar_gen3_thermal_write(tsc, REG_GEN3_CTSR, CTSR_PONM);
-
- rcar_gen3_thermal_write(tsc, REG_GEN3_IRQCTL, 0x3F);
- rcar_gen3_thermal_write(tsc, REG_GEN3_IRQMSK, 0);
- if (priv->ops.set_trips)
- rcar_gen3_thermal_write(tsc, REG_GEN3_IRQEN,
- IRQ_TEMPD1 | IRQ_TEMP2);
-
- rcar_gen3_thermal_write(tsc, REG_GEN3_CTSR,
- CTSR_PONM | CTSR_AOUT | CTSR_THBGR | CTSR_VMEN);
-
- usleep_range(100, 200);
-
- rcar_gen3_thermal_write(tsc, REG_GEN3_CTSR,
- CTSR_PONM | CTSR_AOUT | CTSR_THBGR | CTSR_VMEN |
- CTSR_VMST | CTSR_THSST);
-
- usleep_range(1000, 2000);
-}
-
static void rcar_gen3_thermal_init(struct rcar_gen3_thermal_priv *priv,
struct rcar_gen3_thermal_tsc *tsc)
{
return -ENOMEM;
priv->ops = rcar_gen3_tz_of_ops;
- priv->thermal_init = rcar_gen3_thermal_init;
- if (soc_device_match(r8a7795es1))
- priv->thermal_init = rcar_gen3_thermal_init_r8a7795es1;
platform_set_drvdata(pdev, priv);
for (i = 0; i < priv->num_tscs; i++) {
struct rcar_gen3_thermal_tsc *tsc = priv->tscs[i];
- priv->thermal_init(priv, tsc);
+ rcar_gen3_thermal_init(priv, tsc);
rcar_gen3_thermal_calc_coefs(priv, tsc, *ths_tj_1);
zone = devm_thermal_of_zone_register(dev, i, tsc, &priv->ops);
for (i = 0; i < priv->num_tscs; i++) {
struct rcar_gen3_thermal_tsc *tsc = priv->tscs[i];
- priv->thermal_init(priv, tsc);
+ rcar_gen3_thermal_init(priv, tsc);
}
return 0;
* Thermal_zone doesn't enable hwmon as default,
* enable it here
*/
- sensor->th_dev->tzp->no_hwmon = false;
ret = thermal_add_hwmon_sysfs(sensor->th_dev);
if (ret)
goto err_tz;
#include <linux/suspend.h>
#define CREATE_TRACE_POINTS
-#include <trace/events/thermal.h>
+#include "thermal_trace.h"
#include "thermal_core.h"
#include "thermal_hwmon.h"
#include <linux/string.h>
#include <linux/sysfs.h>
-#include <trace/events/thermal.h>
-
#include "thermal_core.h"
+#include "thermal_trace.h"
int get_tz_trend(struct thermal_zone_device *tz, int trip)
{
#endif /* CONFIG_DEVFREQ_THERMAL */
#endif /* _TRACE_THERMAL_H */
+#undef TRACE_INCLUDE_PATH
+#define TRACE_INCLUDE_PATH .
+
+#undef TRACE_INCLUDE_FILE
+#define TRACE_INCLUDE_FILE thermal_trace
+
/* This part must be outside protection */
#include <trace/define_trace.h>
);
#endif /* _TRACE_THERMAL_POWER_ALLOCATOR_H */
+#undef TRACE_INCLUDE_PATH
+#define TRACE_INCLUDE_PATH .
+
+#undef TRACE_INCLUDE_FILE
+#define TRACE_INCLUDE_FILE thermal_trace_ipa
+
/* This part must be outside protection */
#include <trace/define_trace.h>
#include "ti-bandgap.h"
#include "../thermal_hwmon.h"
+#define TI_BANDGAP_UPDATE_INTERVAL_MS 250
+
/* common data structures */
struct ti_thermal_data {
struct cpufreq_policy *policy;
char *domain)
{
struct ti_thermal_data *data;
- int interval;
data = ti_bandgap_get_sensor_data(bgp, id);
return PTR_ERR(data->ti_thermal);
}
- interval = jiffies_to_msecs(data->ti_thermal->polling_delay_jiffies);
-
ti_bandgap_set_sensor_data(bgp, id, data);
- ti_bandgap_write_update_interval(bgp, data->sensor_id, interval);
+ ti_bandgap_write_update_interval(bgp, data->sensor_id,
+ TI_BANDGAP_UPDATE_INTERVAL_MS);
if (devm_thermal_add_hwmon_sysfs(bgp->dev, data->ti_thermal))
dev_warn(bgp->dev, "failed to add hwmon sysfs attributes\n");
projects / platform / kernel / linux-starfive.git / commitdiff