drm/bridge/sii8620: simplify MHL3 mode setting

It is not necessary to set REG_COC_CTL0, REG_MHL_COC_CTL1 registers.

Change-Id: Id363df66baffe0be9f96e61597bc04a16bf42aad
Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>

diff --git a/drivers/gpu/drm/bridge/sil-sii8620.c b/drivers/gpu/drm/bridge/sil-sii8620.c
index 1ef5924f75bfc16e34c760ce215f73b96ec9edfc..92f5dd61129bec8301830465ad0d792b31a3590f 100644 (file)
--- a/drivers/gpu/drm/bridge/sil-sii8620.c
+++ b/drivers/gpu/drm/bridge/sil-sii8620.c
@@ -976,12 +976,8 @@ static void sii8620_set_mode(struct sii8620 *ctx, enum sii8620_mode mode)
                );
                break;
        case CM_MHL3:
-               sii8620_write_seq_static(ctx,
-                       REG_M3_CTRL, VAL_M3_CTRL_MHL3_VALUE,
-                       REG_COC_CTL0, 0x40,
-                       REG_MHL_COC_CTL1, 0x07
-               );
-               break;
+               sii8620_write(ctx, REG_M3_CTRL, VAL_M3_CTRL_MHL3_VALUE);
+               return;
        case CM_DISCONNECTED:
                break;
        default: