+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-- | FileCheck %s
; This tests whether or not we generate vectors large than preferred vector width when
; Function Attrs: nounwind uwtable
define weak_odr dso_local void @A(i8* %src, i8* %dst) local_unnamed_addr #0 {
+; CHECK-LABEL: A:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vmovups (%rdi), %xmm0
+; CHECK-NEXT: vmovups 16(%rdi), %xmm1
+; CHECK-NEXT: vmovups %xmm1, 16(%rsi)
+; CHECK-NEXT: vmovups %xmm0, (%rsi)
+; CHECK-NEXT: retq
entry:
-; CHECK: A
-; CHECK-NOT: vmovups %ymm
-; CHECK: vmovups %xmm
call void @llvm.memmove.p0i8.p0i8.i64(i8* align 1 %dst, i8* align 1 %src, i64 32, i1 false)
ret void
}
; Function Attrs: nounwind uwtable
define weak_odr dso_local void @B(i8* %src, i8* %dst) local_unnamed_addr #0 {
+; CHECK-LABEL: B:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vmovups (%rdi), %xmm0
+; CHECK-NEXT: vmovups 16(%rdi), %xmm1
+; CHECK-NEXT: vmovups 32(%rdi), %xmm2
+; CHECK-NEXT: vmovups 48(%rdi), %xmm3
+; CHECK-NEXT: vmovups %xmm3, 48(%rsi)
+; CHECK-NEXT: vmovups %xmm2, 32(%rsi)
+; CHECK-NEXT: vmovups %xmm1, 16(%rsi)
+; CHECK-NEXT: vmovups %xmm0, (%rsi)
+; CHECK-NEXT: retq
entry:
-; CHECK: B
-; CHECK-NOT: vmovups %zmm
-; CHECK: vmovups %xmm
call void @llvm.memmove.p0i8.p0i8.i64(i8* align 1 %dst, i8* align 1 %src, i64 64, i1 false)
ret void
}
; Function Attrs: nounwind uwtable
define weak_odr dso_local void @C(i8* %src, i8* %dst) local_unnamed_addr #2 {
+; CHECK-LABEL: C:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vmovups (%rdi), %ymm0
+; CHECK-NEXT: vmovups %ymm0, (%rsi)
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: retq
entry:
-; CHECK: C
-; CHECK-NOT: vmovups %ymm
-; CHECK: vmovups %ymm
call void @llvm.memmove.p0i8.p0i8.i64(i8* align 1 %dst, i8* align 1 %src, i64 32, i1 false)
ret void
}
; Function Attrs: nounwind uwtable
define weak_odr dso_local void @D(i8* %src, i8* %dst) local_unnamed_addr #2 {
+; CHECK-LABEL: D:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vmovups (%rdi), %ymm0
+; CHECK-NEXT: vmovups 32(%rdi), %ymm1
+; CHECK-NEXT: vmovups %ymm1, 32(%rsi)
+; CHECK-NEXT: vmovups %ymm0, (%rsi)
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: retq
entry:
-; CHECK: D
-; CHECK-NOT: vmovups %zmm
-; CHECK: vmovups %ymm
call void @llvm.memmove.p0i8.p0i8.i64(i8* align 1 %dst, i8* align 1 %src, i64 64, i1 false)
ret void
}