i.MX7ULP: Enable Job ring driver model.
authorGaurav Jain <gaurav.jain@nxp.com>
Thu, 24 Mar 2022 06:20:31 +0000 (11:50 +0530)
committerStefano Babic <sbabic@denx.de>
Tue, 12 Apr 2022 09:18:34 +0000 (11:18 +0200)
added crypto node in device tree.
sec is initialized based on job ring information processed
from device tree.

Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
arch/arm/Kconfig
arch/arm/dts/imx7ulp.dtsi
arch/arm/mach-imx/mx7ulp/Kconfig
arch/arm/mach-imx/mx7ulp/soc.c

index 9b3c7b1..79b8046 100644 (file)
@@ -923,7 +923,7 @@ config ARCH_MX7ULP
        select CPU_V7A
        select GPIO_EXTRA_HEADER
        select MACH_IMX
-       select SYS_FSL_HAS_SEC if IMX_HAB
+       select SYS_FSL_HAS_SEC
        select SYS_FSL_SEC_COMPAT_4
        select SYS_FSL_SEC_LE
        select ROM_UNIFIED_SECTIONS
index 7bcd2cc..494b9d9 100644 (file)
@@ -1,5 +1,6 @@
 /*
  * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2021 NXP
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
                        };
                };
 
+               crypto: crypto@40240000 {
+                       compatible = "fsl,sec-v4.0";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       reg = <0x40240000 0x10000>;
+                       ranges = <0 0x40240000 0x10000>;
+                       clocks = <&clks IMX7ULP_CLK_CAAM>,
+                                <&clks IMX7ULP_CLK_NIC1_BUS_DIV>;
+                       clock-names = "aclk", "ipg";
+
+                       sec_jr0: jr@1000 {
+                               compatible = "fsl,sec-v4.0-job-ring";
+                               reg = <0x1000 0x1000>;
+                               interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
+                       };
+
+                       sec_jr1: jr@2000 {
+                               compatible = "fsl,sec-v4.0-job-ring";
+                               reg = <0x2000 0x1000>;
+                               interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
+                       };
+               };
+
                tpm5: tpm@40260000 {
                        compatible = "fsl,imx7ulp-tpm";
                        reg = <0x40260000 0x1000>;
index 15c3ab6..615d75b 100644 (file)
@@ -40,6 +40,8 @@ config TARGET_MX7ULP_EVK
        bool "Support mx7ulp EVK board"
        select MX7ULP
        select SYS_ARCH_TIMER
+       select FSL_CAAM
+       select ARCH_MISC_INIT
 
 endchoice
 
index bc41cbc..08bdc0c 100644 (file)
@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2021 NXP
  */
 
 #include <common.h>
@@ -16,6 +17,7 @@
 #include <asm/mach-imx/sys_proto.h>
 #include <asm/setup.h>
 #include <linux/bitops.h>
+#include <dm.h>
 
 #define PMC0_BASE_ADDR         0x410a1000
 #define PMC0_CTRL              0x28
@@ -82,6 +84,22 @@ int arch_cpu_init(void)
        return 0;
 }
 
+#if defined(CONFIG_ARCH_MISC_INIT)
+int arch_misc_init(void)
+{
+       if (IS_ENABLED(CONFIG_FSL_CAAM)) {
+               struct udevice *dev;
+               int ret;
+
+               ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
+               if (ret)
+                       printf("Failed to initialize %s: %d\n", dev->name, ret);
+       }
+
+       return 0;
+}
+#endif
+
 #ifdef CONFIG_BOARD_POSTCLK_INIT
 int board_postclk_init(void)
 {