re PR target/11183 ([arm] ICE in change_address_1 (3.3) / subreg_hard_regno (3.4))

PR target/11183
* arm.h (CANNOT_CHANGE_MODE_CLASS): Define.

From-SVN: r67947

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index fd2c294..4713756 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2003-06-14  Richard Earnshaw  <rearnsha@arm.com>
+
+       PR target/11183
+       * arm.h (CANNOT_CHANGE_MODE_CLASS): Define.
+
 2003-06-14  Roger Sayle  <roger@eyesopen.com>
 
        * opts.sh: Work around a mysterious feature in cygwin's gawk

diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h
index cffdd3b..acec706 100644 (file)
--- a/gcc/config/arm/arm.h
+++ b/gcc/config/arm/arm.h
@@ -1146,6 +1146,12 @@ enum reg_class
    or could index an array.  */
 #define REGNO_REG_CLASS(REGNO)  arm_regno_class (REGNO)
 
+/* FPA registers can't do dubreg as all values are reformatted to internal
+   precision.  */
+#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS)      \
+  (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO)          \
+   ? reg_classes_intersect_p (FPA_REGS, (CLASS)) : 0)
+
 /* The class value for index registers, and the one for base regs.  */
 #define INDEX_REG_CLASS  (TARGET_THUMB ? LO_REGS : GENERAL_REGS)
 #define BASE_REG_CLASS   (TARGET_THUMB ? LO_REGS : GENERAL_REGS)