There is a slight possibility that the destination register
is a scalar register. We need to check it here.
Signed-off-by: Zhigang Gong <zhigang.gong@linux.intel.com>
Tested-by: Lv, Meng <meng.lv@intel.com>
const Immediate imm = insn.getImmediate();
const GenRegister dst = sel.selReg(insn.getDst(0), type);
+ sel.push();
+ if (sel.isScalarOrBool(insn.getDst(0)) == true) {
+ sel.curr.execWidth = 1;
+ sel.curr.predicate = GEN_PREDICATE_NONE;
+ sel.curr.noMask = 1;
+ }
+
switch (type) {
case TYPE_U32:
case TYPE_S32:
case TYPE_S8: sel.MOV(dst, GenRegister::immw(imm.data.s8)); break;
default: NOT_SUPPORTED;
}
+ sel.pop();
return true;
}