drm/amd/display: Add PPS immediate update flag for DCN2

[Why]
This change is needed for DCN2 to make use of the immediate_update
flag. With this flag, update to PPS will be immediate, rather than
always taking place on dig_update signal.

[How]
Set AFMT_GENERIC7_FRAME/IMMEDIATE_UPDATE bits depending on flag
value.

Reviewed-by: Wenjing Liu <wenjing.liu@amd.com>
Acked-by: Anson Jacob <Anson.Jacob@amd.com>
Signed-off-by: Ilya <Ilya.Bakoulin@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
index f6e747f..c90b851 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
@@ -467,6 +467,11 @@ void optc2_lock_doublebuffer_enable(struct timing_generator *optc)
                        (h_blank_start - 200 - 1) / optc1->opp_count,
                        MASTER_UPDATE_LOCK_DB_Y,
                        v_blank_start - 1);
+
+       REG_SET_3(OTG_VUPDATE_KEEPOUT, 0,
+               MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET, 0,
+               MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET, 100,
+               OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN, 1);
 }
 
 void optc2_lock_doublebuffer_disable(struct timing_generator *optc)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c
index 11c50b5..aab25ca 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c
@@ -211,7 +211,8 @@ static void enc2_stream_encoder_stop_hdmi_info_packets(
 /* Update GSP7 SDP 128 byte long */
 static void enc2_update_gsp7_128_info_packet(
        struct dcn10_stream_encoder *enc1,
-       const struct dc_info_packet_128 *info_packet)
+       const struct dc_info_packet_128 *info_packet,
+       bool immediate_update)
 {
        uint32_t i;
 
@@ -266,7 +267,9 @@ static void enc2_update_gsp7_128_info_packet(
                REG_WRITE(AFMT_GENERIC_7, *content++);
        }
 
-       REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC7_FRAME_UPDATE, 1);
+       REG_UPDATE_2(AFMT_VBI_PACKET_CONTROL1,
+                       AFMT_GENERIC7_FRAME_UPDATE, !immediate_update,
+                       AFMT_GENERIC7_IMMEDIATE_UPDATE, immediate_update);
 }
 
 /* Set DSC-related configuration.
@@ -309,7 +312,7 @@ static void enc2_dp_set_dsc_pps_info_packet(struct stream_encoder *enc,
                pps_sdp.hb2 = 127;
                pps_sdp.hb3 = 0;
                memcpy(&pps_sdp.sb[0], dsc_packed_pps, sizeof(pps_sdp.sb));
-               enc2_update_gsp7_128_info_packet(enc1, &pps_sdp);
+               enc2_update_gsp7_128_info_packet(enc1, &pps_sdp, immediate_update);
 
                /* Enable Generic Stream Packet 7 (GSP) transmission */
                //REG_UPDATE(DP_SEC_CNTL,