ARM: zynq: Support systems with more memory banks

This is example how to change u-boot to support more memory banks read
from DT.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c
index 4c20450..183f642 100644 (file)
--- a/board/xilinx/zynq/board.c
+++ b/board/xilinx/zynq/board.c
@@ -111,26 +111,134 @@ int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
        return 0;
 }
 
+#if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
+/*
+ * fdt_get_reg - Fill buffer by information from DT
+ */
+static phys_size_t fdt_get_reg(const void *fdt, int nodeoffset, void *buf,
+                              const u32 *cell, int n)
+{
+       int i = 0, b, banks;
+       int parent_offset = fdt_parent_offset(fdt, nodeoffset);
+       int address_cells = fdt_address_cells(fdt, parent_offset);
+       int size_cells = fdt_size_cells(fdt, parent_offset);
+       char *p = buf;
+       u64 val;
+       u64 vals;
+
+       debug("%s: addr_cells=%x, size_cell=%x, buf=%p, cell=%p\n",
+             __func__, address_cells, size_cells, buf, cell);
+
+       /* Check memory bank setup */
+       banks = n % (address_cells + size_cells);
+       if (banks)
+               panic("Incorrect memory setup cells=%d, ac=%d, sc=%d\n",
+                     n, address_cells, size_cells);
+
+       banks = n / (address_cells + size_cells);
+
+       for (b = 0; b < banks; b++) {
+               debug("%s: Bank #%d:\n", __func__, b);
+               if (address_cells == 2) {
+                       val = cell[i + 1];
+                       val <<= 32;
+                       val |= cell[i];
+                       val = fdt64_to_cpu(val);
+                       debug("%s: addr64=%llx, ptr=%p, cell=%p\n",
+                             __func__, val, p, &cell[i]);
+                       *(phys_addr_t *)p = val;
+               } else {
+                       debug("%s: addr32=%x, ptr=%p\n",
+                             __func__, fdt32_to_cpu(cell[i]), p);
+                       *(phys_addr_t *)p = fdt32_to_cpu(cell[i]);
+               }
+               p += sizeof(phys_addr_t);
+               i += address_cells;
+
+               debug("%s: pa=%p, i=%x, size=%zu\n", __func__, p, i,
+                     sizeof(phys_addr_t));
+
+               if (size_cells == 2) {
+                       vals = cell[i + 1];
+                       vals <<= 32;
+                       vals |= cell[i];
+                       vals = fdt64_to_cpu(vals);
+
+                       debug("%s: size64=%llx, ptr=%p, cell=%p\n",
+                             __func__, vals, p, &cell[i]);
+                       *(phys_size_t *)p = vals;
+               } else {
+                       debug("%s: size32=%x, ptr=%p\n",
+                             __func__, fdt32_to_cpu(cell[i]), p);
+                       *(phys_size_t *)p = fdt32_to_cpu(cell[i]);
+               }
+               p += sizeof(phys_size_t);
+               i += size_cells;
+
+               debug("%s: ps=%p, i=%x, size=%zu\n",
+                     __func__, p, i, sizeof(phys_size_t));
+       }
+
+       /* Return the first address size */
+       return *(phys_size_t *)((char *)buf + sizeof(phys_addr_t));
+}
+
+#define FDT_REG_SIZE  sizeof(u32)
+/* Temp location for sharing data for storing */
+/* Up to 64-bit address + 64-bit size */
+static u8 tmp[CONFIG_NR_DRAM_BANKS * 16];
+
+void dram_init_banksize(void)
+{
+       int bank;
+
+       memcpy(&gd->bd->bi_dram[0], &tmp, sizeof(tmp));
+
+       for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
+               debug("Bank #%d: start %llx\n", bank,
+                     (unsigned long long)gd->bd->bi_dram[bank].start);
+               debug("Bank #%d: size %llx\n", bank,
+                     (unsigned long long)gd->bd->bi_dram[bank].size);
+       }
+}
+
 int dram_init(void)
 {
-       int node;
-       fdt_addr_t addr;
-       fdt_size_t size;
+       int node, len;
        const void *blob = gd->fdt_blob;
+       const u32 *cell;
 
-       node = fdt_node_offset_by_prop_value(blob, -1, "device_type",
-                                            "memory", 7);
-       if (node == -FDT_ERR_NOTFOUND) {
-               debug("ZYNQ DRAM: Can't get memory node\n");
-               return -1;
+       memset(&tmp, 0, sizeof(tmp));
+
+       /* find or create "/memory" node. */
+       node = fdt_subnode_offset(blob, 0, "memory");
+       if (node < 0) {
+               printf("%s: Can't get memory node\n", __func__);
+               return node;
        }
-       addr = fdtdec_get_addr_size(blob, node, "reg", &size);
-       if (addr == FDT_ADDR_T_NONE || size == 0) {
-               debug("ZYNQ DRAM: Can't get base address or size\n");
+
+       /* Get pointer to cells and lenght of it */
+       cell = fdt_getprop(blob, node, "reg", &len);
+       if (!cell) {
+               printf("%s: Can't get reg property\n", __func__);
                return -1;
        }
-       gd->ram_size = size;
+
+       gd->ram_size = fdt_get_reg(blob, node, &tmp, cell, len / FDT_REG_SIZE);
+
+       debug("%s: Initial DRAM size %llx\n", __func__, (u64)gd->ram_size);
+
+       zynq_ddrc_init();
+
+       return 0;
+}
+#else
+int dram_init(void)
+{
+       gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+
        zynq_ddrc_init();
 
        return 0;
 }
+#endif

diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h
index aac1e2b..2d941a7 100644 (file)
--- a/include/configs/zynq-common.h
+++ b/include/configs/zynq-common.h
@@ -277,7 +277,9 @@
 /* Physical Memory map */
 #define CONFIG_SYS_TEXT_BASE           0x4000000
 
-#define CONFIG_NR_DRAM_BANKS           1
+#ifndef CONFIG_NR_DRAM_BANKS
+# define CONFIG_NR_DRAM_BANKS          1
+#endif
 
 #define CONFIG_SYS_MEMTEST_START       0
 #define CONFIG_SYS_MEMTEST_END         0x1000