mx5: lowlevel_init.S: Split init_clock macro

init_clock is currently shared between mx51 and mx53 and it contains lots of
ifdef's which makes it really hard to follow the code.

Split the init_clock between mx51 and mx53 to allow easier readability.

No functional changes are made.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>

diff --git a/arch/arm/cpu/armv7/mx5/lowlevel_init.S b/arch/arm/cpu/armv7/mx5/lowlevel_init.S
index 529e35b4405aa5f611e5232ad8c6dec49bd4eb91..d0bab4545a2d16763a7d96e17149b69f3e2913dd 100644 (file)
--- a/arch/arm/cpu/armv7/mx5/lowlevel_init.S
+++ b/arch/arm/cpu/armv7/mx5/lowlevel_init.S
@@ -162,9 +162,9 @@ setup_pll_func:
 .endm
 
 .macro init_clock
+#if defined (CONFIG_MX51)
        ldr r0, =CCM_BASE_ADDR
 
-#if defined(CONFIG_MX51)
        /* Gate of clocks to the peripherals first */
        ldr r1, =0x3FFFFFFF
        str r1, [r0, #CLKCTL_CCGR0]
@@ -190,21 +190,6 @@ setup_pll_func:
 1:     ldr r1, [r0, #CLKCTL_CDHIPR]
        cmp r1, #0x0
        bne 1b
-#else
-       ldr r1, =0x3FFFFFFF
-       str r1, [r0, #CLKCTL_CCGR0]
-       str r4, [r0, #CLKCTL_CCGR1]
-       str r4, [r0, #CLKCTL_CCGR2]
-       str r4, [r0, #CLKCTL_CCGR3]
-       str r4, [r0, #CLKCTL_CCGR7]
-
-       ldr r1, =0x00030000
-       str r1, [r0, #CLKCTL_CCGR4]
-       ldr r1, =0x00FFF030
-       str r1, [r0, #CLKCTL_CCGR5]
-       ldr r1, =0x0F00030F
-       str r1, [r0, #CLKCTL_CCGR6]
-#endif
 
        /* Switch ARM to step clock */
        mov r1, #0x4
@@ -217,7 +202,6 @@ setup_pll_func:
        setup_pll PLL1_BASE_ADDR, 800
 #endif
 
-#if defined(CONFIG_MX51)
        setup_pll PLL3_BASE_ADDR, 665
 
        /* Switch peripheral to PLL 3 */
@@ -234,7 +218,7 @@ setup_pll_func:
        str r1, [r0, #CLKCTL_CBCDR]
        ldr r1, =0x000020C0 | CONFIG_SYS_DDR_CLKSEL
        str r1, [r0, #CLKCTL_CBCMR]
-#endif
+
        setup_pll PLL3_BASE_ADDR, 216
 
        /* Set the platform clock dividers */
@@ -244,21 +228,17 @@ setup_pll_func:
 
        ldr r0, =CCM_BASE_ADDR
 
-#if defined(CONFIG_MX51)
        /* Run 3.0 at Full speed, for other TO's wait till we increase VDDGP */
        ldr r3, [r4, #ROM_SI_REV]
        cmp r3, #0x10
        movls r1, #0x1
        movhi r1, #0
-#else
-       mov r1, #0
-#endif
+
        str r1, [r0, #CLKCTL_CACRR]
 
        /* Switch ARM back to PLL 1 */
        str r4, [r0, #CLKCTL_CCSR]
 
-#if defined(CONFIG_MX51)
        /* setup the rest */
        /* Use lp_apm (24MHz) source for perclk */
        ldr r1, =0x000020C2 | CONFIG_SYS_DDR_CLKSEL
@@ -266,7 +246,6 @@ setup_pll_func:
        /* ddr clock from PLL 1, all perclk dividers are 1 since using 24MHz */
        ldr r1, =CONFIG_SYS_CLKTL_CBCDR
        str r1, [r0, #CLKCTL_CBCDR]
-#endif
 
        /* Restore the default values in the Gate registers */
        ldr r1, =0xFFFFFFFF
@@ -277,17 +256,72 @@ setup_pll_func:
        str r1, [r0, #CLKCTL_CCGR4]
        str r1, [r0, #CLKCTL_CCGR5]
        str r1, [r0, #CLKCTL_CCGR6]
-#if defined(CONFIG_MX53)
-       str r1, [r0, #CLKCTL_CCGR7]
-#endif
 
-#if defined(CONFIG_MX51)
        /* Use PLL 2 for UART's, get 66.5MHz from it */
        ldr r1, =0xA5A2A020
        str r1, [r0, #CLKCTL_CSCMR1]
        ldr r1, =0x00C30321
        str r1, [r0, #CLKCTL_CSCDR1]
-#elif defined(CONFIG_MX53)
+       /* make sure divider effective */
+1:     ldr r1, [r0, #CLKCTL_CDHIPR]
+       cmp r1, #0x0
+       bne 1b
+
+       str r4, [r0, #CLKCTL_CCDR]
+
+       /* for cko - for ARM div by 8 */
+       mov r1, #0x000A0000
+       add r1, r1, #0x00000F0
+       str r1, [r0, #CLKCTL_CCOSR]
+#else  /* CONFIG_MX53 */
+       ldr r0, =CCM_BASE_ADDR
+
+       /* Gate of clocks to the peripherals first */
+       ldr r1, =0x3FFFFFFF
+       str r1, [r0, #CLKCTL_CCGR0]
+       str r4, [r0, #CLKCTL_CCGR1]
+       str r4, [r0, #CLKCTL_CCGR2]
+       str r4, [r0, #CLKCTL_CCGR3]
+       str r4, [r0, #CLKCTL_CCGR7]
+       ldr r1, =0x00030000
+       str r1, [r0, #CLKCTL_CCGR4]
+       ldr r1, =0x00FFF030
+       str r1, [r0, #CLKCTL_CCGR5]
+       ldr r1, =0x0F00030F
+       str r1, [r0, #CLKCTL_CCGR6]
+
+       /* Switch ARM to step clock */
+       mov r1, #0x4
+       str r1, [r0, #CLKCTL_CCSR]
+
+       setup_pll PLL1_BASE_ADDR, 800
+
+       setup_pll PLL3_BASE_ADDR, 216
+
+       /* Set the platform clock dividers */
+       ldr r0, =ARM_BASE_ADDR
+       ldr r1, =0x00000725
+       str r1, [r0, #0x14]
+
+       ldr r0, =CCM_BASE_ADDR
+
+       mov r1, #0
+       str r1, [r0, #CLKCTL_CACRR]
+
+       /* Switch ARM back to PLL 1 */
+       str r4, [r0, #CLKCTL_CCSR]
+
+       /* Restore the default values in the Gate registers */
+       ldr r1, =0xFFFFFFFF
+       str r1, [r0, #CLKCTL_CCGR0]
+       str r1, [r0, #CLKCTL_CCGR1]
+       str r1, [r0, #CLKCTL_CCGR2]
+       str r1, [r0, #CLKCTL_CCGR3]
+       str r1, [r0, #CLKCTL_CCGR4]
+       str r1, [r0, #CLKCTL_CCGR5]
+       str r1, [r0, #CLKCTL_CCGR6]
+       str r1, [r0, #CLKCTL_CCGR7]
+
        /* Switch peripheral to PLL2 */
        ldr r0, =CCM_BASE_ADDR
        ldr r1, =0x00808145
@@ -306,7 +340,7 @@ setup_pll_func:
        and r1, r1, #0xffffffc0
        orr r1, r1, #0x0a
        str r1, [r0, #CLKCTL_CSCDR1]
-#endif
+
        /* make sure divider effective */
 1:     ldr r1, [r0, #CLKCTL_CDHIPR]
        cmp r1, #0x0
@@ -318,6 +352,7 @@ setup_pll_func:
        mov r1, #0x000A0000
        add r1, r1, #0x00000F0
        str r1, [r0, #CLKCTL_CCOSR]
+#endif /* CONFIG_MX53 */
 .endm
 
 .macro setup_wdog