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ld/ARM: Increase maximum page size to 64kB
authorWill Newton <will.newton@linaro.org>
Thu, 26 Jun 2014 14:23:31 +0000 (15:23 +0100)
committerWill Newton <will.newton@linaro.org>
Tue, 8 Jul 2014 14:00:12 +0000 (15:00 +0100)
Increase the maximum page size to 64kB and align the TEXT_START_ADDR
to a 64kB boundary. This brings AArch32 in line with AArch64 and
improves compatability under certain conditions.

bfd/ChangeLog:

2014-07-08  Will Newton  <will.newton@linaro.org>

* elf32-arm.c (ELF_MAXPAGESIZE): Increase the default
value to 64kB and remove custom setting for NaCl.

ld/ChangeLog:

2014-07-08  Will Newton  <will.newton@linaro.org>

* emulparams/armelf_linux.sh (TEXT_START_ADDR): Increase
alignment to 64kB boundary.

ld/testsuite/ChangeLog:

2014-07-08  Will Newton  <will.newton@linaro.org>

* ld-arm/arm-lib.ld: Increase MAXPAGESIZE value to
match bfd.
* ld-arm/cortex-a8-fix-bl-rel-plt.d: Update offsets to
take into account increased segment alignment.
* ld-arm/ifunc-gdesc.r: Likewise.
* ld-arm/tls-lib.d: Likewise.

bfd/ChangeLog patch | blob | history
bfd/elf32-arm.c patch | blob | history
ld/ChangeLog patch | blob | history
ld/emulparams/armelf_linux.sh patch | blob | history
ld/testsuite/ChangeLog patch | blob | history
ld/testsuite/ld-arm/arm-lib.ld patch | blob | history
ld/testsuite/ld-arm/cortex-a8-fix-bl-rel-plt.d patch | blob | history
ld/testsuite/ld-arm/ifunc-gdesc.r patch | blob | history
ld/testsuite/ld-arm/tls-lib.d patch | blob | history

diff --git a/bfd/ChangeLog b/bfd/ChangeLog
index 48280c4..edf983a 100644 (file)
--- a/bfd/ChangeLog
+++ b/bfd/ChangeLog
@@ -1,3 +1,8 @@
+2014-07-08  Will Newton  <will.newton@linaro.org>
+
+       * elf32-arm.c (ELF_MAXPAGESIZE): Increase the default
+       value to 64kB and remove custom setting for NaCl.
+
 2014-07-08  Alan Modra  <amodra@gmail.com>
 
        * elflink.c (_bfd_elf_copy_link_hash_symbol_type): Copy st_other
diff --git a/bfd/elf32-arm.c b/bfd/elf32-arm.c
index 1c6965e..e6f4a9f 100644 (file)
--- a/bfd/elf32-arm.c
+++ b/bfd/elf32-arm.c
@@ -16100,7 +16100,7 @@ elf32_arm_get_synthetic_symtab (bfd *abfd,
 #ifdef __QNXTARGET__
 #define ELF_MAXPAGESIZE                        0x1000
 #else
-#define ELF_MAXPAGESIZE                        0x8000
+#define ELF_MAXPAGESIZE                        0x10000
 #endif
 #define ELF_MINPAGESIZE                        0x1000
 #define ELF_COMMONPAGESIZE             0x1000
@@ -16250,8 +16250,6 @@ elf32_arm_nacl_plt_sym_val (bfd_vma i, const asection *plt,
 #undef  elf_backend_plt_sym_val
 #define elf_backend_plt_sym_val                        elf32_arm_nacl_plt_sym_val
 
-#undef ELF_MAXPAGESIZE
-#define ELF_MAXPAGESIZE                        0x10000
 #undef ELF_MINPAGESIZE
 #undef ELF_COMMONPAGESIZE
 
diff --git a/ld/ChangeLog b/ld/ChangeLog
index 20e5bb4..c1ab4a1 100644 (file)
--- a/ld/ChangeLog
+++ b/ld/ChangeLog
@@ -1,3 +1,8 @@
+2014-07-08  Will Newton  <will.newton@linaro.org>
+
+       * emulparams/armelf_linux.sh (TEXT_START_ADDR): Increase
+       alignment to 64kB boundary.
+
 2014-07-04  Alan Modra  <amodra@gmail.com>
 
        * configure.ac: Update "configure.in" comments.
diff --git a/ld/emulparams/armelf_linux.sh b/ld/emulparams/armelf_linux.sh
index 35891f1..280db84 100644 (file)
--- a/ld/emulparams/armelf_linux.sh
+++ b/ld/emulparams/armelf_linux.sh
@@ -17,7 +17,7 @@ OTHER_BSS_END_SYMBOLS='_bss_end__ = . ; __bss_end__ = . ;'
 OTHER_END_SYMBOLS='__end__ = . ;'
 OTHER_SECTIONS='.note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) }'
 
-TEXT_START_ADDR=0x00008000
+TEXT_START_ADDR=0x00010000
 TARGET2_TYPE=got-rel
 
 # ARM does not support .s* sections.
diff --git a/ld/testsuite/ChangeLog b/ld/testsuite/ChangeLog
index 340c23f..8cafff0 100644 (file)
--- a/ld/testsuite/ChangeLog
+++ b/ld/testsuite/ChangeLog
@@ -1,3 +1,12 @@
+2014-07-08  Will Newton  <will.newton@linaro.org>
+
+       * ld-arm/arm-lib.ld: Increase MAXPAGESIZE value to
+       match bfd.
+       * ld-arm/cortex-a8-fix-bl-rel-plt.d: Update offsets to
+       take into account increased segment alignment.
+       * ld-arm/ifunc-gdesc.r: Likewise.
+       * ld-arm/tls-lib.d: Likewise.
+
 2014-07-08  Jiong Wang  <jiong.wang@arm.com>
 
        * ld-aarch64/emit-relocs-local-addend-bar.s: New source file.
diff --git a/ld/testsuite/ld-arm/arm-lib.ld b/ld/testsuite/ld-arm/arm-lib.ld
index f158c23..f946d0a 100644 (file)
--- a/ld/testsuite/ld-arm/arm-lib.ld
+++ b/ld/testsuite/ld-arm/arm-lib.ld
@@ -75,7 +75,7 @@ SECTIONS
   .gcc_except_table   : ONLY_IF_RO { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) }
   /* Adjust the address for the data segment.  We want to adjust up to
      the same address within the page on the next page up.  */
-  . = ALIGN (0x8000) - ((0x8000 - .) & (0x8000 - 1)); . = DATA_SEGMENT_ALIGN (0x8000, 0x1000);
+  . = ALIGN (0x10000) - ((0x10000 - .) & (0x10000 - 1)); . = DATA_SEGMENT_ALIGN (0x10000, 0x1000);
   /* Exception handling  */
   .eh_frame       : ONLY_IF_RW { KEEP (*(.eh_frame)) }
   .gcc_except_table   : ONLY_IF_RW { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) }
diff --git a/ld/testsuite/ld-arm/cortex-a8-fix-bl-rel-plt.d b/ld/testsuite/ld-arm/cortex-a8-fix-bl-rel-plt.d
index e2fd8ac..ba1f537 100644 (file)
--- a/ld/testsuite/ld-arm/cortex-a8-fix-bl-rel-plt.d
+++ b/ld/testsuite/ld-arm/cortex-a8-fix-bl-rel-plt.d
@@ -9,10 +9,10 @@ Disassembly of section \.plt:
     8e04:      e59fe004        ldr     lr, \[pc, #4\]  ; 8e10 <targetfn@plt-0x4>
     8e08:      e08fe00e        add     lr, pc, lr
     8e0c:      e5bef008        ldr     pc, \[lr, #8\]!
-    8e10:      0000827c        \.word  0x0000827c
+    8e10:      0001027c        \.word  0x0001027c
 00008e14 <targetfn@plt>:
     8e14:      e28fc600        add     ip, pc, #0, 12
-    8e18:      e28cca08        add     ip, ip, #8, 20  ; 0x8000
+    8e18:      e28cca10        add     ip, ip, #16, 20 ; 0x10000
     8e1c:      e5bcf27c        ldr     pc, \[ip, #636\]!       ; 0x27c
 
 Disassembly of section \.text:
diff --git a/ld/testsuite/ld-arm/ifunc-gdesc.r b/ld/testsuite/ld-arm/ifunc-gdesc.r
index a49dd2b..20f5ccc 100644 (file)
--- a/ld/testsuite/ld-arm/ifunc-gdesc.r
+++ b/ld/testsuite/ld-arm/ifunc-gdesc.r
@@ -1,6 +1,6 @@
 tmpdir/ifunc-gdesc.so:     file format elf32-(big|little)arm
 DYNAMIC RELOCATION RECORDS
 OFFSET   TYPE              VALUE 
-0000825c R_ARM_IRELATIVE   \*ABS\*
-00008248 R_ARM_TLS_DESC    \*ABS\*
-00008250 R_ARM_TLS_DESC    \*ABS\*
+0001025c R_ARM_IRELATIVE   \*ABS\*
+00010248 R_ARM_TLS_DESC    \*ABS\*
+00010250 R_ARM_TLS_DESC    \*ABS\*
diff --git a/ld/testsuite/ld-arm/tls-lib.d b/ld/testsuite/ld-arm/tls-lib.d
index a299fba..440d1d3 100644 (file)
--- a/ld/testsuite/ld-arm/tls-lib.d
+++ b/ld/testsuite/ld-arm/tls-lib.d
@@ -10,6 +10,6 @@ Disassembly of section .text:
  .*:   e1a00000        nop                     ; \(mov r0, r0\)
  .*:   e1a00000        nop                     ; \(mov r0, r0\)
  .*:   e1a0f00e        mov     pc, lr
- .*:   00008098        .word   0x00008098
- .*:   0000808c        .word   0x0000808c
+ .*:   00010098        .word   0x00010098
+ .*:   0001008c        .word   0x0001008c
  .*:   00000004        .word   0x00000004
Domain: System / Toolchain;