hdmirx: set rxsense sync with pddq for tl1 [1/1]

PD#SWPL-5668

Problem:
recognized as dvi after suspend/resume
when connect xiaomi mtk box

Solution:
when resume, add rxsense pulse to avoid
sda pulled low by xiaomi mtk box

Verify:
TL1-T962X2_X301

Change-Id: I480cbb4376bbb0c3b38318df2e26f5cc85db3d59
Signed-off-by: Hang Cheng <hang.cheng@amlogic.com>

diff --git a/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_drv.c b/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_drv.c
index 867837a..8477643 100644 (file)
--- a/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_drv.c
+++ b/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_drv.c
@@ -1718,7 +1718,7 @@ static void rx_phy_resume(void)
                         * rxsense pulse and phy_int shottern than
                         * 50ms, SDA may be pulled low 800ms on MTK box
                         */
-                       rx_phy_rxsense_pulse(20, 50, 1);
+                       rx_phy_rxsense_pulse(10, 50, 1);
                }
        }
        hdmirx_phy_init();

diff --git a/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_drv.h b/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_drv.h
index f298ed8..abcf9fe 100644 (file)
--- a/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_drv.h
+++ b/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_drv.h
@@ -41,7 +41,7 @@
  *
  *
  */
-#define RX_VER1 "ver.2019/03/14"
+#define RX_VER1 "ver.2019/03/15"
 /*
  *
  *

diff --git a/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_hw.c b/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_hw.c
index 6bf4b2d..9a48d1a 100644 (file)
--- a/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_hw.c
+++ b/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_hw.c
@@ -700,8 +700,19 @@ unsigned int rx_set_hdcp14_secure_key(void)
  */
 void hdmirx_phy_pddq(unsigned int enable)
 {
-       if (rx.chip_id == CHIP_ID_TL1)
+       uint32_t term_value =
+               hdmirx_rd_top(TOP_HPD_PWR5V) & 0x7;
+
+       if (rx.chip_id == CHIP_ID_TL1) {
                wr_reg_hhi_bits(HHI_HDMIRX_PHY_MISC_CNTL2, _BIT(1), enable);
+               /* set rxsense */
+               if (enable)
+                       wr_reg_hhi_bits(HHI_HDMIRX_PHY_MISC_CNTL0,
+                               MSK(3, 0), 0);
+               else
+                       wr_reg_hhi_bits(HHI_HDMIRX_PHY_MISC_CNTL0,
+                               MSK(3, 0), term_value);
+       }
        else
                hdmirx_wr_bits_dwc(DWC_SNPS_PHYG3_CTRL,
                        MSK(1, 1), enable);