};
+ dwc3: dwc3@ff500000 {
+ compatible = "synopsys, dwc3";
+ status = "disabled";
+ reg = <0xff500000 0x100000>;
+ interrupts = <0 30 4>;
+ usb-phy = <&usb2_phy_v2>, <&usb3_phy_v2>;
+ cpu-type = "gxl";
+ clock-src = "usb3.0";
+ clocks = <&clkc CLKID_USB_GENERAL>;
+ clock-names = "dwc_general";
+ };
+
+ usb2_phy_v2: usb2phy@ffe09000 {
+ compatible = "amlogic, amlogic-new-usb2-v2";
+ status = "disabled";
+ reg = <0xffe09000 0x80
+ 0xffd01008 0x100
+ 0xff636000 0x2000
+ 0xff63a000 0x2000
+ 0xff658000 0x2000>;
+ pll-setting-1 = <0x09400414>;
+ pll-setting-2 = <0x927E0000>;
+ pll-setting-3 = <0xac5f69e5>;
+ pll-setting-4 = <0xfe18>;
+ pll-setting-5 = <0x8000fff>;
+ pll-setting-6 = <0x78000>;
+ pll-setting-7 = <0xe0004>;
+ pll-setting-8 = <0xe000c>;
+ version = <1>;
+ };
+
+ usb3_phy_v2: usb3phy@ffe09080 {
+ compatible = "amlogic, amlogic-new-usb3-v2";
+ status = "disabled";
+ reg = <0xffe09080 0x20>;
+ phy-reg = <0xff646000>;
+ phy-reg-size = <0x2000>;
+ usb2-phy-reg = <0xffe09000>;
+ usb2-phy-reg-size = <0x80>;
+ interrupts = <0 16 4>;
+ };
+
+ dwc2_a: dwc2_a@ff400000 {
+ compatible = "amlogic, dwc2";
+ status = "disabled";
+ device_name = "dwc2_a";
+ reg = <0xff400000 0x40000>;
+ interrupts = <0 31 4>;
+ pl-periph-id = <0>; /** lm name */
+ clock-src = "usb0"; /** clock src */
+ port-id = <0>; /** ref to mach/usb.h */
+ port-type = <2>; /** 0: otg, 1: host, 2: slave */
+ port-speed = <0>; /** 0: default, high, 1: full */
+ port-config = <0>; /** 0: default */
+ /*0:default,1:single,2:incr,3:incr4,4:incr8,5:incr16,6:disable*/
+ port-dma = <0>;
+ port-id-mode = <0>; /** 0: hardware, 1: sw_host, 2: sw_slave*/
+ usb-fifo = <728>;
+ cpu-type = "v2";
+ phy-reg = <0xffe09000>;
+ phy-reg-size = <0xa0>;
+ /** phy-interface: 0x0: amlogic-v1 phy, 0x1: synopsys phy **/
+ /** 0x2: amlogic-v2 phy **/
+ phy-interface = <0x2>;
+ clocks = <&clkc CLKID_USB_GENERAL
+ &clkc CLKID_USB1_TO_DDR>;
+ clock-names = "usb_general",
+ "usb1";
+ };
+
wdt: watchdog@0xffd0f0d0 {
compatible = "amlogic,meson-tl1-wdt";
status = "okay";
};
};
+&dwc3 {
+ status = "okay";
+};
+
+&usb2_phy_v2 {
+ status = "okay";
+ portnum = <3>;
+};
+
+&usb3_phy_v2 {
+ status = "okay";
+ portnum = <0>;
+ otg = <0>;
+};
+
+&dwc2_a {
+ status = "okay";
+ /** 0: normal, 1: otg+dwc3 host only, 2: otg+dwc3 device only*/
+ controller-type = <1>;
+};
+
&spicc0 {
status = "okay";
pinctrl-names = "default";
status = "okay";
};
+&dwc3 {
+ status = "okay";
+};
+
+&usb2_phy_v2 {
+ status = "okay";
+ portnum = <3>;
+};
+
+&usb3_phy_v2 {
+ status = "okay";
+ portnum = <0>;
+ otg = <0>;
+};
+
+&dwc2_a {
+ status = "okay";
+ /** 0: normal, 1: otg+dwc3 host only, 2: otg+dwc3 device only*/
+ controller-type = <1>;
+};
+
&spicc0 {
status = "okay";
pinctrl-names = "default";
status = "okay";
};
+&dwc3 {
+ status = "okay";
+};
+
+&usb2_phy_v2 {
+ status = "okay";
+ portnum = <3>;
+};
+
+&usb3_phy_v2 {
+ status = "okay";
+ portnum = <0>;
+ otg = <0>;
+};
+
+&dwc2_a {
+ status = "okay";
+ /** 0: normal, 1: otg+dwc3 host only, 2: otg+dwc3 device only*/
+ controller-type = <1>;
+};
+
&spicc0 {
status = "okay";
pinctrl-names = "default";
return -DWC_E_INVALID;
}
if (val >
- (DWC_READ_REG32(&core_if->core_global_regs->dtxfsiz[fifo_num]) >> 16)) {
- DWC_WARN("Value is larger then power-on FIFO size\n");
+ (DWC_READ_REG32
+ (&core_if->core_global_regs->dtxfsiz[fifo_num]) >> 16)) {
+ if (DWC_READ_REG32
+ (&core_if->core_global_regs->dtxfsiz[fifo_num]) >> 16)
+ DWC_WARN("Value is larger then power-on FIFO size\n");
if (dwc_otg_param_initialized
(core_if->core_params->dev_perio_tx_fifo_size[fifo_num]))
DWC_ERROR
return -DWC_E_INVALID;
}
if (val > txfifosize.b.depth) {
- DWC_WARN("Value is larger then power-on FIFO size\n");
+ if (txfifosize.b.depth)
+ DWC_WARN("Value is larger then power-on FIFO size\n");
if (dwc_otg_param_initialized
(core_if->core_params->dev_tx_fifo_size[fifo_num]))
DWC_ERROR
DWC_DEBUGPL(DBG_PCD, "SPEED ENUM\n");
#ifdef CONFIG_AMLOGIC_USB3PHY
- if (GET_CORE_IF(pcd)->phy_interface == 0) {
+ if (GET_CORE_IF(pcd)->phy_interface != 1) {
speed = get_device_speed(GET_CORE_IF(pcd));
if (speed != USB_SPEED_HIGH) {
gintsts.d32 = 0;
if (value) {
DWC_DEBUGPL(DBG_PCDV, "start usb device\n");
dwc_otg_enable_global_interrupts(otg_dev->core_if);
- if (otg_dev->core_if->phy_interface == 0)
+ if (otg_dev->core_if->phy_interface != 0)
dwc_otg_enable_device_interrupts(otg_dev->core_if);
otg_dev->pcd->core_if->pcd_cb->start(otg_dev->pcd);
} else {
dwc_otg_disable_global_interrupts(otg_dev->core_if);
/* Disable all interrupts. */
- if (otg_dev->core_if->phy_interface == 0)
+ if (otg_dev->core_if->phy_interface != 0)
DWC_WRITE_REG32(&global_regs->gintmsk, 0);
otg_dev->pcd->core_if->pcd_cb->stop(otg_dev->pcd);
if (!g_phy2_v2)
return;
+
+ if (g_phy2_v2->phy_version == 1)
+ return;
+
if (port > g_phy2_v2->portnum)
return;
if (default_val == g_phy2_v2->phy_cfg_state[port])
if (!g_phy2_v2)
return;
+
+ if (g_phy2_v2->phy_version == 1)
+ return;
+
if (port > g_phy2_v2->portnum)
return;
if (default_val == g_phy2_v2->phy_cfg_state[port])
union u2p_r0_v2 reg0;
union u2p_r1_v2 reg1;
u32 val;
+ u32 temp = 0;
+ u32 portnum = phy->portnum;
+
+ while (portnum--)
+ temp = temp | (1 << (16 + portnum));
val = readl((void __iomem *)
((unsigned long)phy->reset_regs + (0x21 * 4 - 0x8)));
- writel((val | (0x3 << 16)), (void __iomem *)
+ writel((val | temp), (void __iomem *)
((unsigned long)phy->reset_regs + (0x21 * 4 - 0x8)));
amlogic_new_usbphy_reset_v2(phy);
{
struct amlogic_usb_v2 *phy = phy_to_amlusb(x);
u32 val;
+ u32 temp = 0;
+ u32 cnt = phy->portnum;
+
+ while (cnt--)
+ temp = temp | (1 << (16 + cnt));
/* set usb phy to low power mode */
val = readl((void __iomem *)
((unsigned long)phy->reset_regs + (0x21 * 4 - 0x8)));
- writel((val & (~(0x3 << 16))), (void __iomem *)
+ writel((val & (~temp)), (void __iomem *)
((unsigned long)phy->reset_regs + (0x21 * 4 - 0x8)));
phy->suspend_flag = 1;
void __iomem *reset_base = NULL;
void __iomem *phy_cfg_base[4];
int portnum = 0;
+ int phy_version = 0;
const void *prop;
int i = 0;
int retval;
return -ENOMEM;
}
+ prop = of_get_property(dev->of_node, "version", NULL);
+ if (prop)
+ phy_version = of_read_ulong(prop, 1);
+ else
+ phy_version = 0;
+
phy_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
phy_base = devm_ioremap_resource(dev, phy_mem);
if (IS_ERR(phy_base))
phy->pll_setting[6] = pll_setting[6];
phy->pll_setting[7] = pll_setting[7];
phy->suspend_flag = 0;
+ phy->phy_version = phy_version;
for (i = 0; i < portnum; i++) {
phy->phy_cfg[i] = phy_cfg_base[i];
/* set port default tuning state */
if (!virt_dev)
return -EINVAL;
if (!command)
- command = xhci_alloc_command(xhci, false, false, GFP_KERNEL);
+ command = xhci_alloc_command(xhci, false, false, GFP_ATOMIC);
if (!command)
return -ENOMEM;
{
__le32 __iomem **port_array;
u32 temp;
- unsigned long flags = 0;
port_array = xhci->usb2_ports;
temp = readl(port_array[index]);
/* Power off */
writel(temp & ~PORT_POWER, port_array[index]);
}
-
- spin_unlock_irqrestore(&xhci->lock, flags);
- temp = usb_acpi_power_manageable(hcd->self.root_hub,
- index);
- if (temp)
- usb_acpi_set_power_state(hcd->self.root_hub,
- index, on);
- spin_lock_irqsave(&xhci->lock, flags);
}
__le32 __iomem **port_array = xhci->usb2_ports;
/* 15 second delay per the test spec */
- spin_unlock_irqrestore(&xhci->lock, flags);
xhci_err(xhci, "into suspend\n");
spin_lock_irqsave(&xhci->lock, flags);
temp = readl(port_array[wIndex]);
if ((temp & PORT_PE) == 0 || (temp & PORT_RESET)
|| (temp & PORT_PLS_MASK) >= XDEV_U3) {
+ spin_unlock_irqrestore(&xhci->lock, flags);
xhci_warn(xhci, "USB core suspending device not in U0/U1/U2.\n");
return -1;
}
slot_id = xhci_find_slot_id_by_port(hcd, xhci,
wIndex + 1);
if (!slot_id) {
+ spin_unlock_irqrestore(&xhci->lock, flags);
xhci_warn(xhci, "slot_id is zero\n");
return -1;
}
temp = readl(port_array[wIndex]);
xhci_dbg(xhci, "clear USB_PORT_FEAT_SUSPEND\n");
xhci_dbg(xhci, "PORTSC %04x\n", temp);
- if (temp & PORT_RESET)
+ if (temp & PORT_RESET) {
+ spin_unlock_irqrestore(&xhci->lock, flags);
return -1;
+ }
if ((temp & PORT_PLS_MASK) == XDEV_U3) {
- if ((temp & PORT_PE) == 0)
+ if ((temp & PORT_PE) == 0) {
+ spin_unlock_irqrestore(&xhci->lock, flags);
return -1;
+ }
xhci_set_link_state(xhci, port_array, wIndex,
XDEV_RESUME);
}
xhci_ring_device(xhci, slot_id);
+ spin_unlock_irqrestore(&xhci->lock, flags);
return 0;
}
#endif
else if (test_mode == 5)
xhci_port_set_test_mode(xhci,
test_mode, wIndex);
- else
+ else {
+ spin_unlock_irqrestore(&xhci->lock, flags);
retval = xhci_test_suspend_resume(hcd, wIndex);
+ spin_lock_irqsave(&xhci->lock, flags);
+ }
break;
#endif
default:
struct xhci_td *td;
unsigned long flags = 0;
+ spin_lock_irqsave(&xhci->lock, flags);
+
ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
- if (!ep_ring)
+ if (!ep_ring) {
+ spin_unlock_irqrestore(&xhci->lock, flags);
return -EINVAL;
+ }
/*
* Need to copy setup packet into setup TRB, so we can't use the setup
* DMA address.
*/
- if (!urb->setup_packet)
+ if (!urb->setup_packet) {
+ spin_unlock_irqrestore(&xhci->lock, flags);
return -EINVAL;
+ }
/* 1 TRB for setup, 1 for status */
num_trbs = 2;
ret = prepare_transfer(xhci, xhci->devs[slot_id],
ep_index, urb->stream_id,
num_trbs, urb, 0, mem_flags);
- if (ret < 0)
+ if (ret < 0) {
+ spin_unlock_irqrestore(&xhci->lock, flags);
return ret;
+ }
urb_priv = urb->hcpriv;
td = urb_priv->td[0];
giveback_first_trb(xhci, slot_id, ep_index, 0,
start_cycle, start_trb);
- /* 15 second delay per the test spec */
- spin_unlock_irqrestore(&xhci->lock, flags);
- xhci_err(xhci, "step 3\n");
- msleep(15000);
- spin_lock_irqsave(&xhci->lock, flags);
+ /* 15 second delay per the test spec */
+ spin_unlock_irqrestore(&xhci->lock, flags);
+ xhci_err(xhci, "step 3\n");
+ msleep(15000);
return 0;
-
}
#endif
&& (setup->wIndex != 0x0)) {
if ((((setup->wIndex)>>8) & 0xff) == 7) {
setup->wIndex = 0;
+ spin_unlock_irqrestore(&xhci->lock, flags);
ret = xhci_test_single_step(xhci,
GFP_ATOMIC, urb,
slot_id, ep_index, 1);
+ spin_lock_irqsave(&xhci->lock, flags);
} else if ((((setup->wIndex)>>8)&0xff) == 8) {
setup->wIndex = 0;
+ spin_unlock_irqrestore(&xhci->lock, flags);
ret = xhci_test_single_step(xhci,
GFP_ATOMIC, urb,
slot_id, ep_index, 2);
+ spin_lock_irqsave(&xhci->lock, flags);
}
} else
#endif
int portnum;
int suspend_flag;
+ int phy_version;
struct clk *clk;
};