;; A strict_low_part pattern.
+;; Note the use of (match_dup 0) for the first operand of the operation
+;; here. Reload can't handle an operand pair where one is read-write
+;; and must match a read, like in:
+;; (insn 80 79 81 4
+;; (set (strict_low_part
+;; (subreg:QI (reg/v:SI 0 r0 [orig:36 data ] [36]) 0))
+;; (and:QI
+;; (subreg:QI (reg:SI 15 acr [orig:27 D.7531 ] [27]) 0)
+;; (const_int -64 [0xf..fc0]))) x.c:126 147 {*andqi_lowpart_v32}
+;; (nil))
+;; In theory, it could reload this as a movstrictqi of the register
+;; operand at the and:QI to the destination register and change the
+;; and:QI operand to the same as the read-write output operand and the
+;; result would be recognized, but it doesn't recognize that's a valid
+;; reload for a strict_low_part-destination; it just sees a "+" at the
+;; destination constraints. Better than adding complexity to reload is
+;; to follow the lead of m68k (see comment that begins with "These insns
+;; must use MATCH_DUP") since prehistoric times and make it just a
+;; match_dup. FIXME: a sanity-check in gen* to refuse an insn with
+;; input-constraints matching input-output-constraints, e.g. "+r" <- "0".
+
(define_insn "*andhi_lowpart_non_v32"
[(set (strict_low_part
- (match_operand:HI 0 "register_operand" "+r,r, r,r,r,r"))
- (and:HI (match_operand:HI 1 "register_operand" "%0,0, 0,0,0,r")
- (match_operand:HI 2 "general_operand" "r,Q>,L,O,g,!To")))]
+ (match_operand:HI 0 "register_operand" "+r,r,r"))
+ (and:HI (match_dup 0)
+ (match_operand:HI 1 "general_operand" "r,Q>,g")))]
"!TARGET_V32"
"@
- and.w %2,%0
- and.w %2,%0
- and.w %2,%0
- anDq %b2,%0
- and.w %2,%0
- and.w %2,%1,%0"
- [(set_attr "slottable" "yes,yes,no,yes,no,no")
- (set_attr "cc" "normal,normal,normal,clobber,normal,normal")])
+ and.w %1,%0
+ and.w %1,%0
+ and.w %1,%0"
+ [(set_attr "slottable" "yes,yes,no")])
(define_insn "*andhi_lowpart_v32"
[(set (strict_low_part
- (match_operand:HI 0 "register_operand" "+r,r,r,r,r"))
- (and:HI (match_operand:HI 1 "register_operand" "%0,0,0,0,0")
- (match_operand:HI 2 "general_operand" "r,Q>,L,O,g")))]
+ (match_operand:HI 0 "register_operand" "+r,r,r"))
+ (and:HI (match_dup 0)
+ (match_operand:HI 1 "general_operand" "r,Q>,g")))]
"TARGET_V32"
"@
- and.w %2,%0
- and.w %2,%0
- and.w %2,%0
- anDq %b2,%0
- and.w %2,%0"
- [(set_attr "slottable" "yes,yes,no,yes,no")
- (set_attr "cc" "noov32,noov32,noov32,clobber,noov32")])
+ and.w %1,%0
+ and.w %1,%0
+ and.w %1,%0"
+ [(set_attr "slottable" "yes,yes,no")
+ (set_attr "cc" "noov32")])
\f
(define_expand "andqi3"
[(set (match_operand:QI 0 "register_operand")
(define_insn "*andqi_lowpart_non_v32"
[(set (strict_low_part
- (match_operand:QI 0 "register_operand" "+r,r, r,r,r"))
- (and:QI (match_operand:QI 1 "register_operand" "%0,0, 0,0,r")
- (match_operand:QI 2 "general_operand" "r,Q>,O,g,!To")))]
+ (match_operand:QI 0 "register_operand" "+r,r,r"))
+ (and:QI (match_dup 0)
+ (match_operand:QI 1 "general_operand" "r,Q>,g")))]
"!TARGET_V32"
"@
- and.b %2,%0
- and.b %2,%0
- andQ %b2,%0
- and.b %2,%0
- and.b %2,%1,%0"
- [(set_attr "slottable" "yes,yes,yes,no,no")
- (set_attr "cc" "normal,normal,clobber,normal,normal")])
+ and.b %1,%0
+ and.b %1,%0
+ and.b %1,%0"
+ [(set_attr "slottable" "yes,yes,no")])
(define_insn "*andqi_lowpart_v32"
[(set (strict_low_part
- (match_operand:QI 0 "register_operand" "+r,r,r,r"))
- (and:QI (match_operand:QI 1 "register_operand" "%0,0,0,0")
- (match_operand:QI 2 "general_operand" "r,Q>,O,g")))]
+ (match_operand:QI 0 "register_operand" "+r,r,r"))
+ (and:QI (match_dup 0)
+ (match_operand:QI 1 "general_operand" "r,Q>,g")))]
"TARGET_V32"
"@
- and.b %2,%0
- and.b %2,%0
- andQ %b2,%0
- and.b %2,%0"
- [(set_attr "slottable" "yes,yes,yes,no")
- (set_attr "cc" "noov32,noov32,clobber,noov32")])
+ and.b %1,%0
+ and.b %1,%0
+ and.b %1,%0"
+ [(set_attr "slottable" "yes,yes,no")
+ (set_attr "cc" "noov32")])
\f
;; Bitwise or.